drm/amdgpu: add soc15 common ip block support for renoir

This patch adds common ip support for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui
2019-07-24 13:39:36 -05:00
committed by Alex Deucher
parent b51a26a02a
commit 080deab66d

View File

@@ -637,6 +637,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_RENOIR:
vega10_reg_base_init(adev); vega10_reg_base_init(adev);
break; break;
case CHIP_VEGA20: case CHIP_VEGA20:
@@ -1133,6 +1134,11 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x32; adev->external_rev_id = adev->rev_id + 0x32;
break; break;
case CHIP_RENOIR:
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
break;
default: default:
/* FIXME: not supported yet */ /* FIXME: not supported yet */
return -EINVAL; return -EINVAL;