forked from Minki/linux
Merge existing fixes from spi/for-5.8
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commit
064e8af715
@ -34,12 +34,15 @@ properties:
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maxItems: 1
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clocks:
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maxItems: 1
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minItems: 1
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maxItems: 2
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items:
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- description: controller register bus clock
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- description: baud rate generator and delay control clock
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clock-names:
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description: input clock for the baud rate generator
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items:
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- const: core
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minItems: 1
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maxItems: 2
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if:
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properties:
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@ -51,17 +54,22 @@ if:
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then:
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properties:
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clocks:
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contains:
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items:
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- description: controller register bus clock
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- description: baud rate generator and delay control clock
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minItems: 2
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clock-names:
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minItems: 2
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items:
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- const: core
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- const: pclk
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: core
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required:
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- compatible
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- reg
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@ -588,14 +588,14 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
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return;
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if (dma->chan_tx) {
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dma_unmap_single(dma->chan_tx->device->dev, dma->tx_dma_phys,
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dma_bufsize, DMA_TO_DEVICE);
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dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
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dma->tx_dma_buf, dma->tx_dma_phys);
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dma_release_channel(dma->chan_tx);
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}
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if (dma->chan_rx) {
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dma_unmap_single(dma->chan_rx->device->dev, dma->rx_dma_phys,
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dma_bufsize, DMA_FROM_DEVICE);
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dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
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dma->rx_dma_buf, dma->rx_dma_phys);
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dma_release_channel(dma->chan_rx);
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}
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}
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@ -179,7 +179,7 @@
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struct rspi_data {
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void __iomem *addr;
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u32 max_speed_hz;
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u32 speed_hz;
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struct spi_controller *ctlr;
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struct platform_device *pdev;
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wait_queue_head_t wait;
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@ -258,8 +258,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
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rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
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/* Sets transfer bit rate */
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spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
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2 * rspi->max_speed_hz) - 1;
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spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz) - 1;
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rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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/* Disable dummy transmission, set 16-bit word access, 1 frame */
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@ -299,14 +298,14 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
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clksrc = clk_get_rate(rspi->clk);
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while (div < 3) {
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if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
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if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
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break;
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div++;
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clksrc /= 2;
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}
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/* Sets transfer bit rate */
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spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
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spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
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rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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rspi->spcmd |= div << 2;
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@ -341,7 +340,7 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
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rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
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/* Sets transfer bit rate */
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spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
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spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz);
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rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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/* Disable dummy transmission, set byte access */
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@ -949,9 +948,24 @@ static int rspi_prepare_message(struct spi_controller *ctlr,
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{
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struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
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struct spi_device *spi = msg->spi;
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const struct spi_transfer *xfer;
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int ret;
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rspi->max_speed_hz = spi->max_speed_hz;
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/*
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* As the Bit Rate Register must not be changed while the device is
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* active, all transfers in a message must use the same bit rate.
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* In theory, the sequencer could be enabled, and each Command Register
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* could divide the base bit rate by a different value.
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* However, most RSPI variants do not have Transfer Data Length
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* Multiplier Setting Registers, so each sequence step would be limited
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* to a single word, making this feature unsuitable for large
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* transfers, which would gain most from it.
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*/
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rspi->speed_hz = spi->max_speed_hz;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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if (xfer->speed_hz < rspi->speed_hz)
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rspi->speed_hz = xfer->speed_hz;
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}
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rspi->spcmd = SPCMD_SSLKP;
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if (spi->mode & SPI_CPOL)
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@ -389,9 +389,9 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
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/* Load the watchdog timeout value, 50ms is always enough. */
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
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WDG_LOAD_VAL & WDG_LOAD_MASK);
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sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
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/* Start the watchdog to reset system */
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sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
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@ -48,6 +48,10 @@
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#define SPI_TX_QUAD 0x200
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#define SPI_RX_DUAL 0x400
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#define SPI_RX_QUAD 0x800
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#define SPI_CS_WORD 0x1000
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#define SPI_TX_OCTAL 0x2000
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#define SPI_RX_OCTAL 0x4000
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#define SPI_3WIRE_HIZ 0x8000
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/*---------------------------------------------------------------------------*/
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@ -47,7 +47,7 @@ static int transfer_size;
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static int iterations;
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static int interval = 5; /* interval in seconds for showing transfer rate */
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uint8_t default_tx[] = {
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static uint8_t default_tx[] = {
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x40, 0x00, 0x00, 0x00, 0x00, 0x95,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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@ -56,8 +56,8 @@ uint8_t default_tx[] = {
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0xF0, 0x0D,
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};
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uint8_t default_rx[ARRAY_SIZE(default_tx)] = {0, };
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char *input_tx;
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static uint8_t default_rx[ARRAY_SIZE(default_tx)] = {0, };
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static char *input_tx;
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static void hex_dump(const void *src, size_t length, size_t line_size,
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char *prefix)
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@ -461,8 +461,8 @@ int main(int argc, char *argv[])
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pabort("can't get max speed hz");
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printf("spi mode: 0x%x\n", mode);
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printf("bits per word: %d\n", bits);
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printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);
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printf("bits per word: %u\n", bits);
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printf("max speed: %u Hz (%u kHz)\n", speed, speed/1000);
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if (input_tx)
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transfer_escaped_string(fd, input_tx);
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