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Renesas driver updates for v5.5 (take two)

Browse Source 
- Initial support for the R-Car M3-W+ (r8a77961) SoC,
   - A minor fix.
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Merge tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.5 (take two)

  - Initial support for the R-Car M3-W+ (r8a77961) SoC,
  - A minor fix.

* tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-sysc: Add R8A77961 support
  soc: renesas: rcar-rst: Add R8A77961 support
  soc: renesas: Identify R-Car M3-W+
  soc: renesas: Add ARCH_R8A77961 for new R-Car M3-W+
  soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W
  soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960
  soc: renesas: Add missing check for non-zero product register address
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions

Link: https://lore.kernel.org/r/20191101155842.31467-6-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-03 17:05:45 -08:00
commit 064652ad88
9 changed files with 145 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/soc/renesas/Kconfig
View File

@ -199,13 +199,24 @@ config ARCH_R8A7795
help
This enables support for the Renesas R-Car H3 SoC.
config ARCH_R8A77960
bool
select ARCH_RCAR_GEN3
select SYSC_R8A77960
config ARCH_R8A7796
bool "Renesas R-Car M3-W SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A7796
select ARCH_R8A77960
help
This enables support for the Renesas R-Car M3-W SoC.
config ARCH_R8A77961
bool "Renesas R-Car M3-W+ SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A77961
help
This enables support for the Renesas R-Car M3-W+ SoC.
config ARCH_R8A77965
bool "Renesas R-Car M3-N SoC Platform"
select ARCH_RCAR_GEN3
@ -292,10 +303,14 @@ config SYSC_R8A7795
bool "R-Car H3 System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A7796
config SYSC_R8A77960
bool "R-Car M3-W System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A77961
bool "R-Car M3-W+ System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A77965
bool "R-Car M3-N System Controller support" if COMPILE_TEST
select SYSC_RCAR

3
drivers/soc/renesas/Makefile
View File

@ -15,7 +15,8 @@ obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o
obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o
obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
obj-$(CONFIG_SYSC_R8A77960) += r8a7796-sysc.o
obj-$(CONFIG_SYSC_R8A77961) += r8a7796-sysc.o
obj-$(CONFIG_SYSC_R8A77965) += r8a77965-sysc.o
obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o
obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o

27
drivers/soc/renesas/r8a7796-sysc.c
View File

@ -1,19 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas R-Car M3-W System Controller
* Renesas R-Car M3-W/W+ System Controller
*
* Copyright (C) 2016 Glider bvba
* Copyright (C) 2018-2019 Renesas Electronics Corporation
*/
#include <linux/bits.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
#include <dt-bindings/power/r8a7796-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
static struct rcar_sysc_area r8a7796_areas[] __initdata = {
{ "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
PD_SCU },
@ -41,24 +41,27 @@ static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
};
/* Fixups for R-Car M3-W ES1.x revision */
static const struct soc_device_attribute r8a7796es1[] __initconst = {
{ .soc_id = "r8a7796", .revision = "ES1.*" },
{ /* sentinel */ }
#ifdef CONFIG_SYSC_R8A77960
const struct rcar_sysc_info r8a77960_sysc_info __initconst = {
.areas = r8a7796_areas,
.num_areas = ARRAY_SIZE(r8a7796_areas),
};
#endif /* CONFIG_SYSC_R8A77960 */
static int __init r8a7796_sysc_init(void)
#ifdef CONFIG_SYSC_R8A77961
static int __init r8a77961_sysc_init(void)
{
if (soc_device_match(r8a7796es1))
r8a7796_sysc_info.extmask_val = 0;
rcar_sysc_nullify(r8a7796_areas, ARRAY_SIZE(r8a7796_areas),
R8A7796_PD_A2VC0);
return 0;
}
struct rcar_sysc_info r8a7796_sysc_info __initdata = {
.init = r8a7796_sysc_init,
const struct rcar_sysc_info r8a77961_sysc_info __initconst = {
.init = r8a77961_sysc_init,
.areas = r8a7796_areas,
.num_areas = ARRAY_SIZE(r8a7796_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};
#endif /* CONFIG_SYSC_R8A77961 */

1
drivers/soc/renesas/rcar-rst.c
View File

@ -59,6 +59,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
/* R-Car Gen3 */
{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },

7
drivers/soc/renesas/rcar-sysc.c
View File

@ -313,8 +313,11 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A7795
{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A7796
{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
#ifdef CONFIG_SYSC_R8A77960
{ .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A77961
{ .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A77965
{ .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },

3
drivers/soc/renesas/rcar-sysc.h
View File

@ -61,7 +61,8 @@ extern const struct rcar_sysc_info r8a7791_sysc_info;
extern const struct rcar_sysc_info r8a7792_sysc_info;
extern const struct rcar_sysc_info r8a7794_sysc_info;
extern struct rcar_sysc_info r8a7795_sysc_info;
extern struct rcar_sysc_info r8a7796_sysc_info;
extern const struct rcar_sysc_info r8a77960_sysc_info;
extern const struct rcar_sysc_info r8a77961_sysc_info;
extern const struct rcar_sysc_info r8a77965_sysc_info;
extern const struct rcar_sysc_info r8a77970_sysc_info;
extern const struct rcar_sysc_info r8a77980_sysc_info;

7
drivers/soc/renesas/renesas-soc.c
View File

@ -262,9 +262,12 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A7795
{ .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 },
#endif
#ifdef CONFIG_ARCH_R8A7796
#ifdef CONFIG_ARCH_R8A77960
{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_R8A77961
{ .compatible = "renesas,r8a77961", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_R8A77965
{ .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n },
#endif
@ -334,7 +337,7 @@ static int __init renesas_soc_init(void)
if (np) {
chipid = of_iomap(np, 0);
of_node_put(np);
} else if (soc->id) {
} else if (soc->id && family->reg) {
chipid = ioremap(family->reg, 4);
}
if (chipid) {

65
include/dt-bindings/clock/r8a77961-cpg-mssr.h Normal file
View File

@ -0,0 +1,65 @@
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77961 CPG Core Clocks */
#define R8A77961_CLK_Z 0
#define R8A77961_CLK_Z2 1
#define R8A77961_CLK_ZR 2
#define R8A77961_CLK_ZG 3
#define R8A77961_CLK_ZTR 4
#define R8A77961_CLK_ZTRD2 5
#define R8A77961_CLK_ZT 6
#define R8A77961_CLK_ZX 7
#define R8A77961_CLK_S0D1 8
#define R8A77961_CLK_S0D2 9
#define R8A77961_CLK_S0D3 10
#define R8A77961_CLK_S0D4 11
#define R8A77961_CLK_S0D6 12
#define R8A77961_CLK_S0D8 13
#define R8A77961_CLK_S0D12 14
#define R8A77961_CLK_S1D1 15
#define R8A77961_CLK_S1D2 16
#define R8A77961_CLK_S1D4 17
#define R8A77961_CLK_S2D1 18
#define R8A77961_CLK_S2D2 19
#define R8A77961_CLK_S2D4 20
#define R8A77961_CLK_S3D1 21
#define R8A77961_CLK_S3D2 22
#define R8A77961_CLK_S3D4 23
#define R8A77961_CLK_LB 24
#define R8A77961_CLK_CL 25
#define R8A77961_CLK_ZB3 26
#define R8A77961_CLK_ZB3D2 27
#define R8A77961_CLK_ZB3D4 28
#define R8A77961_CLK_CR 29
#define R8A77961_CLK_CRD2 30
#define R8A77961_CLK_SD0H 31
#define R8A77961_CLK_SD0 32
#define R8A77961_CLK_SD1H 33
#define R8A77961_CLK_SD1 34
#define R8A77961_CLK_SD2H 35
#define R8A77961_CLK_SD2 36
#define R8A77961_CLK_SD3H 37
#define R8A77961_CLK_SD3 38
#define R8A77961_CLK_SSP2 39
#define R8A77961_CLK_SSP1 40
#define R8A77961_CLK_SSPRS 41
#define R8A77961_CLK_RPC 42
#define R8A77961_CLK_RPCD2 43
#define R8A77961_CLK_MSO 44
#define R8A77961_CLK_CANFD 45
#define R8A77961_CLK_HDMI 46
#define R8A77961_CLK_CSI0 47
/* CLK_CSIREF was removed */
#define R8A77961_CLK_CP 49
#define R8A77961_CLK_CPEX 50
#define R8A77961_CLK_R 51
#define R8A77961_CLK_OSC 52
#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */

32
include/dt-bindings/power/r8a77961-sysc.h Normal file
View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2019 Glider bvba
*/
#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77961_PD_CA57_CPU0 0
#define R8A77961_PD_CA57_CPU1 1
#define R8A77961_PD_CA53_CPU0 5
#define R8A77961_PD_CA53_CPU1 6
#define R8A77961_PD_CA53_CPU2 7
#define R8A77961_PD_CA53_CPU3 8
#define R8A77961_PD_CA57_SCU 12
#define R8A77961_PD_CR7 13
#define R8A77961_PD_A3VC 14
#define R8A77961_PD_3DG_A 17
#define R8A77961_PD_3DG_B 18
#define R8A77961_PD_CA53_SCU 21
#define R8A77961_PD_A3IR 24
#define R8A77961_PD_A2VC1 26
/* Always-on power area */
#define R8A77961_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */