leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Second Round of Renesas ARM Based SoC DT Updates for v4.1

Browse Source 
* ape6evm board
   - Configure GPIO keys as wake-up source
   - Enable pull-up for GPIO switches
   - Correct polarity of LEDs
 * r8a7791 SoC
   - Correct IPMMU-GP clock to device tree
 * r8a7794 SoC
   - Correct ethernet controller PHY IRQ
 * lager, koelsch and marzen boards
   - Add DU external pixel clock to DT
 * lager board
   - Add HDMI output support to DT
 * r8a7791 and r8a7790 SoCs
   - Tidy up SDHI register size in DT
   - Reference DMA channels for SDHI in DT
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU/j1NAAoJENfPZGlqN0++EcUQAJnDAqO6jtSdPiu8HUNMHDnO
 HKrIbh9VE/rbn2HPcwP4MfIxbwNPe6ezTq99e+ckor2ThzxtQ9uxv4nPEoY/wGSh
 kNq2LALlfa6VFqezD/2V8mroI5o9ZtzRV2uv07U8L7VxVFO0VA3oYqDYDBudhINa
 nD2OmtZhCEgrZXZEWxCqrvHzWGWVYARMiW88ZVZ8VTge+I6Cy/U3Cw+MOfFTI/DP
 ej/I9nK+JnWbnxduFhHNX+VECT1aGqDhltKLMlagEUbJJtHl4VlAcvisSoYBE8VU
 E+Di4WawKVtukkbVhnc5ArYYemjpawYV29FYqbPBpgo/uW87mm8V+Sfj0m0v5iPa
 JxA90PPf7pauauI+eGk1J9BGeUmt2rqZpvh9/InaZbT0QY38/LNW767AC5i3QUg4
 u94tied7GPFpq8VFuD925LOVfgvXX8aFgKP/kf764pN0qcNpRfcC7lEdV/kFRoNB
 6JmRj0NTKvxKPKtlr/NteiD8+c2UkAMO+yDa79FmrImh8+OBMBj4t9BUjbEMfrFd
 tTdvLzN4cRahVWaot5GTMLbbD9VLO8/2wOfv+43xXnKER4xPxgDwI5O6WHMJbJsT
 Q+onSaP/jEe/VdsaOax5iPQ3P+Sv/zLS+rFEmoYBewqDdAtKnjUcjn3tvumjTLqU
 hnIDRuS8grpcgpIk0vpw
 =lxzo
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dt2-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.1" from Simon Horman:

* ape6evm board
  - Configure GPIO keys as wake-up source
  - Enable pull-up for GPIO switches
  - Correct polarity of LEDs
* r8a7791 SoC
  - Correct IPMMU-GP clock to device tree
* r8a7794 SoC
  - Correct ethernet controller PHY IRQ
* lager, koelsch and marzen boards
  - Add DU external pixel clock to DT
* lager board
  - Add HDMI output support to DT
* r8a7791 and r8a7790 SoCs
  - Tidy up SDHI register size in DT
  - Reference DMA channels for SDHI in DT

* tag 'renesas-dt2-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: ape6evm dts: Configure the custom switch as wake-up source
  ARM: shmobile: ape6evm dts: Enable pull-up for GPIO switches
  ARM: shmobile: r8a7791: Fix IPMMU-GP clock to device tree
  ARM: shmobile: r8a7794: alt: Fix ethernet controller PHY IRQ line
  ARM: shmobile: lager: Add DU external pixel clocks to DT
  ARM: shmobile: koelsch: Add DU external pixel clocks to DT
  ARM: shmobile: marzen: Add DU external pixel clock to DT
  ARM: shmobile: ape6evm dts: Fix polarity of LEDs
  ARM: shmobile: lager: Add DU HDMI output support
  ARM: shmobile: r8a7791: Fix HSUSB clock to hp_clk from mp_clk
  ARM: shmobile: r8a7790: Fix HSUSB clock to hp_clk from mp_clk
  ARM: shmobile: r8a7791: tidyup SDHI register size on DTSI
  ARM: shmobile: r8a7790: tidyup SDHI register size on DTSI
  ARM: shmobile: r8a7791: Reference DMA channels in SDHI DT nodes
  ARM: shmobile: r8a7790: Reference DMA channels in SDHI DT nodes
This commit is contained in:
Arnd Bergmann 2015-03-11 22:54:57 +01:00
commit 05e6d23296
7 changed files with 136 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View File

@ -95,27 +95,27 @@
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
gpios = <&pfc 28 GPIO_ACTIVE_HIGH>;
label = "GNSS_EN";
};
led2 {
gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
gpios = <&pfc 126 GPIO_ACTIVE_HIGH>;
label = "NFC_NRST";
};
led3 {
gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
gpios = <&pfc 132 GPIO_ACTIVE_HIGH>;
label = "GNSS_NRST";
};
led4 {
gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
gpios = <&pfc 232 GPIO_ACTIVE_HIGH>;
label = "BT_WAKEUP";
};
led5 {
gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
gpios = <&pfc 250 GPIO_ACTIVE_HIGH>;
label = "STROBE";
};
led6 {
gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
gpios = <&pfc 288 GPIO_ACTIVE_HIGH>;
label = "BBRESETOUT";
};
};
@ -123,10 +123,14 @@
keyboard {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&keyboard_pins>;
zero-key {
gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
linux,code = <KEY_0>;
label = "S16";
gpio-key,wakeup;
};
menu-key {
@ -208,6 +212,12 @@
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
};
keyboard_pins: keyboard {
renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
"PORT328", "PORT329";
bias-pull-up;
};
};
&mmcif0 {

9
arch/arm/boot/dts/r8a7779-marzen.dts
View File

@ -122,6 +122,12 @@
};
};
};
x3_clk: x3-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <65000000>;
};
};
&du {
@ -129,6 +135,9 @@
pinctrl-names = "default";
status = "okay";
clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
clock-names = "du", "dclkin.0";
ports {
port@0 {
endpoint {

69
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -222,6 +222,29 @@
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
x13_clk: x13-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&du {
@ -229,12 +252,26 @@
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7790_CLK_DU0>,
<&mstp7_clks R8A7790_CLK_DU1>,
<&mstp7_clks R8A7790_CLK_DU2>,
<&mstp7_clks R8A7790_CLK_LVDS0>,
<&mstp7_clks R8A7790_CLK_LVDS1>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
"dclkin.0", "dclkin.1";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
port@1 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@2 {
lvds_connector: endpoint {
};
@ -506,6 +543,38 @@
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&iic3 {

15
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -1,6 +1,7 @@
/*
* Device Tree Source for the r8a7790 SoC
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2013-2014 Renesas Solutions Corp.
* Copyright (C) 2014 Cogent Embedded Inc.
*
@ -493,17 +494,21 @@
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7790";
reg = <0 0xee100000 0 0x200>;
reg = <0 0xee100000 0 0x328>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7790";
reg = <0 0xee120000 0 0x200>;
reg = <0 0xee120000 0 0x328>;
interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -512,6 +517,8 @@
reg = <0 0xee140000 0 0x100>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -520,6 +527,8 @@
reg = <0 0xee160000 0 0x100>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1173,7 +1182,7 @@
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
<&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
<&zx_clk>;
#clock-cells = <1>;

19
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -269,6 +269,18 @@
};
};
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
x13_clk: x13-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&du {
@ -276,6 +288,13 @@
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7791_CLK_DU0>,
<&mstp7_clks R8A7791_CLK_DU1>,
<&mstp7_clks R8A7791_CLK_LVDS0>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
ports {
port@0 {
endpoint {

14
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7791 SoC
*
* Copyright (C) 2013-2014 Renesas Electronics Corporation
* Copyright (C) 2013-2015 Renesas Electronics Corporation
* Copyright (C) 2013-2014 Renesas Solutions Corp.
* Copyright (C) 2014 Cogent Embedded Inc.
*
@ -482,9 +482,11 @@
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7791";
reg = <0 0xee100000 0 0x200>;
reg = <0 0xee100000 0 0x328>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -493,6 +495,8 @@
reg = <0 0xee140000 0 0x100>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -501,6 +505,8 @@
reg = <0 0xee160000 0 0x100>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1178,7 +1184,7 @@
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>, <&zx_clk>, <&zx_clk>;
#clock-cells = <1>;
@ -1196,7 +1202,7 @@
mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <

2
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -51,7 +51,7 @@
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
};
};