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Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6

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This commit is contained in:
Russell King 2008-10-30 14:26:45 +00:00 committed by Russell King
commit 05cd2544f4
245 changed files with 4765 additions and 1766 deletions
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2
Documentation/scheduler/sched-design-CFS.txt
View File

@ -92,7 +92,7 @@ other HZ detail. Thus the CFS scheduler has no notion of "timeslices" in the
way the previous scheduler had, and has no heuristics whatsoever. There is
only one central tunable (you have to switch on CONFIG_SCHED_DEBUG):
/proc/sys/kernel/sched_granularity_ns
/proc/sys/kernel/sched_min_granularity_ns
which can be used to tune the scheduler from "desktop" (i.e., low latencies) to
"server" (i.e., good batching) workloads. It defaults to a setting suitable

2
Makefile
View File

@ -536,7 +536,7 @@ KBUILD_CFLAGS += -g
KBUILD_AFLAGS += -gdwarf-2
endif
ifdef CONFIG_FTRACE
ifdef CONFIG_FUNCTION_TRACER
KBUILD_CFLAGS += -pg
endif

3
arch/arm/Kconfig
View File

@ -16,8 +16,7 @@ config ARM
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FTRACE if (!XIP_KERNEL)
select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_GENERIC_DMA_COHERENT
help
The ARM series is a line of low-power-consumption RISC chip designs

2
arch/arm/boot/compressed/Makefile
View File

@ -70,7 +70,7 @@ SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
head.o misc.o $(OBJS)
ifeq ($(CONFIG_FTRACE),y)
ifeq ($(CONFIG_FUNCTION_TRACER),y)
ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
endif

19
arch/arm/common/sharpsl_pm.c
View File

@ -54,11 +54,13 @@
/*
* Prototypes
*/
#ifdef CONFIG_PM
static int sharpsl_off_charge_battery(void);
static int sharpsl_check_battery_temp(void);
static int sharpsl_check_battery_voltage(void);
static int sharpsl_ac_check(void);
static int sharpsl_fatal_check(void);
#endif
static int sharpsl_check_battery_temp(void);
static int sharpsl_ac_check(void);
static int sharpsl_average_value(int ad);
static void sharpsl_average_clear(void);
static void sharpsl_charge_toggle(struct work_struct *private_);
@ -424,6 +426,7 @@ static int sharpsl_check_battery_temp(void)
return 0;
}
#ifdef CONFIG_PM
static int sharpsl_check_battery_voltage(void)
{
int val, i, buff[5];
@ -455,6 +458,7 @@ static int sharpsl_check_battery_voltage(void)
return 0;
}
#endif
static int sharpsl_ac_check(void)
{
@ -586,8 +590,6 @@ static int corgi_pxa_pm_enter(suspend_state_t state)
return 0;
}
#endif
/*
* Check for fatal battery errors
@ -738,7 +740,10 @@ static int sharpsl_off_charge_battery(void)
}
}
}
#else
#define sharpsl_pm_suspend NULL
#define sharpsl_pm_resume NULL
#endif
static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf)
{
@ -768,10 +773,12 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info)
info->battery_life = sharpsl_pm.battstat.mainbat_percent;
}
#ifdef CONFIG_PM
static struct platform_suspend_ops sharpsl_pm_ops = {
.enter = corgi_pxa_pm_enter,
.valid = suspend_valid_only_mem,
};
#endif
static int __init sharpsl_pm_probe(struct platform_device *pdev)
{
@ -802,7 +809,9 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev)
apm_get_power_status = sharpsl_apm_get_power_status;
#ifdef CONFIG_PM
suspend_set_ops(&sharpsl_pm_ops);
#endif
mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));

2
arch/arm/include/asm/ftrace.h
View File

@ -1,7 +1,7 @@
#ifndef _ASM_ARM_FTRACE
#define _ASM_ARM_FTRACE
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
#define MCOUNT_ADDR ((long)(mcount))
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */

2
arch/arm/kernel/armksyms.c
View File

@ -183,6 +183,6 @@ EXPORT_SYMBOL(_find_next_bit_be);
EXPORT_SYMBOL(copy_page);
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
EXPORT_SYMBOL(mcount);
#endif

4
arch/arm/kernel/entry-common.S
View File

@ -101,7 +101,7 @@ ENDPROC(ret_from_fork)
#undef CALL
#define CALL(x) .long x
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
#ifdef CONFIG_DYNAMIC_FTRACE
ENTRY(mcount)
stmdb sp!, {r0-r3, lr}
@ -149,7 +149,7 @@ trace:
ftrace_stub:
mov pc, lr
#endif /* CONFIG_FTRACE */
#endif /* CONFIG_FUNCTION_TRACER */
/*=============================================================================
* SWI handler

13
arch/arm/kernel/ftrace.c
View File

@ -95,19 +95,6 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
return ret;
}
int ftrace_mcount_set(unsigned long *data)
{
unsigned long pc, old;
unsigned long *addr = data;
unsigned char *new;
pc = (unsigned long)&mcount_call;
memcpy(&old, &mcount_call, MCOUNT_INSN_SIZE);
new = ftrace_call_replace(pc, *addr);
*addr = ftrace_modify_code(pc, (unsigned char *)&old, new);
return 0;
}
/* run from kstop_machine */
int __init ftrace_dyn_arch_init(void *data)
{

4
arch/arm/mach-pxa/corgi_pm.c
View File

@ -204,7 +204,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
.read_devdata = corgipm_read_devdata,
.charger_wakeup = corgi_charger_wakeup,
.should_wakeup = corgi_should_wakeup,
#ifdef CONFIG_BACKLIGHT_CORGI
#if defined(CONFIG_LCD_CORGI)
.backlight_limit = corgi_lcd_limit_intensity,
#elif defined(CONFIG_BACKLIGHT_CORGI)
.backlight_limit = corgibl_limit_intensity,
#endif
.charge_on_volt = SHARPSL_CHARGE_ON_VOLT,

1
arch/arm/mach-pxa/include/mach/sharpsl.h
View File

@ -26,6 +26,7 @@ struct corgits_machinfo {
* SharpSL Backlight
*/
extern void corgibl_limit_intensity(int limit);
extern void corgi_lcd_limit_intensity(int limit);
/*

12
arch/arm/mach-pxa/spitz.c
View File

@ -385,6 +385,16 @@ static void __init spitz_init_spi(void)
if (err)
goto err_free_2;
err = gpio_direction_output(SPITZ_GPIO_ADS7846_CS, 1);
if (err)
goto err_free_3;
err = gpio_direction_output(SPITZ_GPIO_LCDCON_CS, 1);
if (err)
goto err_free_3;
err = gpio_direction_output(SPITZ_GPIO_MAX1111_CS, 1);
if (err)
goto err_free_3;
if (machine_is_akita()) {
spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
@ -394,6 +404,8 @@ static void __init spitz_init_spi(void)
spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
return;
err_free_3:
gpio_free(SPITZ_GPIO_MAX1111_CS);
err_free_2:
gpio_free(SPITZ_GPIO_LCDCON_CS);
err_free_1:

4
arch/arm/mach-pxa/spitz_pm.c
View File

@ -198,7 +198,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
.read_devdata = spitzpm_read_devdata,
.charger_wakeup = spitz_charger_wakeup,
.should_wakeup = spitz_should_wakeup,
#ifdef CONFIG_BACKLIGHT_CORGI
#if defined(CONFIG_LCD_CORGI)
.backlight_limit = corgi_lcd_limit_intensity,
#elif defined(CONFIG_BACKLIGHT_CORGI)
.backlight_limit = corgibl_limit_intensity,
#endif
.charge_on_volt = SHARPSL_CHARGE_ON_VOLT,

6
arch/ia64/include/asm/kvm_host.h
View File

@ -365,7 +365,8 @@ struct kvm_vcpu_arch {
long itc_offset;
unsigned long itc_check;
unsigned long timer_check;
unsigned long timer_pending;
unsigned int timer_pending;
unsigned int timer_fired;
unsigned long vrr[8];
unsigned long ibr[8];
@ -417,6 +418,9 @@ struct kvm_arch {
struct list_head assigned_dev_head;
struct dmar_domain *intel_iommu_domain;
struct hlist_head irq_ack_notifier_list;
unsigned long irq_sources_bitmap;
unsigned long irq_states[KVM_IOAPIC_NUM_PINS];
};
union cpuid3_t {

8
arch/ia64/kvm/Makefile
View File

@ -29,13 +29,18 @@ define cmd_offsets
echo ""; \
echo "#endif" ) > $@
endef
# We use internal rules to avoid the "is up to date" message from make
arch/ia64/kvm/asm-offsets.s: arch/ia64/kvm/asm-offsets.c
arch/ia64/kvm/asm-offsets.s: arch/ia64/kvm/asm-offsets.c \
$(wildcard $(srctree)/arch/ia64/include/asm/*.h)\
$(wildcard $(srctree)/include/linux/*.h)
$(call if_changed_dep,cc_s_c)
$(obj)/$(offsets-file): arch/ia64/kvm/asm-offsets.s
$(call cmd,offsets)
FORCE : $(obj)/$(offsets-file)
#
# Makefile for Kernel-based Virtual Machine module
#
@ -53,7 +58,6 @@ endif
kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
obj-$(CONFIG_KVM) += kvm.o
FORCE : $(obj)/$(offsets-file)
EXTRA_CFLAGS_vcpu.o += -mfixed-range=f2-f5,f12-f127
kvm-intel-objs = vmm.o vmm_ivt.o trampoline.o vcpu.o optvfault.o mmio.o \
vtlb.o process.o

84
arch/ia64/kvm/kvm-ia64.c
View File

@ -385,6 +385,7 @@ static int handle_global_purge(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
struct kvm *kvm = vcpu->kvm;
struct call_data call_data;
int i;
call_data.ptc_g_data = p->u.ptc_g_data;
for (i = 0; i < KVM_MAX_VCPUS; i++) {
@ -418,33 +419,41 @@ int kvm_emulate_halt(struct kvm_vcpu *vcpu)
ktime_t kt;
long itc_diff;
unsigned long vcpu_now_itc;
unsigned long expires;
struct hrtimer *p_ht = &vcpu->arch.hlt_timer;
unsigned long cyc_per_usec = local_cpu_data->cyc_per_usec;
struct vpd *vpd = to_host(vcpu->kvm, vcpu->arch.vpd);
vcpu_now_itc = ia64_getreg(_IA64_REG_AR_ITC) + vcpu->arch.itc_offset;
if (time_after(vcpu_now_itc, vpd->itm)) {
vcpu->arch.timer_check = 1;
return 1;
}
itc_diff = vpd->itm - vcpu_now_itc;
if (itc_diff < 0)
itc_diff = -itc_diff;
expires = div64_u64(itc_diff, cyc_per_usec);
kt = ktime_set(0, 1000 * expires);
vcpu->arch.ht_active = 1;
hrtimer_start(p_ht, kt, HRTIMER_MODE_ABS);
if (irqchip_in_kernel(vcpu->kvm)) {
vcpu_now_itc = ia64_getreg(_IA64_REG_AR_ITC) + vcpu->arch.itc_offset;
if (time_after(vcpu_now_itc, vpd->itm)) {
vcpu->arch.timer_check = 1;
return 1;
}
itc_diff = vpd->itm - vcpu_now_itc;
if (itc_diff < 0)
itc_diff = -itc_diff;
expires = div64_u64(itc_diff, cyc_per_usec);
kt = ktime_set(0, 1000 * expires);
down_read(&vcpu->kvm->slots_lock);
vcpu->arch.ht_active = 1;
hrtimer_start(p_ht, kt, HRTIMER_MODE_ABS);
vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
kvm_vcpu_block(vcpu);
hrtimer_cancel(p_ht);
vcpu->arch.ht_active = 0;
if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
vcpu->arch.mp_state =
KVM_MP_STATE_RUNNABLE;
up_read(&vcpu->kvm->slots_lock);
if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
return -EINTR;
return 1;
@ -484,10 +493,6 @@ static int (*kvm_vti_exit_handlers[])(struct kvm_vcpu *vcpu,
static const int kvm_vti_max_exit_handlers =
sizeof(kvm_vti_exit_handlers)/sizeof(*kvm_vti_exit_handlers);
static void kvm_prepare_guest_switch(struct kvm_vcpu *vcpu)
{
}
static uint32_t kvm_get_exit_reason(struct kvm_vcpu *vcpu)
{
struct exit_ctl_data *p_exit_data;
@ -600,8 +605,6 @@ static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
again:
preempt_disable();
kvm_prepare_guest_switch(vcpu);
local_irq_disable();
if (signal_pending(current)) {
@ -614,7 +617,7 @@ again:
vcpu->guest_mode = 1;
kvm_guest_enter();
down_read(&vcpu->kvm->slots_lock);
r = vti_vcpu_run(vcpu, kvm_run);
if (r < 0) {
local_irq_enable();
@ -634,9 +637,8 @@ again:
* But we need to prevent reordering, hence this barrier():
*/
barrier();
kvm_guest_exit();
up_read(&vcpu->kvm->slots_lock);
preempt_enable();
r = kvm_handle_exit(kvm_run, vcpu);
@ -673,6 +675,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
kvm_vcpu_block(vcpu);
clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
vcpu_put(vcpu);
return -EAGAIN;
}
@ -778,6 +781,9 @@ static void kvm_init_vm(struct kvm *kvm)
kvm_build_io_pmt(kvm);
INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
/* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
}
struct kvm *kvm_arch_create_vm(void)
@ -941,9 +947,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
goto out;
if (irqchip_in_kernel(kvm)) {
mutex_lock(&kvm->lock);
kvm_ioapic_set_irq(kvm->arch.vioapic,
irq_event.irq,
irq_event.level);
kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
irq_event.irq, irq_event.level);
mutex_unlock(&kvm->lock);
r = 0;
}
@ -1123,15 +1128,16 @@ static enum hrtimer_restart hlt_timer_fn(struct hrtimer *data)
wait_queue_head_t *q;
vcpu = container_of(data, struct kvm_vcpu, arch.hlt_timer);
q = &vcpu->wq;
if (vcpu->arch.mp_state != KVM_MP_STATE_HALTED)
goto out;
q = &vcpu->wq;
if (waitqueue_active(q)) {
vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
if (waitqueue_active(q))
wake_up_interruptible(q);
}
out:
vcpu->arch.timer_fired = 1;
vcpu->arch.timer_check = 1;
return HRTIMER_NORESTART;
}
@ -1700,12 +1706,14 @@ static void vcpu_kick_intr(void *info)
void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
{
int ipi_pcpu = vcpu->cpu;
int cpu = get_cpu();
if (waitqueue_active(&vcpu->wq))
wake_up_interruptible(&vcpu->wq);
if (vcpu->guest_mode)
if (vcpu->guest_mode && cpu != ipi_pcpu)
smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
put_cpu();
}
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
@ -1715,13 +1723,7 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
if (!test_and_set_bit(vec, &vpd->irr[0])) {
vcpu->arch.irq_new_pending = 1;
if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
kvm_vcpu_kick(vcpu);
else if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) {
vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
if (waitqueue_active(&vcpu->wq))
wake_up_interruptible(&vcpu->wq);
}
kvm_vcpu_kick(vcpu);
return 1;
}
return 0;
@ -1791,7 +1793,7 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
{
return 0;
return vcpu->arch.timer_fired;
}
gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)

9
arch/ia64/kvm/kvm_fw.c
View File

@ -286,6 +286,12 @@ static u64 kvm_get_pal_call_index(struct kvm_vcpu *vcpu)
return index;
}
static void prepare_for_halt(struct kvm_vcpu *vcpu)
{
vcpu->arch.timer_pending = 1;
vcpu->arch.timer_fired = 0;
}
int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
@ -304,11 +310,10 @@ int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *run)
break;
case PAL_HALT_LIGHT:
{
vcpu->arch.timer_pending = 1;
INIT_PAL_STATUS_SUCCESS(result);
prepare_for_halt(vcpu);
if (kvm_highest_pending_irq(vcpu) == -1)
ret = kvm_emulate_halt(vcpu);
}
break;

2
arch/ia64/kvm/process.c
View File

@ -713,7 +713,7 @@ void leave_hypervisor_tail(void)
if (!(VCPU(v, itv) & (1 << 16))) {
vcpu_pend_interrupt(v, VCPU(v, itv)
& 0xff);
VMX(v, itc_check) = 0;
VMX(v, itc_check) = 0;
} else {
v->arch.timer_pending = 1;
}

62
arch/mips/Kconfig
View File

@ -238,21 +238,8 @@ config MIPS_SIM
This option enables support for MIPS Technologies MIPSsim software
emulator.
config MARKEINS
bool "NEC EMMA2RH Mark-eins"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_CPU_R5000
help
This enables support for the R5432-based NEC Mark-eins
boards with R5500 CPU.
config MACH_EMMA
bool "NEC EMMA series based machines"
config MACH_VR41XX
bool "NEC VR4100 series based machines"
@ -261,6 +248,19 @@ config MACH_VR41XX
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
config NXP_STB220
bool "NXP STB220 board"
select SOC_PNX833X
help
Support for NXP Semiconductors STB220 Development Board.
config NXP_STB225
bool "NXP 225 board"
select SOC_PNX833X
select SOC_PNX8335
help
Support for NXP Semiconductors STB225 Development Board.
config PNX8550_JBS
bool "NXP PNX8550 based JBS board"
select PNX8550
@ -601,6 +601,7 @@ endchoice
source "arch/mips/alchemy/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/emma/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
@ -849,6 +850,24 @@ config MIPS_RM9122
bool
select SERIAL_RM9000
config SOC_PNX833X
bool
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select DMA_NONCOHERENT
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
select CPU_MIPSR2_IRQ_VI
config SOC_PNX8335
bool
select SOC_PNX833X
config PNX8550
bool
select SOC_PNX8550
@ -1092,6 +1111,16 @@ config CPU_R5432
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
config CPU_R5500
bool "R5500"
depends on SYS_HAS_CPU_R5500
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
instruction set.
config CPU_R6000
bool "R6000"
depends on EXPERIMENTAL
@ -1202,6 +1231,9 @@ config SYS_HAS_CPU_R5000
config SYS_HAS_CPU_R5432
bool
config SYS_HAS_CPU_R5500
bool
config SYS_HAS_CPU_R6000
bool

23
arch/mips/Makefile
View File

@ -131,6 +131,8 @@ cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \
-Wa,--trap
cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \
-Wa,--trap
cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \
-Wa,--trap
cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \
@ -381,6 +383,14 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
#
load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
# NXP STB225
core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/
cflags-$(CONFIG_SOC_PNX833X) += -Iarch/mips/include/asm/mach-pnx833x
libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/
load-$(CONFIG_NXP_STB220) += 0xffffffff80001000
libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/
load-$(CONFIG_NXP_STB225) += 0xffffffff80001000
#
# Common NXP PNX8550
#
@ -399,14 +409,17 @@ load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/
load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
# NEC EMMA2RH boards
#
core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/
cflags-$(CONFIG_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
# Common NEC EMMAXXX
#
core-$(CONFIG_SOC_EMMA) += arch/mips/emma/common/
cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
#
# NEC EMMA2RH Mark-eins
core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/
load-$(CONFIG_MARKEINS) += 0xffffffff88100000
#
core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
#
# SGI IP22 (Indy/Indigo2)

98
arch/mips/alchemy/common/platform.c
View File

@ -17,6 +17,8 @@
#include <linux/init.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#define PORT(_base, _irq) \
{ \
@ -163,24 +165,6 @@ static struct resource au1xxx_usb_gdt_resources[] = {
},
};
static struct resource au1xxx_mmc_resources[] = {
[0] = {
.start = SD0_PHYS_ADDR,
.end = SD0_PHYS_ADDR + 0x7ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SD1_PHYS_ADDR,
.end = SD1_PHYS_ADDR + 0x7ffff,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 udc_dmamask = DMA_32BIT_MASK;
static struct platform_device au1xxx_usb_gdt_device = {
@ -249,16 +233,79 @@ static struct platform_device au1200_lcd_device = {
static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK;
static struct platform_device au1xxx_mmc_device = {
extern struct au1xmmc_platform_data au1xmmc_platdata[2];
static struct resource au1200_mmc0_resources[] = {
[0] = {
.start = SD0_PHYS_ADDR,
.end = SD0_PHYS_ADDR + 0x7ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_SDMS_TX0,
.end = DSCR_CMD0_SDMS_TX0,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_SDMS_RX0,
.end = DSCR_CMD0_SDMS_RX0,
.flags = IORESOURCE_DMA,
}
};
static struct platform_device au1200_mmc0_device = {
.name = "au1xxx-mmc",
.id = 0,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
.platform_data = &au1xmmc_platdata[0],
},
.num_resources = ARRAY_SIZE(au1xxx_mmc_resources),
.resource = au1xxx_mmc_resources,
.num_resources = ARRAY_SIZE(au1200_mmc0_resources),
.resource = au1200_mmc0_resources,
};
#ifndef CONFIG_MIPS_DB1200
static struct resource au1200_mmc1_resources[] = {
[0] = {
.start = SD1_PHYS_ADDR,
.end = SD1_PHYS_ADDR + 0x7ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_SDMS_TX1,
.end = DSCR_CMD0_SDMS_TX1,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_SDMS_RX1,
.end = DSCR_CMD0_SDMS_RX1,
.flags = IORESOURCE_DMA,
}
};
static struct platform_device au1200_mmc1_device = {
.name = "au1xxx-mmc",
.id = 1,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
.platform_data = &au1xmmc_platdata[1],
},
.num_resources = ARRAY_SIZE(au1200_mmc1_resources),
.resource = au1200_mmc1_resources,
};
#endif /* #ifndef CONFIG_MIPS_DB1200 */
#endif /* #ifdef CONFIG_SOC_AU1200 */
static struct platform_device au1x00_pcmcia_device = {
@ -296,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
&au1xxx_usb_gdt_device,
&au1xxx_usb_otg_device,
&au1200_lcd_device,
&au1xxx_mmc_device,
&au1200_mmc0_device,
#ifndef CONFIG_MIPS_DB1200
&au1200_mmc1_device,
#endif
#endif
#ifdef SMBUS_PSC_BASE
&pbdb_smbus_device,

81
arch/mips/alchemy/pb1200/platform.c
View File

@ -20,9 +20,90 @@
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1100_mmc.h>
static int mmc_activity;
static void pb1200mmc0_set_power(void *mmc_host, int state)
{
if (state)
bcsr->board |= BCSR_BOARD_SD0PWR;
else
bcsr->board &= ~BCSR_BOARD_SD0PWR;
au_sync_delay(1);
}
static int pb1200mmc0_card_readonly(void *mmc_host)
{
return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0;
}
static int pb1200mmc0_card_inserted(void *mmc_host)
{
return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0;
}
static void pb1200_mmcled_set(struct led_classdev *led,
enum led_brightness brightness)
{
if (brightness != LED_OFF) {
if (++mmc_activity == 1)
bcsr->disk_leds &= ~(1 << 8);
} else {
if (--mmc_activity == 0)
bcsr->disk_leds |= (1 << 8);
}
}
static struct led_classdev pb1200mmc_led = {
.brightness_set = pb1200_mmcled_set,
};
#ifndef CONFIG_MIPS_DB1200
static void pb1200mmc1_set_power(void *mmc_host, int state)
{
if (state)
bcsr->board |= BCSR_BOARD_SD1PWR;
else
bcsr->board &= ~BCSR_BOARD_SD1PWR;
au_sync_delay(1);
}
static int pb1200mmc1_card_readonly(void *mmc_host)
{
return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0;
}
static int pb1200mmc1_card_inserted(void *mmc_host)
{
return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0;
}
#endif
const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
[0] = {
.set_power = pb1200mmc0_set_power,
.card_inserted = pb1200mmc0_card_inserted,
.card_readonly = pb1200mmc0_card_readonly,
.cd_setup = NULL, /* use poll-timer in driver */
.led = &pb1200mmc_led,
},
#ifndef CONFIG_MIPS_DB1200
[1] = {
.set_power = pb1200mmc1_set_power,
.card_inserted = pb1200mmc1_card_inserted,
.card_readonly = pb1200mmc1_card_readonly,
.cd_setup = NULL, /* use poll-timer in driver */
.led = &pb1200mmc_led,
},
#endif
};
static struct resource ide_resources[] = {
[0] = {

1149
arch/mips/configs/pnx8335-stb225_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

29
arch/mips/emma/Kconfig Normal file
View File

@ -0,0 +1,29 @@
choice
prompt "Machine type"
depends on MACH_EMMA
default NEC_MARKEINS
config NEC_MARKEINS
bool "NEC EMMA2RH Mark-eins board"
select SOC_EMMA2RH
select HW_HAS_PCI
help
This enables support for the NEC Electronics Mark-eins boards.
endchoice
config SOC_EMMA2RH
bool
select SOC_EMMA
select SYS_HAS_CPU_R5500
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
config SOC_EMMA
bool
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select SWAP_IO_SPACE
select SYS_SUPPORTS_BIG_ENDIAN

2
arch/mips/emma2rh/common/Makefile → arch/mips/emma/common/Makefile
View File

@ -10,4 +10,4 @@
# (at your option) any later version.
#
obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o
obj-$(CONFIG_NEC_MARKEINS) += prom.o

6
arch/mips/emma2rh/common/prom.c → arch/mips/emma/common/prom.c
View File

@ -29,11 +29,11 @@
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
const char *get_system_type(void)
{
#if defined(CONFIG_MARKEINS)
#ifdef CONFIG_NEC_MARKEINS
return "NEC EMMA2RH Mark-eins";
#else
#error Unknown NEC board
@ -60,7 +60,7 @@ void __init prom_init(void)
strcat(arcs_cmdline, " ");
}
#if defined(CONFIG_MARKEINS)
#ifdef CONFIG_NEC_MARKEINS
add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
#else
#error Unknown NEC board

2
arch/mips/emma2rh/markeins/Makefile → arch/mips/emma/markeins/Makefile
View File

@ -10,4 +10,4 @@
# (at your option) any later version.
#
obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o
obj-$(CONFIG_NEC_MARKEINS) += irq.o setup.o led.o platform.o

331
arch/mips/emma/markeins/irq.c Normal file
View File

@ -0,0 +1,331 @@
/*
* arch/mips/emma2rh/markeins/irq.c
* This file defines the irq handler for EMMA2RH.
*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/delay.h>
#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/emma/emma2rh.h>
static void emma2rh_irq_enable(unsigned int irq)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
irq -= EMMA2RH_IRQ_BASE;
reg_index = EMMA2RH_BHIF_INT_EN_0 +
(EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
reg_value = emma2rh_in32(reg_index);
reg_bitmask = 0x1 << (irq % 32);
emma2rh_out32(reg_index, reg_value | reg_bitmask);
}
static void emma2rh_irq_disable(unsigned int irq)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
irq -= EMMA2RH_IRQ_BASE;
reg_index = EMMA2RH_BHIF_INT_EN_0 +
(EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
reg_value = emma2rh_in32(reg_index);
reg_bitmask = 0x1 << (irq % 32);
emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
}
struct irq_chip emma2rh_irq_controller = {
.name = "emma2rh_irq",
.ack = emma2rh_irq_disable,
.mask = emma2rh_irq_disable,
.mask_ack = emma2rh_irq_disable,
.unmask = emma2rh_irq_enable,
};
void emma2rh_irq_init(void)
{
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq);
}
static void emma2rh_sw_irq_enable(unsigned int irq)
{
u32 reg;
irq -= EMMA2RH_SW_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
}
static void emma2rh_sw_irq_disable(unsigned int irq)
{
u32 reg;
irq -= EMMA2RH_SW_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
}
struct irq_chip emma2rh_sw_irq_controller = {
.name = "emma2rh_sw_irq",
.ack = emma2rh_sw_irq_disable,
.mask = emma2rh_sw_irq_disable,
.mask_ack = emma2rh_sw_irq_disable,
.unmask = emma2rh_sw_irq_enable,
};
void emma2rh_sw_irq_init(void)
{
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq);
}
static void emma2rh_gpio_irq_enable(unsigned int irq)
{
u32 reg;
irq -= EMMA2RH_GPIO_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_disable(unsigned int irq)
{
u32 reg;
irq -= EMMA2RH_GPIO_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_ack(unsigned int irq)
{
u32 reg;
irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_end(unsigned int irq)
{
u32 reg;
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
irq -= EMMA2RH_GPIO_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
}
struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable,
.mask_ack = emma2rh_gpio_irq_ack,
.unmask = emma2rh_gpio_irq_enable,
.end = emma2rh_gpio_irq_end,
};
void emma2rh_gpio_irq_init(void)
{
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller);
}
static struct irqaction irq_cascade = {
.handler = no_action,
.flags = 0,
.mask = CPU_MASK_NONE,
.name = "cascade",
.dev_id = NULL,
.next = NULL,
};
/*
* the first level int-handler will jump here if it is a emma2rh irq
*/
void emma2rh_irq_dispatch(void)
{
u32 intStatus;
u32 bitmask;
u32 i;
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
#ifdef EMMA2RH_SW_CASCADE
if (intStatus &
(1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
u32 swIntStatus;
swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (swIntStatus & bitmask) {
do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
return;
}
}
}
#endif
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
#ifdef EMMA2RH_GPIO_CASCADE
if (intStatus &
(1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
u32 gpioIntStatus;
gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (gpioIntStatus & bitmask) {
do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
return;
}
}
}
#endif
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
}
void __init arch_init_irq(void)
{
u32 reg;
/* by default, interrupts are disabled. */
emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
clear_c0_status(0xff00);
set_c0_status(0x0400);
#define GPIO_PCI (0xf<<15)
/* setup GPIO interrupt for PCI interface */
/* direction input */
reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
/* disable interrupt */
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
/* level triggerd */
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
/* interrupt clear */
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
/* init all controllers */
emma2rh_irq_init();
emma2rh_sw_irq_init();
emma2rh_gpio_irq_init();
mips_cpu_irq_init();
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7);
else if (pending & STATUSF_IP2)
emma2rh_irq_dispatch();
else if (pending & STATUSF_IP1)
do_IRQ(CPU_IRQ_BASE + 1);
else if (pending & STATUSF_IP0)
do_IRQ(CPU_IRQ_BASE + 0);
else
spurious_interrupt();
}

2
arch/mips/emma2rh/markeins/led.c → arch/mips/emma/markeins/led.c
View File

@ -21,7 +21,7 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
const unsigned long clear = 0x20202020;

2
arch/mips/emma2rh/markeins/platform.c → arch/mips/emma/markeins/platform.c
View File

@ -36,7 +36,7 @@
#include <asm/reboot.h>
#include <asm/traps.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */

2
arch/mips/emma2rh/markeins/setup.c → arch/mips/emma/markeins/setup.c
View File

@ -29,7 +29,7 @@
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */

105
arch/mips/emma2rh/common/irq.c
View File

@ -1,105 +0,0 @@
/*
* arch/mips/emma2rh/common/irq.c
* This file is common irq dispatcher.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/emma2rh/emma2rh.h>
/*
* the first level int-handler will jump here if it is a emma2rh irq
*/
void emma2rh_irq_dispatch(void)
{
u32 intStatus;
u32 bitmask;
u32 i;
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
& emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
#ifdef EMMA2RH_SW_CASCADE
if (intStatus &
(1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
u32 swIntStatus;
swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (swIntStatus & bitmask) {
do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
return;
}
}
}
#endif
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
& emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
#ifdef EMMA2RH_GPIO_CASCADE
if (intStatus &
(1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
u32 gpioIntStatus;
gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
if (gpioIntStatus & bitmask) {
do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
return;
}
}
}
#endif
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
& emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
if (intStatus & bitmask) {
do_IRQ(EMMA2RH_IRQ_BASE + i);
return;
}
}
}

106
arch/mips/emma2rh/common/irq_emma2rh.c
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@ -1,106 +0,0 @@
/*
* arch/mips/emma2rh/common/irq_emma2rh.c
* This file defines the irq handler for EMMA2RH.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* EMMA2RH defines 64 IRQs.
*
* This file exports one function:
* emma2rh_irq_init(u32 irq_base);
*/
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/debug.h>
#include <asm/emma2rh/emma2rh.h>
/* number of total irqs supported by EMMA2RH */
#define NUM_EMMA2RH_IRQ 96
static int emma2rh_irq_base = -1;
void ll_emma2rh_irq_enable(int);
void ll_emma2rh_irq_disable(int);
static void emma2rh_irq_enable(unsigned int irq)
{
ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
}
static void emma2rh_irq_disable(unsigned int irq)
{
ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
}
struct irq_chip emma2rh_irq_controller = {
.name = "emma2rh_irq",
.ack = emma2rh_irq_disable,
.mask = emma2rh_irq_disable,
.mask_ack = emma2rh_irq_disable,
.unmask = emma2rh_irq_enable,
};
void emma2rh_irq_init(u32 irq_base)
{
u32 i;
for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
set_irq_chip_and_handler(i, &emma2rh_irq_controller,
handle_level_irq);
emma2rh_irq_base = irq_base;
}
void ll_emma2rh_irq_enable(int emma2rh_irq)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
reg_index = EMMA2RH_BHIF_INT_EN_0
+ (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
* (emma2rh_irq / 32);
reg_value = emma2rh_in32(reg_index);
reg_bitmask = 0x1 << (emma2rh_irq % 32);
db_assert((reg_value & reg_bitmask) == 0);
emma2rh_out32(reg_index, reg_value | reg_bitmask);
}
void ll_emma2rh_irq_disable(int emma2rh_irq)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
reg_index = EMMA2RH_BHIF_INT_EN_0
+ (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
* (emma2rh_irq / 32);
reg_value = emma2rh_in32(reg_index);
reg_bitmask = 0x1 << (emma2rh_irq % 32);
db_assert((reg_value & reg_bitmask) != 0);
emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
}

132
arch/mips/emma2rh/markeins/irq.c
View File

@ -1,132 +0,0 @@
/*
* arch/mips/emma2rh/markeins/irq.c
* This file defines the irq handler for EMMA2RH.
*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/delay.h>
#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/debug.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/emma2rh/emma2rh.h>
/*
* IRQ mapping
*
* 0-7: 8 CPU interrupts
* 0 - software interrupt 0
* 1 - software interrupt 1
* 2 - most Vrc5477 interrupts are routed to this pin
* 3 - (optional) some other interrupts routed to this pin for debugg
* 4 - not used
* 5 - not used
* 6 - not used
* 7 - cpu timer (used by default)
*
*/
extern void emma2rh_sw_irq_init(u32 base);
extern void emma2rh_gpio_irq_init(u32 base);
extern void emma2rh_irq_init(u32 base);
extern void emma2rh_irq_dispatch(void);
static struct irqaction irq_cascade = {
.handler = no_action,
.flags = 0,
.mask = CPU_MASK_NONE,
.name = "cascade",
.dev_id = NULL,
.next = NULL,
};
void __init arch_init_irq(void)
{
u32 reg;
db_run(printk("markeins_irq_setup invoked.\n"));
/* by default, interrupts are disabled. */
emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
clear_c0_status(0xff00);
set_c0_status(0x0400);
#define GPIO_PCI (0xf<<15)
/* setup GPIO interrupt for PCI interface */
/* direction input */
reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
/* disable interrupt */
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
/* level triggerd */
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
/* interrupt clear */
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
/* init all controllers */
emma2rh_irq_init(EMMA2RH_IRQ_BASE);
emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
mips_cpu_irq_init();
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7);
else if (pending & STATUSF_IP2)
emma2rh_irq_dispatch();
else if (pending & STATUSF_IP1)
do_IRQ(CPU_IRQ_BASE + 1);
else if (pending & STATUSF_IP0)
do_IRQ(CPU_IRQ_BASE + 0);
else
spurious_interrupt();
}

158
arch/mips/emma2rh/markeins/irq_markeins.c
View File

@ -1,158 +0,0 @@
/*
* arch/mips/emma2rh/markeins/irq_markeins.c
* This file defines the irq handler for Mark-eins.
*
* Copyright (C) NEC Electronics Corporation 2004-2006
*
* This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
*
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/debug.h>
#include <asm/emma2rh/emma2rh.h>
static int emma2rh_sw_irq_base = -1;
static int emma2rh_gpio_irq_base = -1;
void ll_emma2rh_sw_irq_enable(int reg);
void ll_emma2rh_sw_irq_disable(int reg);
void ll_emma2rh_gpio_irq_enable(int reg);
void ll_emma2rh_gpio_irq_disable(int reg);
static void emma2rh_sw_irq_enable(unsigned int irq)
{
ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
}
static void emma2rh_sw_irq_disable(unsigned int irq)
{
ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
}
struct irq_chip emma2rh_sw_irq_controller = {
.name = "emma2rh_sw_irq",
.ack = emma2rh_sw_irq_disable,
.mask = emma2rh_sw_irq_disable,
.mask_ack = emma2rh_sw_irq_disable,
.unmask = emma2rh_sw_irq_enable,
};
void emma2rh_sw_irq_init(u32 irq_base)
{
u32 i;
for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
handle_level_irq);
emma2rh_sw_irq_base = irq_base;
}
void ll_emma2rh_sw_irq_enable(int irq)
{
u32 reg;
db_assert(irq >= 0);
db_assert(irq < NUM_EMMA2RH_IRQ_SW);
reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
}
void ll_emma2rh_sw_irq_disable(int irq)
{
u32 reg;
db_assert(irq >= 0);
db_assert(irq < 32);
reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
}
static void emma2rh_gpio_irq_enable(unsigned int irq)
{
ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
}
static void emma2rh_gpio_irq_disable(unsigned int irq)
{
ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
}
static void emma2rh_gpio_irq_ack(unsigned int irq)
{
irq -= emma2rh_gpio_irq_base;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
ll_emma2rh_gpio_irq_disable(irq);
}
static void emma2rh_gpio_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
}
struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable,
.mask_ack = emma2rh_gpio_irq_ack,
.unmask = emma2rh_gpio_irq_enable,
.end = emma2rh_gpio_irq_end,
};
void emma2rh_gpio_irq_init(u32 irq_base)
{
u32 i;
for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip(i, &emma2rh_gpio_irq_controller);
emma2rh_gpio_irq_base = irq_base;
}
void ll_emma2rh_gpio_irq_enable(int irq)
{
u32 reg;
db_assert(irq >= 0);
db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
void ll_emma2rh_gpio_irq_disable(int irq)
{
u32 reg;
db_assert(irq >= 0);
db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}

15
arch/mips/include/asm/emma2rh/emma2rh.h → arch/mips/include/asm/emma/emma2rh.h
View File

@ -1,5 +1,5 @@
/*
* include/asm-mips/emma2rh/emma2rh.h
* arch/mips/include/asm/emma/emma2rh.h
* This file is EMMA2RH common header.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
@ -21,8 +21,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_EMMA2RH_EMMA2RH_H
#define __ASM_EMMA2RH_EMMA2RH_H
#ifndef __ASM_EMMA_EMMA2RH_H
#define __ASM_EMMA_EMMA2RH_H
#include <irq.h>
@ -206,7 +206,6 @@ static inline void emma2rh_out32(u32 offset, u32 val)
static inline u32 emma2rh_in32(u32 offset)
{
u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
@ -219,7 +218,6 @@ static inline void emma2rh_out16(u32 offset, u16 val)
static inline u16 emma2rh_in16(u32 offset)
{
u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
@ -232,7 +230,6 @@ static inline void emma2rh_out8(u32 offset, u8 val)
static inline u8 emma2rh_in8(u32 offset)
{
u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
@ -324,10 +321,10 @@ static inline u8 emma2rh_in8(u32 offset)
/*
* include the board dependent part
*/
#if defined(CONFIG_MARKEINS)
#include <asm/emma2rh/markeins.h>
#ifdef CONFIG_NEC_MARKEINS
#include <asm/emma/markeins.h>
#else
#error "Unknown EMMA2RH board!"
#endif
#endif /* __ASM_EMMA2RH_EMMA2RH_H */
#endif /* __ASM_EMMA_EMMA2RH_H */

0
arch/mips/include/asm/emma2rh/markeins.h → arch/mips/include/asm/emma/markeins.h
View File

30
arch/mips/include/asm/mach-lemote/pci.h Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
*
* This program is free software; you can redistribute it
* and/or modify it under the terms of the GNU General
* Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the Free
* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
* 02139, USA.
*/
#ifndef _LEMOTE_PCI_H_
#define _LEMOTE_PCI_H_
#define LOONGSON2E_PCI_MEM_START 0x14000000UL
#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL
#define LOONGSON2E_PCI_IO_START 0x00004000UL
#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL
#endif /* !_LEMOTE_PCI_H_ */

172
arch/mips/include/asm/mach-pnx833x/gpio.h Normal file
View File

@ -0,0 +1,172 @@
/*
* gpio.h: GPIO Support for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
#define __ASM_MIPS_MACH_PNX833X_GPIO_H
/* BIG FAT WARNING: races danger!
No protections exist here. Current users are only early init code,
when locking is not needed because no cuncurency yet exists there,
and GPIO IRQ dispatcher, which does locking.
However, if many uses will ever happen, proper locking will be needed
- including locking between different uses
*/
#include "pnx833x.h"
#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
/* Initialize GPIO to a known state */
static inline void pnx833x_gpio_init(void)
{
PNX833X_PIO_DIR = 0;
PNX833X_PIO_DIR2 = 0;
PNX833X_PIO_SEL = 0;
PNX833X_PIO_SEL2 = 0;
PNX833X_PIO_INT_EDGE = 0;
PNX833X_PIO_INT_HI = 0;
PNX833X_PIO_INT_LO = 0;
/* clear any GPIO interrupt requests */
PNX833X_PIO_INT_CLEAR = 0xffff;
PNX833X_PIO_INT_CLEAR = 0;
PNX833X_PIO_INT_ENABLE = 0;
}
/* Select GPIO direction for a pin */
static inline void pnx833x_gpio_select_input(unsigned int pin)
{
if (pin < 32)
CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
else
CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
}
static inline void pnx833x_gpio_select_output(unsigned int pin)
{
if (pin < 32)
SET_REG_BIT(PNX833X_PIO_DIR, pin);
else
SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
}
/* Select GPIO or alternate function for a pin */
static inline void pnx833x_gpio_select_function_io(unsigned int pin)
{
if (pin < 32)
CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
else
CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
}
static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
{
if (pin < 32)
SET_REG_BIT(PNX833X_PIO_SEL, pin);
else
SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
}
/* Read GPIO pin */
static inline int pnx833x_gpio_read(unsigned int pin)
{
if (pin < 32)
return (PNX833X_PIO_IN >> pin) & 1;
else
return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
}
/* Write GPIO pin */
static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
{
if (pin < 32) {
if (val)
SET_REG_BIT(PNX833X_PIO_OUT, pin);
else
CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
} else {
if (val)
SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
else
CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
}
}
/* Configure GPIO interrupt */
#define GPIO_INT_NONE 0
#define GPIO_INT_LEVEL_LOW 1
#define GPIO_INT_LEVEL_HIGH 2
#define GPIO_INT_EDGE_RISING 3
#define GPIO_INT_EDGE_FALLING 4
#define GPIO_INT_EDGE_BOTH 5
static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
{
switch (when) {
case GPIO_INT_LEVEL_LOW:
CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_LEVEL_HIGH:
CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_EDGE_RISING:
SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_EDGE_FALLING:
SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
case GPIO_INT_EDGE_BOTH:
SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
default:
CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
break;
}
}
/* Enable/disable GPIO interrupt */
static inline void pnx833x_gpio_enable_irq(unsigned int pin)
{
SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
}
static inline void pnx833x_gpio_disable_irq(unsigned int pin)
{
CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
}
/* Clear GPIO interrupt request */
static inline void pnx833x_gpio_clear_irq(unsigned int pin)
{
SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
}
#endif

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/*
* irq.h: IRQ mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
/*
* The "IRQ numbers" are completely virtual.
*
* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
* numbers 49..64 for (virtual) GPIO interrupts.
*
* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
* connected to PIC, which uses core hardware interrupt 2, and also
* a timer interrupt through hardware interrupt 5.
* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
* numbers 65..80 for (virtual) GPIO interrupts.
*
*/
#include <irq.h>
#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
/* Interrupts supported by PIC */
#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
#if defined(CONFIG_SOC_PNX8335)
#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
#endif
/* GPIO interrupts */
#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
#endif

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/*
* irq.h: IRQ mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
#define __ASM_MIPS_MACH_PNX833X_IRQ_H
/*
* The "IRQ numbers" are completely virtual.
*
* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
* numbers 49..64 for (virtual) GPIO interrupts.
*
* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
* connected to PIC, which uses core hardware interrupt 2, and also
* a timer interrupt through hardware interrupt 5.
* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
* numbers 65..80 for (virtual) GPIO interrupts.
*
*/
#if defined(CONFIG_SOC_PNX8335)
#define PNX833X_PIC_NUM_IRQ 58
#else
#define PNX833X_PIC_NUM_IRQ 37
#endif
#define MIPS_CPU_NUM_IRQ 8
#define PNX833X_GPIO_NUM_IRQ 16
#define MIPS_CPU_IRQ_BASE 0
#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
#endif

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/*
* pnx833x.h: Register mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
/* All regs are accessed in KSEG1 */
#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
/* Read access to multibit fields */
#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
/* Use PNX833X_FIELD to extract a field from val */
#define PNX_FIELD(cpu, val, reg, field) \
(((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
PNX##cpu##_##reg##_##field##_SHIFT)
#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
/* Use PNX833X_REGFIELD to extract a field from a register */
#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
#define PNX_WRITEFIELD(cpu, val, reg, field) \
(PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
((val) << PNX##cpu##_##reg##_##field##_SHIFT))
#define PNX833X_WRITEFIELD(val, reg, field) \
PNX_WRITEFIELD(833X, val, reg, field)
#define PNX8330_WRITEFIELD(val, reg, field) \
PNX_WRITEFIELD(8330, val, reg, field)
#define PNX8335_WRITEFIELD(val, reg, field) \
PNX_WRITEFIELD(8335, val, reg, field)
/* Macros to detect CPU type */
#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
#define PNX8330_CONFIG_MODULE_MAJREV 4
#define PNX8335_CONFIG_MODULE_MAJREV 5
#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
PNX8330_CONFIG_MODULE_MAJREV)
#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
PNX8335_CONFIG_MODULE_MAJREV)
#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
#define PNX833X_PIO_IN PNX833X_REG(0xF000)
#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
(PNX833X_MIU_CONFIG_SPI = \
((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
/* I/O location(gets remapped)*/
#define PNX8335_NAND_BASE 0x18000000
/* I/O location with CLE high */
#define PNX8335_NAND_CLE_MASK 0x00100000
/* I/O location with ALE high */
#define PNX8335_NAND_ALE_MASK 0x00010000
#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
#endif

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
#define __ASM_MIPS_MACH_PNX833X_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */

26
arch/mips/include/asm/mach-tx49xx/mangle-port.h Normal file
View File

@ -0,0 +1,26 @@
#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H
#define __ASM_MACH_TX49XX_MANGLE_PORT_H
#define __swizzle_addr_b(port) (port)
#define __swizzle_addr_w(port) (port)
#define __swizzle_addr_l(port) (port)
#define __swizzle_addr_q(port) (port)
#define ioswabb(a, x) (x)
#define __mem_ioswabb(a, x) (x)
#if defined(CONFIG_TOSHIBA_RBTX4939) && \
(defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \
defined(__BIG_ENDIAN)
#define NEEDS_TXX9_IOSWABW
extern u16 (*ioswabw)(volatile u16 *a, u16 x);
extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
#else
#define ioswabw(a, x) le16_to_cpu(x)
#define __mem_ioswabw(a, x) (x)
#endif
#define ioswabl(a, x) le32_to_cpu(x)
#define __mem_ioswabl(a, x) (x)
#define ioswabq(a, x) le64_to_cpu(x)
#define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */

1
arch/mips/include/asm/mipsregs.h
View File

@ -192,6 +192,7 @@
#define PM_16M 0x01ffe000
#define PM_64M 0x07ffe000
#define PM_256M 0x1fffe000
#define PM_1G 0x7fffe000
#endif

2
arch/mips/include/asm/module.h
View File

@ -98,6 +98,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "R5000 "
#elif defined CONFIG_CPU_R5432
#define MODULE_PROC_FAMILY "R5432 "
#elif defined CONFIG_CPU_R5500
#define MODULE_PROC_FAMILY "R5500 "
#elif defined CONFIG_CPU_R6000
#define MODULE_PROC_FAMILY "R6000 "
#elif defined CONFIG_CPU_NEVADA

17
arch/mips/include/asm/ptrace.h
View File

@ -80,25 +80,25 @@ enum pt_watch_style {
pt_watch_style_mips64
};
struct mips32_watch_regs {
uint32_t watchlo[8];
unsigned int watchlo[8];
/* Lower 16 bits of watchhi. */
uint16_t watchhi[8];
unsigned short watchhi[8];
/* Valid mask and I R W bits.
* bit 0 -- 1 if W bit is usable.
* bit 1 -- 1 if R bit is usable.
* bit 2 -- 1 if I bit is usable.
* bits 3 - 11 -- Valid watchhi mask bits.
*/
uint16_t watch_masks[8];
unsigned short watch_masks[8];
/* The number of valid watch register pairs. */
uint32_t num_valid;
unsigned int num_valid;
} __attribute__((aligned(8)));
struct mips64_watch_regs {
uint64_t watchlo[8];
uint16_t watchhi[8];
uint16_t watch_masks[8];
uint32_t num_valid;
unsigned long long watchlo[8];
unsigned short watchhi[8];
unsigned short watch_masks[8];
unsigned int num_valid;
} __attribute__((aligned(8)));
struct pt_watch_regs {
@ -116,6 +116,7 @@ struct pt_watch_regs {
#include <linux/compiler.h>
#include <linux/linkage.h>
#include <linux/types.h>
#include <asm/isadep.h>
struct task_struct;

5
arch/mips/include/asm/txx9/generic.h
View File

@ -86,4 +86,9 @@ void txx9_iocled_init(unsigned long baseaddr,
int basenum, unsigned int num, int lowactive,
const char *color, char **deftriggers);
/* 7SEG LED */
void txx9_7segled_init(unsigned int num,
void (*putc)(unsigned int pos, unsigned char val));
int txx9_7segled_putc(unsigned int pos, char c);
#endif /* __ASM_TXX9_GENERIC_H */

1
arch/mips/kernel/Makefile
View File

@ -33,6 +33,7 @@ obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o

4
arch/mips/kernel/scall32-o32.S
View File

@ -180,7 +180,7 @@ bad_stack:
* The system call does not exist in this kernel
*/
illegal_syscall:
li v0, -ENOSYS # error
li v0, ENOSYS # error
sw v0, PT_R2(sp)
li t0, 1 # set error flag
sw t0, PT_R7(sp)
@ -293,7 +293,7 @@ bad_alignment:
jr t2
/* Unreached */
einval: li v0, -EINVAL
einval: li v0, -ENOSYS
jr ra
END(sys_syscall)

2
arch/mips/kernel/scall64-64.S
View File

@ -117,7 +117,7 @@ syscall_trace_entry:
illegal_syscall:
/* This also isn't a 64-bit syscall, throw an error. */
li v0, -ENOSYS # error
li v0, ENOSYS # error
sd v0, PT_R2(sp)
li t0, 1 # set error flag
sd t0, PT_R7(sp)

4
arch/mips/kernel/setup.c
View File

@ -601,8 +601,8 @@ static int __init debugfs_mips(void)
struct dentry *d;
d = debugfs_create_dir("mips", NULL);
if (IS_ERR(d))
return PTR_ERR(d);
if (!d)
return -ENOMEM;
mips_debugfs_dir = d;
return 0;
}

6
arch/mips/kernel/smp.c
View File

@ -163,8 +163,10 @@ static void stop_this_cpu(void *dummy)
* Remove this CPU:
*/
cpu_clear(smp_processor_id(), cpu_online_map);
local_irq_enable(); /* May need to service _machine_restart IPI */
for (;;); /* Wait if available. */
for (;;) {
if (cpu_wait)
(*cpu_wait)(); /* Wait if available. */
}
}
void smp_send_stop(void)

8
arch/mips/kernel/unaligned.c
View File

@ -560,12 +560,12 @@ static int __init debugfs_unaligned(void)
return -ENODEV;
d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
mips_debugfs_dir, &unaligned_instructions);
if (IS_ERR(d))
return PTR_ERR(d);
if (!d)
return -ENOMEM;
d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
mips_debugfs_dir, &unaligned_action);
if (IS_ERR(d))
return PTR_ERR(d);
if (!d)
return -ENOMEM;
return 0;
}
__initcall(debugfs_unaligned);

13
arch/mips/lemote/lm2e/pci.c
View File

@ -30,19 +30,20 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mips-boards/bonito64.h>
#include <asm/mach-lemote/pci.h>
extern struct pci_ops bonito64_pci_ops;
static struct resource loongson2e_pci_mem_resource = {
.name = "LOONGSON2E PCI MEM",
.start = 0x14000000UL,
.end = 0x1fffffffUL,
.start = LOONGSON2E_PCI_MEM_START,
.end = LOONGSON2E_PCI_MEM_END,
.flags = IORESOURCE_MEM,
};
static struct resource loongson2e_pci_io_resource = {
.name = "LOONGSON2E PCI IO MEM",
.start = 0x00004000UL,
.start = LOONGSON2E_PCI_IO_START,
.end = IO_SPACE_LIMIT,
.flags = IORESOURCE_IO,
};
@ -82,6 +83,12 @@ static void __init ict_pcimap(void)
static int __init pcibios_init(void)
{
ict_pcimap();
loongson2e_pci_controller.io_map_base =
(unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE,
loongson2e_pci_io_resource.end -
loongson2e_pci_io_resource.start + 1);
register_pci_controller(&loongson2e_pci_controller);
return 0;

11
arch/mips/lemote/lm2e/setup.c
View File

@ -34,6 +34,7 @@
#include <asm/mc146818-time.h>
#include <asm/time.h>
#include <asm/wbflush.h>
#include <asm/mach-lemote/pci.h>
#ifdef CONFIG_VT
#include <linux/console.h>
@ -42,12 +43,6 @@
extern void mips_reboot_setup(void);
#ifdef CONFIG_64BIT
#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
#else
#define PTR_PAD(p) (p)
#endif
unsigned long cpu_clock_freq;
unsigned long bus_clock;
unsigned int memsize;
@ -80,8 +75,8 @@ static void wbflush_loongson2e(void)
void __init plat_mem_setup(void)
{
set_io_port_base(PTR_PAD(0xbfd00000));
set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE,
IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1));
mips_reboot_setup();
__wbflush = wbflush_loongson2e;

1
arch/mips/lib/Makefile
View File

@ -18,6 +18,7 @@ obj-$(CONFIG_CPU_R4300) += dump_tlb.o
obj-$(CONFIG_CPU_R4X00) += dump_tlb.o
obj-$(CONFIG_CPU_R5000) += dump_tlb.o
obj-$(CONFIG_CPU_R5432) += dump_tlb.o
obj-$(CONFIG_CPU_R5500) += dump_tlb.o
obj-$(CONFIG_CPU_R6000) +=
obj-$(CONFIG_CPU_R8000) +=
obj-$(CONFIG_CPU_RM7000) += dump_tlb.o

1
arch/mips/lib/dump_tlb.c
View File

@ -25,6 +25,7 @@ static inline const char *msk2str(unsigned int mask)
case PM_16M: return "16Mb";
case PM_64M: return "64Mb";
case PM_256M: return "256Mb";
case PM_1G: return "1Gb";
#endif
}
return "";

8
arch/mips/math-emu/cp1emu.c
View File

@ -1299,12 +1299,12 @@ static int __init debugfs_fpuemu(void)
if (!mips_debugfs_dir)
return -ENODEV;
dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
if (IS_ERR(dir))
return PTR_ERR(dir);
if (!dir)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(vars); i++) {
d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
if (IS_ERR(d))
return PTR_ERR(d);
if (!d)
return -ENOMEM;
}
return 0;
}

1
arch/mips/mm/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o

2
arch/mips/mm/dma-default.c
View File

@ -324,7 +324,6 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
if (cpu_is_noncoherent_r10000(dev))
__dma_sync((unsigned long)page_address(sg_page(sg)),
sg->length, direction);
plat_unmap_dma_mem(sg->dma_address);
}
}
@ -342,7 +341,6 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele
if (!plat_device_is_coherent(dev))
__dma_sync((unsigned long)page_address(sg_page(sg)),
sg->length, direction);
plat_unmap_dma_mem(sg->dma_address);
}
}

3
arch/mips/nxp/pnx833x/common/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y := interrupts.o platform.o prom.o setup.o reset.o
EXTRA_CFLAGS += -Werror

380
arch/mips/nxp/pnx833x/common/interrupts.c Normal file
View File

@ -0,0 +1,380 @@
/*
* interrupts.c: Interrupt mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/hardirq.h>
#include <linux/interrupt.h>
#include <asm/mipsregs.h>
#include <asm/irq_cpu.h>
#include <irq.h>
#include <irq-mapping.h>
#include <gpio.h>
static int mips_cpu_timer_irq;
static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
{
0, /* unused */
4, /* PNX833X_PIC_I2C0_INT 1 */
4, /* PNX833X_PIC_I2C1_INT 2 */
1, /* PNX833X_PIC_UART0_INT 3 */
1, /* PNX833X_PIC_UART1_INT 4 */
6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */
6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */
7, /* PNX833X_PIC_GPIO_INT 7 */
4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */
5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */
4, /* PNX833X_PIC_CONFIG_INT 10 */
4, /* PNX833X_PIC_AOI_INT 11 */
9, /* PNX833X_PIC_SYNC_INT 12 */
9, /* PNX8335_PIC_SATA_INT 13 */
4, /* PNX833X_PIC_OSD_INT 14 */
9, /* PNX833X_PIC_DISP1_INT 15 */
4, /* PNX833X_PIC_DEINTERLACER_INT 16 */
9, /* PNX833X_PIC_DISPLAY2_INT 17 */
4, /* PNX833X_PIC_VC_INT 18 */
4, /* PNX833X_PIC_SC_INT 19 */
9, /* PNX833X_PIC_IDE_INT 20 */
9, /* PNX833X_PIC_IDE_DMA_INT 21 */
6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */
6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */
4, /* PNX833X_PIC_SGDX_DMA_INT 24 */
4, /* PNX833X_PIC_TS_OUT_INT 25 */
4, /* PNX833X_PIC_IR_INT 26 */
3, /* PNX833X_PIC_VMSP1_INT 27 */
3, /* PNX833X_PIC_VMSP2_INT 28 */
4, /* PNX833X_PIC_PIBC_INT 29 */
4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */
4, /* PNX833X_PIC_SGDX_TPD_INT 31 */
5, /* PNX833X_PIC_USB_INT 32 */
4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */
4, /* PNX833X_PIC_CLOCK_INT 34 */
4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */
4, /* PNX833X_PIC_VMSP_DMA_INT 36 */
#if defined(CONFIG_SOC_PNX8335)
4, /* PNX8335_PIC_MIU_INT 37 */
4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */
9, /* PNX8335_PIC_SYNC_HD_INT 39 */
9, /* PNX8335_PIC_DISP_HD_INT 40 */
9, /* PNX8335_PIC_DISP_SCALER_INT 41 */
4, /* PNX8335_PIC_OSD_HD1_INT 42 */
4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */
4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */
4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */
4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */
4, /* PNX8335_PIC_DENC_TTX_INT 47 */
4, /* PNX8335_PIC_MMI_SIF0_INT 48 */
4, /* PNX8335_PIC_MMI_SIF1_INT 49 */
4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */
4, /* PNX8335_PIC_PIBCS_INT 51 */
12, /* PNX8335_PIC_ETHERNET_INT 52 */
3, /* PNX8335_PIC_VMSP1_0_INT 53 */
3, /* PNX8335_PIC_VMSP1_1_INT 54 */
4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */
4, /* PNX8335_PIC_TDGR_DE_INT 56 */
4, /* PNX8335_PIC_IR1_IRQ_INT 57 */
#endif
};
static void pnx833x_timer_dispatch(void)
{
do_IRQ(mips_cpu_timer_irq);
}
static void pic_dispatch(void)
{
unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
unsigned long priority = PNX833X_PIC_INT_PRIORITY;
PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
if (irq == PNX833X_PIC_GPIO_INT) {
unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
int pin;
while ((pin = ffs(mask & 0xffff))) {
pin -= 1;
do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
mask &= ~(1 << pin);
}
} else {
do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
}
PNX833X_PIC_INT_PRIORITY = priority;
} else {
printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
}
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & STATUSF_IP4)
pic_dispatch();
else if (pending & STATUSF_IP7)
do_IRQ(PNX833X_TIMER_IRQ);
else
spurious_interrupt();
}
static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
{
/* Currently we do this by setting IRQ priority to 1.
If priority support is being implemented, 1 should be repalced
by a better value. */
PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
}
static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
{
/* Disable IRQ by writing setting it's priority to 0 */
PNX833X_PIC_INT_REG(irq) = 0;
}
static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */
#define IRQFLAG_STARTED 1
#define IRQFLAG_DISABLED 2
static DEFINE_SPINLOCK(pnx833x_irq_lock);
static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
{
unsigned long flags;
unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
spin_lock_irqsave(&pnx833x_irq_lock, flags);
irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */
pnx833x_hard_enable_pic_irq(pic_irq);
spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
return 0;
}
static void pnx833x_shutdown_pic_irq(unsigned int irq)
{
unsigned long flags;
unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
spin_lock_irqsave(&pnx833x_irq_lock, flags);
irqflags[pic_irq] = 0; /* not started */
pnx833x_hard_disable_pic_irq(pic_irq);
spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
}
static void pnx833x_enable_pic_irq(unsigned int irq)
{
unsigned long flags;
unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
spin_lock_irqsave(&pnx833x_irq_lock, flags);
irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
if (irqflags[pic_irq] == IRQFLAG_STARTED)
pnx833x_hard_enable_pic_irq(pic_irq);
spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
}
static void pnx833x_disable_pic_irq(unsigned int irq)
{
unsigned long flags;
unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
spin_lock_irqsave(&pnx833x_irq_lock, flags);
irqflags[pic_irq] |= IRQFLAG_DISABLED;
pnx833x_hard_disable_pic_irq(pic_irq);
spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
}
static void pnx833x_ack_pic_irq(unsigned int irq)
{
}
static void pnx833x_end_pic_irq(unsigned int irq)
{
}
static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
{
int pin = irq - PNX833X_GPIO_IRQ_BASE;
unsigned long flags;
spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
pnx833x_gpio_enable_irq(pin);
spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
return 0;
}
static void pnx833x_enable_gpio_irq(unsigned int irq)
{
int pin = irq - PNX833X_GPIO_IRQ_BASE;
unsigned long flags;
spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
pnx833x_gpio_enable_irq(pin);
spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
}
static void pnx833x_disable_gpio_irq(unsigned int irq)
{
int pin = irq - PNX833X_GPIO_IRQ_BASE;
unsigned long flags;
spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
pnx833x_gpio_disable_irq(pin);
spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
}
static void pnx833x_ack_gpio_irq(unsigned int irq)
{
}
static void pnx833x_end_gpio_irq(unsigned int irq)
{
int pin = irq - PNX833X_GPIO_IRQ_BASE;
unsigned long flags;
spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
pnx833x_gpio_clear_irq(pin);
spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
}
static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
{
int pin = irq - PNX833X_GPIO_IRQ_BASE;
int gpio_mode;
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
gpio_mode = GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
gpio_mode = GPIO_INT_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
gpio_mode = GPIO_INT_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
gpio_mode = GPIO_INT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
gpio_mode = GPIO_INT_LEVEL_LOW;
break;
default:
gpio_mode = GPIO_INT_NONE;
break;
}
pnx833x_gpio_setup_irq(gpio_mode, pin);
return 0;
}
static struct irq_chip pnx833x_pic_irq_type = {
.typename = "PNX-PIC",
.startup = pnx833x_startup_pic_irq,
.shutdown = pnx833x_shutdown_pic_irq,
.enable = pnx833x_enable_pic_irq,
.disable = pnx833x_disable_pic_irq,
.ack = pnx833x_ack_pic_irq,
.end = pnx833x_end_pic_irq
};
static struct irq_chip pnx833x_gpio_irq_type = {
.typename = "PNX-GPIO",
.startup = pnx833x_startup_gpio_irq,
.shutdown = pnx833x_disable_gpio_irq,
.enable = pnx833x_enable_gpio_irq,
.disable = pnx833x_disable_gpio_irq,
.ack = pnx833x_ack_gpio_irq,
.end = pnx833x_end_gpio_irq,
.set_type = pnx833x_set_type_gpio_irq
};
void __init arch_init_irq(void)
{
unsigned int irq;
/* setup standard internal cpu irqs */
mips_cpu_irq_init();
/* Set IRQ information in irq_desc */
for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
pnx833x_hard_disable_pic_irq(irq);
set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
}
for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
/* Set PIC priority limiter register to 0 */
PNX833X_PIC_INT_PRIORITY = 0;
/* Setup GPIO IRQ dispatching */
pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
/* Enable PIC IRQs (HWIRQ2) */
if (cpu_has_vint)
set_vi_handler(4, pic_dispatch);
write_c0_status(read_c0_status() | IE_IRQ2);
}
unsigned int __cpuinit get_c0_compare_int(void)
{
if (cpu_has_vint)
set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
return mips_cpu_timer_irq;
}
void __init plat_time_init(void)
{
/* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
extern unsigned long mips_hpt_frequency;
unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
/* Functional clock is disabled so use crystal frequency */
mips_hpt_frequency = 25;
} else {
#if defined(CONFIG_SOC_PNX8335)
/* Functional clock is enabled, so get clock multiplier */
mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
#else
static const unsigned long int freq[4] = {240, 160, 120, 80};
mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
#endif
}
printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
mips_hpt_frequency *= 500000;
}

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/*
* platform.c: platform support for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* Based on software written by:
* Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/resource.h>
#include <linux/serial.h>
#include <linux/serial_pnx8xxx.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#ifdef CONFIG_I2C_PNX0105
/* Until i2c driver available in kernel.*/
#include <linux/i2c-pnx0105.h>
#endif
#include <irq.h>
#include <irq-mapping.h>
#include <pnx833x.h>
static u64 uart_dmamask = DMA_32BIT_MASK;
static struct resource pnx833x_uart_resources[] = {
[0] = {
.start = PNX833X_UART0_PORTS_START,
.end = PNX833X_UART0_PORTS_END,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PNX833X_PIC_UART0_INT,
.end = PNX833X_PIC_UART0_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = PNX833X_UART1_PORTS_START,
.end = PNX833X_UART1_PORTS_END,
.flags = IORESOURCE_MEM,
},
[3] = {
.start = PNX833X_PIC_UART1_INT,
.end = PNX833X_PIC_UART1_INT,
.flags = IORESOURCE_IRQ,
},
};
struct pnx8xxx_port pnx8xxx_ports[] = {
[0] = {
.port = {
.type = PORT_PNX8XXX,
.iotype = UPIO_MEM,
.membase = (void __iomem *)PNX833X_UART0_PORTS_START,
.mapbase = PNX833X_UART0_PORTS_START,
.irq = PNX833X_PIC_UART0_INT,
.uartclk = 3692300,
.fifosize = 16,
.flags = UPF_BOOT_AUTOCONF,
.line = 0,
},
},
[1] = {
.port = {
.type = PORT_PNX8XXX,
.iotype = UPIO_MEM,
.membase = (void __iomem *)PNX833X_UART1_PORTS_START,
.mapbase = PNX833X_UART1_PORTS_START,
.irq = PNX833X_PIC_UART1_INT,
.uartclk = 3692300,
.fifosize = 16,
.flags = UPF_BOOT_AUTOCONF,
.line = 1,
},
},
};
static struct platform_device pnx833x_uart_device = {
.name = "pnx8xxx-uart",
.id = -1,
.dev = {
.dma_mask = &uart_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
.platform_data = pnx8xxx_ports,
},
.num_resources = ARRAY_SIZE(pnx833x_uart_resources),
.resource = pnx833x_uart_resources,
};
static u64 ehci_dmamask = DMA_32BIT_MASK;
static struct resource pnx833x_usb_ehci_resources[] = {
[0] = {
.start = PNX833X_USB_PORTS_START,
.end = PNX833X_USB_PORTS_END,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PNX833X_PIC_USB_INT,
.end = PNX833X_PIC_USB_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pnx833x_usb_ehci_device = {
.name = "pnx833x-ehci",
.id = -1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
},
.num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),
.resource = pnx833x_usb_ehci_resources,
};
#ifdef CONFIG_I2C_PNX0105
static struct resource pnx833x_i2c0_resources[] = {
{
.start = PNX833X_I2C0_PORTS_START,
.end = PNX833X_I2C0_PORTS_END,
.flags = IORESOURCE_MEM,
},
{
.start = PNX833X_PIC_I2C0_INT,
.end = PNX833X_PIC_I2C0_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct resource pnx833x_i2c1_resources[] = {
{
.start = PNX833X_I2C1_PORTS_START,
.end = PNX833X_I2C1_PORTS_END,
.flags = IORESOURCE_MEM,
},
{
.start = PNX833X_PIC_I2C1_INT,
.end = PNX833X_PIC_I2C1_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = {
{
.base = PNX833X_I2C0_PORTS_START,
.irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */
.clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */
.bus_addr = 0, /* no slave support */
},
{
.base = PNX833X_I2C1_PORTS_START,
.irq = -1, /* on high freq, polling is faster */
/*.irq = PNX833X_PIC_I2C1_INT,*/
.clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */
.bus_addr = 0, /* no slave support */
},
};
static struct platform_device pnx833x_i2c0_device = {
.name = "i2c-pnx0105",
.id = 0,
.dev = {
.platform_data = &pnx833x_i2c_dev[0],
},
.num_resources = ARRAY_SIZE(pnx833x_i2c0_resources),
.resource = pnx833x_i2c0_resources,
};
static struct platform_device pnx833x_i2c1_device = {
.name = "i2c-pnx0105",
.id = 1,
.dev = {
.platform_data = &pnx833x_i2c_dev[1],
},
.num_resources = ARRAY_SIZE(pnx833x_i2c1_resources),
.resource = pnx833x_i2c1_resources,
};
#endif
static u64 ethernet_dmamask = DMA_32BIT_MASK;
static struct resource pnx833x_ethernet_resources[] = {
[0] = {
.start = PNX8335_IP3902_PORTS_START,
.end = PNX8335_IP3902_PORTS_END,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PNX8335_PIC_ETHERNET_INT,
.end = PNX8335_PIC_ETHERNET_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pnx833x_ethernet_device = {
.name = "ip3902-eth",
.id = -1,
.dev = {
.dma_mask = &ethernet_dmamask,
.coherent_dma_mask = DMA_32BIT_MASK,
},
.num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
.resource = pnx833x_ethernet_resources,
};
static struct resource pnx833x_sata_resources[] = {
[0] = {
.start = PNX8335_SATA_PORTS_START,
.end = PNX8335_SATA_PORTS_END,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PNX8335_PIC_SATA_INT,
.end = PNX8335_PIC_SATA_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pnx833x_sata_device = {
.name = "pnx833x-sata",
.id = -1,
.num_resources = ARRAY_SIZE(pnx833x_sata_resources),
.resource = pnx833x_sata_resources,
};
static const char *part_probes[] = {
"cmdlinepart",
NULL
};
static void
pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));
else
writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));
}
static struct platform_nand_data pnx833x_flash_nand_data = {
.chip = {
.chip_delay = 25,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = pnx833x_flash_nand_cmd_ctrl
}
};
/*
* Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),
* 12 bytes more seems to be the standard that allows for NAND access.
*/
static struct resource pnx833x_flash_nand_resource = {
.start = PNX8335_NAND_BASE,
.end = PNX8335_NAND_BASE + 12,
.flags = IORESOURCE_MEM,
};
static struct platform_device pnx833x_flash_nand = {
.name = "gen_nand",
.id = -1,
.num_resources = 1,
.resource = &pnx833x_flash_nand_resource,
.dev = {
.platform_data = &pnx833x_flash_nand_data,
},
};
static struct platform_device *pnx833x_platform_devices[] __initdata = {
&pnx833x_uart_device,
&pnx833x_usb_ehci_device,
#ifdef CONFIG_I2C_PNX0105
&pnx833x_i2c0_device,
&pnx833x_i2c1_device,
#endif
&pnx833x_ethernet_device,
&pnx833x_sata_device,
&pnx833x_flash_nand,
};
static int __init pnx833x_platform_init(void)
{
int res;
res = platform_add_devices(pnx833x_platform_devices,
ARRAY_SIZE(pnx833x_platform_devices));
return res;
}
arch_initcall(pnx833x_platform_init);

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/*
* prom.c:
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* Based on software written by:
* Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <asm/bootinfo.h>
#include <linux/string.h>
void __init prom_init_cmdline(void)
{
int argc = fw_arg0;
char **argv = (char **)fw_arg1;
char *c = &(arcs_cmdline[0]);
int i;
for (i = 1; i < argc; i++) {
strcpy(c, argv[i]);
c += strlen(argv[i]);
if (i < argc-1)
*c++ = ' ';
}
*c = 0;
}
char __init *prom_getenv(char *envname)
{
extern char **prom_envp;
char **env = prom_envp;
int i;
i = strlen(envname);
while (*env) {
if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
return *env + i + 1;
env++;
}
return 0;
}
void __init prom_free_prom_memory(void)
{
}
char * __init prom_getcmdline(void)
{
return arcs_cmdline;
}

45
arch/mips/nxp/pnx833x/common/reset.c Normal file
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/*
* reset.c: reset support for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* Based on software written by:
* Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/slab.h>
#include <linux/reboot.h>
#include <pnx833x.h>
void pnx833x_machine_restart(char *command)
{
PNX833X_RESET_CONTROL_2 = 0;
PNX833X_RESET_CONTROL = 0;
}
void pnx833x_machine_halt(void)
{
while (1)
__asm__ __volatile__ ("wait");
}
void pnx833x_machine_power_off(void)
{
pnx833x_machine_halt();
}

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arch/mips/nxp/pnx833x/common/setup.c Normal file
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/*
* setup.c: Setup PNX833X Soc.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* Based on software written by:
* Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <asm/reboot.h>
#include <pnx833x.h>
#include <gpio.h>
extern void pnx833x_board_setup(void);
extern void pnx833x_machine_restart(char *);
extern void pnx833x_machine_halt(void);
extern void pnx833x_machine_power_off(void);
int __init plat_mem_setup(void)
{
/* fake pci bus to avoid bounce buffers */
PCI_DMA_BUS_IS_PHYS = 1;
/* set mips clock to 320MHz */
#if defined(CONFIG_SOC_PNX8335)
PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ);
#endif
pnx833x_gpio_init(); /* so it will be ready in board_setup() */
pnx833x_board_setup();
_machine_restart = pnx833x_machine_restart;
_machine_halt = pnx833x_machine_halt;
pm_power_off = pnx833x_machine_power_off;
/* IO/MEM resources. */
set_io_port_base(KSEG1);
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;
iomem_resource.end = ~0;
return 0;
}

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arch/mips/nxp/pnx833x/stb22x/Makefile Normal file
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lib-y := board.o
EXTRA_CFLAGS += -Werror

133
arch/mips/nxp/pnx833x/stb22x/board.c Normal file
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/*
* board.c: STB225 board support.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
*
* Based on software written by:
* Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <asm/bootinfo.h>
#include <linux/mm.h>
#include <pnx833x.h>
#include <gpio.h>
/* endianess twiddlers */
#define PNX8335_DEBUG0 0x4400
#define PNX8335_DEBUG1 0x4404
#define PNX8335_DEBUG2 0x4408
#define PNX8335_DEBUG3 0x440c
#define PNX8335_DEBUG4 0x4410
#define PNX8335_DEBUG5 0x4414
#define PNX8335_DEBUG6 0x4418
#define PNX8335_DEBUG7 0x441c
int prom_argc;
char **prom_argv = 0, **prom_envp = 0;
extern void prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
const char *get_system_type(void)
{
return "NXP STB22x";
}
static inline unsigned long env_or_default(char *env, unsigned long dfl)
{
char *str = prom_getenv(env);
return str ? simple_strtol(str, 0, 0) : dfl;
}
void __init prom_init(void)
{
unsigned long memsize;
prom_argc = fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
prom_init_cmdline();
memsize = env_or_default("memsize", 0x02000000);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void __init pnx833x_board_setup(void)
{
pnx833x_gpio_select_function_alt(4);
pnx833x_gpio_select_output(4);
pnx833x_gpio_select_function_alt(5);
pnx833x_gpio_select_input(5);
pnx833x_gpio_select_function_alt(6);
pnx833x_gpio_select_input(6);
pnx833x_gpio_select_function_alt(7);
pnx833x_gpio_select_output(7);
pnx833x_gpio_select_function_alt(25);
pnx833x_gpio_select_function_alt(26);
pnx833x_gpio_select_function_alt(27);
pnx833x_gpio_select_function_alt(28);
pnx833x_gpio_select_function_alt(29);
pnx833x_gpio_select_function_alt(30);
pnx833x_gpio_select_function_alt(31);
pnx833x_gpio_select_function_alt(32);
pnx833x_gpio_select_function_alt(33);
#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
/* Setup MIU for NAND access on CS0...
*
* (it seems that we must also configure CS1 for reliable operation,
* otherwise the first read ID command will fail if it's read as 4 bytes
* but pass if it's read as 1 word.)
*/
/* Setup MIU CS0 & CS1 timing */
PNX833X_MIU_SEL0 = 0;
PNX833X_MIU_SEL1 = 0;
PNX833X_MIU_SEL0_TIMING = 0x50003081;
PNX833X_MIU_SEL1_TIMING = 0x50003081;
/* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
pnx833x_gpio_select_function_alt(0);
/* Setup GPIO 04 to input NAND read/busy signal */
pnx833x_gpio_select_function_io(4);
pnx833x_gpio_select_input(4);
/* Setup GPIO 05 to disable NAND write protect */
pnx833x_gpio_select_function_io(5);
pnx833x_gpio_select_output(5);
pnx833x_gpio_write(1, 5);
#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE)
/* Set up MIU for 16-bit NOR access on CS0 and CS1... */
/* Setup MIU CS0 & CS1 timing */
PNX833X_MIU_SEL0 = 1;
PNX833X_MIU_SEL1 = 1;
PNX833X_MIU_SEL0_TIMING = 0x6A08D082;
PNX833X_MIU_SEL1_TIMING = 0x6A08D082;
/* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */
pnx833x_gpio_select_function_alt(0);
#endif
}

2
arch/mips/pci/Makefile
View File

@ -13,7 +13,7 @@ obj-$(CONFIG_MIPS_MSC) += ops-msc.o
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o

2
arch/mips/pci/fixup-emma2rh.c
View File

@ -30,7 +30,7 @@
#include <asm/bootinfo.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
#define EMMA2RH_PCI_HOST_SLOT 0x09
#define EMMA2RH_USB_SLOT 0x03

1
arch/mips/pci/fixup-rc32434.c
View File

@ -30,6 +30,7 @@
#include <linux/init.h>
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/irq.h>
static int __devinitdata irq_map[2][12] = {
{0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},

2
arch/mips/pci/ops-emma2rh.c
View File

@ -30,7 +30,7 @@
#include <asm/addrspace.h>
#include <asm/debug.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
#define RTABORT (0x1<<9)
#define RMABORT (0x1<<10)

2
arch/mips/pci/pci-emma2rh.c
View File

@ -30,7 +30,7 @@
#include <asm/bootinfo.h>
#include <asm/emma2rh/emma2rh.h>
#include <asm/emma/emma2rh.h>
static struct resource pci_io_resource = {
.name = "pci IO space",

2
arch/mips/rb532/devices.c
View File

@ -280,7 +280,7 @@ static int __init plat_setup_devices(void)
{
/* Look for the CF card reader */
if (!readl(IDT434_REG_BASE + DEV1MASK))
rb532_devs[1] = NULL;
rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
else {
cf_slot0_res[0].start =
readl(IDT434_REG_BASE + DEV1BASE);

4
arch/mips/rb532/gpio.c
View File

@ -310,6 +310,10 @@ int __init rb532_gpio_init(void)
return -ENXIO;
}
/* Set the interrupt status and level for the CF pin */
rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1);
rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0);
return 0;
}
arch_initcall(rb532_gpio_init);

17
arch/mips/sgi-ip22/ip22-int.c
View File

@ -12,20 +12,11 @@
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/irq_cpu.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
#include <asm/time.h>
/* #define DEBUG_SGINT */
/* So far nothing hangs here */
#undef USE_LIO3_IRQ
@ -68,7 +59,7 @@ static void enable_local1_irq(unsigned int irq)
sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
}
void disable_local1_irq(unsigned int irq)
static void disable_local1_irq(unsigned int irq)
{
sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
}
@ -87,7 +78,7 @@ static void enable_local2_irq(unsigned int irq)
sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
}
void disable_local2_irq(unsigned int irq)
static void disable_local2_irq(unsigned int irq)
{
sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
if (!sgint->cmeimask0)
@ -108,7 +99,7 @@ static void enable_local3_irq(unsigned int irq)
sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
}
void disable_local3_irq(unsigned int irq)
static void disable_local3_irq(unsigned int irq)
{
sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
if (!sgint->cmeimask1)
@ -344,6 +335,6 @@ void __init arch_init_irq(void)
#ifdef CONFIG_EISA
if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
ip22_eisa_init();
ip22_eisa_init();
#endif
}

6
arch/mips/txx9/Kconfig
View File

@ -46,9 +46,10 @@ config TOSHIBA_RBTX4938
support this machine type
config TOSHIBA_RBTX4939
bool "Toshiba RBTX4939 bobard"
bool "Toshiba RBTX4939 board"
depends on MACH_TX49XX
select SOC_TX4939
select TXX9_7SEGLED
help
This Toshiba board is based on the TX4939 processor. Say Y here to
support this machine type
@ -86,6 +87,9 @@ config SOC_TX4939
select HW_HAS_PCI
select PCI_TX4927
config TXX9_7SEGLED
bool
config TOSHIBA_FPCIB0
bool "FPCIB0 Backplane Support"
depends on PCI && MACH_TXX9

112
arch/mips/txx9/generic/7segled.c Normal file
View File

@ -0,0 +1,112 @@
/*
* 7 Segment LED routines
* Based on RBTX49xx patch from CELF patch archive.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) Copyright TOSHIBA CORPORATION 2005-2007
* All Rights Reserved.
*/
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/map_to_7segment.h>
#include <asm/txx9/generic.h>
static unsigned int tx_7segled_num;
static void (*tx_7segled_putc)(unsigned int pos, unsigned char val);
void __init txx9_7segled_init(unsigned int num,
void (*putc)(unsigned int pos, unsigned char val))
{
tx_7segled_num = num;
tx_7segled_putc = putc;
}
static SEG7_CONVERSION_MAP(txx9_seg7map, MAP_ASCII7SEG_ALPHANUM_LC);
int txx9_7segled_putc(unsigned int pos, char c)
{
if (pos >= tx_7segled_num)
return -EINVAL;
c = map_to_seg7(&txx9_seg7map, c);
if (c < 0)
return c;
tx_7segled_putc(pos, c);
return 0;
}
static ssize_t ascii_store(struct sys_device *dev,
struct sysdev_attribute *attr,
const char *buf, size_t size)
{
unsigned int ch = dev->id;
txx9_7segled_putc(ch, buf[0]);
return size;
}
static ssize_t raw_store(struct sys_device *dev,
struct sysdev_attribute *attr,
const char *buf, size_t size)
{
unsigned int ch = dev->id;
tx_7segled_putc(ch, buf[0]);
return size;
}
static SYSDEV_ATTR(ascii, 0200, NULL, ascii_store);
static SYSDEV_ATTR(raw, 0200, NULL, raw_store);
static ssize_t map_seg7_show(struct sysdev_class *class, char *buf)
{
memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map));
return sizeof(txx9_seg7map);
}
static ssize_t map_seg7_store(struct sysdev_class *class,
const char *buf, size_t size)
{
if (size != sizeof(txx9_seg7map))
return -EINVAL;
memcpy(&txx9_seg7map, buf, size);
return size;
}
static SYSDEV_CLASS_ATTR(map_seg7, 0600, map_seg7_show, map_seg7_store);
static struct sysdev_class tx_7segled_sysdev_class = {
.name = "7segled",
};
static int __init tx_7segled_init_sysfs(void)
{
int error, i;
if (!tx_7segled_num)
return -ENODEV;
error = sysdev_class_register(&tx_7segled_sysdev_class);
if (error)
return error;
error = sysdev_class_create_file(&tx_7segled_sysdev_class,
&attr_map_seg7);
if (error)
return error;
for (i = 0; i < tx_7segled_num; i++) {
struct sys_device *dev;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
error = -ENODEV;
break;
}
dev->id = i;
dev->cls = &tx_7segled_sysdev_class;
error = sysdev_register(dev);
if (!error) {
sysdev_create_file(dev, &attr_ascii);
sysdev_create_file(dev, &attr_raw);
}
}
return error;
}
device_initcall(tx_7segled_init_sysfs);

1
arch/mips/txx9/generic/Makefile
View File

@ -10,5 +10,6 @@ obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
obj-$(CONFIG_SPI) += spi_eeprom.o
obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
EXTRA_CFLAGS += -Werror

37
arch/mips/txx9/generic/setup.c
View File

@ -156,11 +156,23 @@ static struct txx9_board_vec *__init find_board_byname(const char *name)
static void __init prom_init_cmdline(void)
{
int argc = (int)fw_arg0;
int *argv32 = (int *)fw_arg1;
int argc;
int *argv32;
int i; /* Always ignore the "-c" at argv[0] */
char builtin[CL_SIZE];
if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
/*
* argc is not a valid number, or argv32 is not a valid
* pointer
*/
argc = 0;
argv32 = NULL;
} else {
argc = (int)fw_arg0;
argv32 = (int *)fw_arg1;
}
/* ignore all built-in args if any f/w args given */
/*
* But if built-in strings was started with '+', append them
@ -414,10 +426,12 @@ char * __init prom_getcmdline(void)
const char *__init prom_getenv(const char *name)
{
const s32 *str = (const s32 *)fw_arg2;
const s32 *str;
if (!str)
if (fw_arg2 < CKSEG0)
return NULL;
str = (const s32 *)fw_arg2;
/* YAMON style ("name", "value" pairs) */
while (str[0] && str[1]) {
if (!strcmp((const char *)(unsigned long)str[0], name))
@ -622,6 +636,21 @@ unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
EXPORT_SYMBOL(__swizzle_addr_b);
#endif
#ifdef NEEDS_TXX9_IOSWABW
static u16 ioswabw_default(volatile u16 *a, u16 x)
{
return le16_to_cpu(x);
}
static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
{
return x;
}
u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
EXPORT_SYMBOL(ioswabw);
u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
EXPORT_SYMBOL(__mem_ioswabw);
#endif
void __init txx9_physmap_flash_init(int no, unsigned long addr,
unsigned long size,
const struct physmap_flash_data *pdata)

74
arch/mips/txx9/rbtx4939/setup.c
View File

@ -14,6 +14,8 @@
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/interrupt.h>
#include <linux/smc91x.h>
#include <asm/reboot.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
@ -33,6 +35,21 @@ static void __init rbtx4939_time_init(void)
tx4939_time_init(0);
}
#if defined(__BIG_ENDIAN) && \
(defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE))
#define HAVE_RBTX4939_IOSWAB
#define IS_CE1_ADDR(addr) \
((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
{
return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
}
static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
{
return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
}
#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
static void __init rbtx4939_pci_setup(void)
{
#ifdef CONFIG_PCI
@ -239,6 +256,32 @@ static inline void rbtx4939_led_setup(void)
}
#endif
static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
{
#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
unsigned long flags;
local_irq_save(flags);
/* bit7: reserved for LED class */
led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
val = led_val[pos];
local_irq_restore(flags);
#endif
writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
}
static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
{
/* convert from map_to_seg7() notation */
val = (val & 0x88) |
((val & 0x40) >> 6) |
((val & 0x20) >> 4) |
((val & 0x10) >> 2) |
((val & 0x04) << 2) |
((val & 0x02) << 4) |
((val & 0x01) << 6);
__rbtx4939_7segled_putc(pos, val);
}
static void __init rbtx4939_arch_init(void)
{
rbtx4939_pci_setup();
@ -246,6 +289,22 @@ static void __init rbtx4939_arch_init(void)
static void __init rbtx4939_device_init(void)
{
unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
struct resource smc_res[] = {
{
.start = smc_addr,
.end = smc_addr + 0x10 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = RBTX4939_IRQ_ETHER,
/* override default irq flag defined in smc91x.h */
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
struct smc91x_platdata smc_pdata = {
.flags = SMC91X_USE_16BIT,
};
struct platform_device *pdev;
#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
int i, j;
unsigned char ethaddr[2][6];
@ -262,6 +321,12 @@ static void __init rbtx4939_device_init(void)
}
tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
#endif
pdev = platform_device_alloc("smc91x", -1);
if (!pdev ||
platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
platform_device_add(pdev))
platform_device_put(pdev);
rbtx4939_led_setup();
tx4939_wdt_init();
tx4939_ata_init();
@ -269,6 +334,8 @@ static void __init rbtx4939_device_init(void)
static void __init rbtx4939_setup(void)
{
int i;
rbtx4939_ebusc_setup();
/* always enable ATA0 */
txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
@ -276,9 +343,16 @@ static void __init rbtx4939_setup(void)
if (txx9_master_clock == 0)
txx9_master_clock = 20000000;
tx4939_setup();
#ifdef HAVE_RBTX4939_IOSWAB
ioswabw = rbtx4939_ioswabw;
__mem_ioswabw = rbtx4939_mem_ioswabw;
#endif
_machine_restart = rbtx4939_machine_restart;
txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
txx9_7segled_putc(i, '-');
pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));

3
arch/powerpc/Kconfig
View File

@ -108,8 +108,7 @@ config ARCH_NO_VIRT_TO_BUS
config PPC
bool
default y
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE
select HAVE_FUNCTION_TRACER
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_IDE
select HAVE_IOREMAP_PROT

2
arch/powerpc/Makefile
View File

@ -122,7 +122,7 @@ KBUILD_CFLAGS += -mcpu=powerpc
endif
# Work around a gcc code-gen bug with -fno-omit-frame-pointer.
ifeq ($(CONFIG_FTRACE),y)
ifeq ($(CONFIG_FUNCTION_TRACER),y)
KBUILD_CFLAGS += -mno-sched-epilog
endif

2
arch/powerpc/include/asm/ftrace.h
View File

@ -1,7 +1,7 @@
#ifndef _ASM_POWERPC_FTRACE
#define _ASM_POWERPC_FTRACE
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
#define MCOUNT_ADDR ((long)(_mcount))
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */

2
arch/powerpc/kernel/Makefile
View File

@ -12,7 +12,7 @@ CFLAGS_prom_init.o += -fPIC
CFLAGS_btext.o += -fPIC
endif
ifdef CONFIG_FTRACE
ifdef CONFIG_FUNCTION_TRACER
# Do not trace early boot code
CFLAGS_REMOVE_cputable.o = -pg -mno-sched-epilog
CFLAGS_REMOVE_prom_init.o = -pg -mno-sched-epilog

2
arch/powerpc/kernel/entry_32.S
View File

@ -1158,7 +1158,7 @@ machine_check_in_rtas:
#endif /* CONFIG_PPC_RTAS */
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
#ifdef CONFIG_DYNAMIC_FTRACE
_GLOBAL(mcount)
_GLOBAL(_mcount)

2
arch/powerpc/kernel/entry_64.S
View File

@ -884,7 +884,7 @@ _GLOBAL(enter_prom)
mtlr r0
blr
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
#ifdef CONFIG_DYNAMIC_FTRACE
_GLOBAL(mcount)
_GLOBAL(_mcount)

27
arch/powerpc/kernel/ftrace.c
View File

@ -28,17 +28,17 @@ static unsigned int ftrace_nop = 0x60000000;
#endif
static unsigned int notrace ftrace_calc_offset(long ip, long addr)
static unsigned int ftrace_calc_offset(long ip, long addr)
{
return (int)(addr - ip);
}
notrace unsigned char *ftrace_nop_replace(void)
unsigned char *ftrace_nop_replace(void)
{
return (char *)&ftrace_nop;
}
notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
{
static unsigned int op;
@ -68,7 +68,7 @@ notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
# define _ASM_PTR " .long "
#endif
notrace int
int
ftrace_modify_code(unsigned long ip, unsigned char *old_code,
unsigned char *new_code)
{
@ -113,7 +113,7 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code,
return faulted;
}
notrace int ftrace_update_ftrace_func(ftrace_func_t func)
int ftrace_update_ftrace_func(ftrace_func_t func)
{
unsigned long ip = (unsigned long)(&ftrace_call);
unsigned char old[MCOUNT_INSN_SIZE], *new;
@ -126,23 +126,6 @@ notrace int ftrace_update_ftrace_func(ftrace_func_t func)
return ret;
}
notrace int ftrace_mcount_set(unsigned long *data)
{
unsigned long ip = (long)(&mcount_call);
unsigned long *addr = data;
unsigned char old[MCOUNT_INSN_SIZE], *new;
/*
* Replace the mcount stub with a pointer to the
* ip recorder function.
*/
memcpy(old, &mcount_call, MCOUNT_INSN_SIZE);
new = ftrace_call_replace(ip, *addr);
*addr = ftrace_modify_code(ip, old, new);
return 0;
}
int __init ftrace_dyn_arch_init(void *data)
{
/* This is running in kstop_machine */

2
arch/powerpc/kernel/ppc_ksyms.c
View File

@ -68,7 +68,7 @@ EXPORT_SYMBOL(single_step_exception);
EXPORT_SYMBOL(sys_sigreturn);
#endif
#ifdef CONFIG_FTRACE
#ifdef CONFIG_FUNCTION_TRACER
EXPORT_SYMBOL(_mcount);
#endif

2
arch/powerpc/platforms/powermac/Makefile
View File

@ -1,6 +1,6 @@
CFLAGS_bootx_init.o += -fPIC
ifdef CONFIG_FTRACE
ifdef CONFIG_FUNCTION_TRACER
# Do not trace early boot code
CFLAGS_REMOVE_bootx_init.o = -pg -mno-sched-epilog
endif

16
arch/s390/Kconfig
View File

@ -241,19 +241,17 @@ config PACK_STACK
Say Y if you are unsure.
config SMALL_STACK
bool "Use 4kb/8kb for kernel stack instead of 8kb/16kb"
depends on PACK_STACK && !LOCKDEP
bool "Use 8kb for kernel stack instead of 16kb"
depends on PACK_STACK && 64BIT && !LOCKDEP
help
If you say Y here and the compiler supports the -mkernel-backchain
option the kernel will use a smaller kernel stack size. For 31 bit
the reduced size is 4kb instead of 8kb and for 64 bit it is 8kb
instead of 16kb. This allows to run more thread on a system and
reduces the pressure on the memory management for higher order
page allocations.
option the kernel will use a smaller kernel stack size. The reduced
size is 8kb instead of 16kb. This allows to run more threads on a
system and reduces the pressure on the memory management for higher
order page allocations.
Say N if you are unsure.
config CHECK_STACK
bool "Detect kernel stack overflow"
help
@ -384,7 +382,7 @@ config IPL
choice
prompt "IPL method generated into head.S"
depends on IPL
default IPL_TAPE
default IPL_VM
help
Select "tape" if you want to IPL the image from a Tape.

2
arch/s390/appldata/appldata_base.c
View File

@ -424,7 +424,7 @@ out:
*/
int appldata_register_ops(struct appldata_ops *ops)
{
if ((ops->size > APPLDATA_MAX_REC_SIZE) || (ops->size < 0))
if (ops->size > APPLDATA_MAX_REC_SIZE)
return -EINVAL;
ops->ctl_table = kzalloc(4 * sizeof(struct ctl_table), GFP_KERNEL);

2
arch/s390/include/asm/kvm_virtio.h
View File

@ -52,7 +52,7 @@ struct kvm_vqconfig {
#ifdef __KERNEL__
/* early virtio console setup */
#ifdef CONFIG_VIRTIO_CONSOLE
#ifdef CONFIG_S390_GUEST
extern void s390_virtio_console_init(void);
#else
static inline void s390_virtio_console_init(void)

3
arch/s390/include/asm/mmu.h
View File

@ -7,7 +7,8 @@ typedef struct {
unsigned long asce_bits;
unsigned long asce_limit;
int noexec;
int pgstes;
int has_pgste; /* The mmu context has extended page tables */
int alloc_pgste; /* cloned contexts will have extended page tables */
} mm_context_t;
#endif

19
arch/s390/include/asm/mmu_context.h
View File

@ -20,12 +20,25 @@ static inline int init_new_context(struct task_struct *tsk,
#ifdef CONFIG_64BIT
mm->context.asce_bits |= _ASCE_TYPE_REGION3;
#endif
if (current->mm->context.pgstes) {
if (current->mm->context.alloc_pgste) {
/*
* alloc_pgste indicates, that any NEW context will be created
* with extended page tables. The old context is unchanged. The
* page table allocation and the page table operations will
* look at has_pgste to distinguish normal and extended page
* tables. The only way to create extended page tables is to
* set alloc_pgste and then create a new context (e.g. dup_mm).
* The page table allocation is called after init_new_context
* and if has_pgste is set, it will create extended page
* tables.
*/
mm->context.noexec = 0;
mm->context.pgstes = 1;
mm->context.has_pgste = 1;
mm->context.alloc_pgste = 1;
} else {
mm->context.noexec = s390_noexec;
mm->context.pgstes = 0;
mm->context.has_pgste = 0;
mm->context.alloc_pgste = 0;
}
mm->context.asce_limit = STACK_TOP_MAX;
crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));

8
arch/s390/include/asm/pgtable.h
View File

@ -679,7 +679,7 @@ static inline void pmd_clear(pmd_t *pmd)
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
if (mm->context.pgstes)
if (mm->context.has_pgste)
ptep_rcp_copy(ptep);
pte_val(*ptep) = _PAGE_TYPE_EMPTY;
if (mm->context.noexec)
@ -763,7 +763,7 @@ static inline int kvm_s390_test_and_clear_page_dirty(struct mm_struct *mm,
struct page *page;
unsigned int skey;
if (!mm->context.pgstes)
if (!mm->context.has_pgste)
return -EINVAL;
rcp_lock(ptep);
pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
@ -794,7 +794,7 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
int young;
unsigned long *pgste;
if (!vma->vm_mm->context.pgstes)
if (!vma->vm_mm->context.has_pgste)
return 0;
physpage = pte_val(*ptep) & PAGE_MASK;
pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
@ -844,7 +844,7 @@ static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
static inline void ptep_invalidate(struct mm_struct *mm,
unsigned long address, pte_t *ptep)
{
if (mm->context.pgstes) {
if (mm->context.has_pgste) {
rcp_lock(ptep);
__ptep_ipte(address, ptep);
ptep_rcp_copy(ptep);

5
arch/s390/include/asm/thread_info.h
View File

@ -15,13 +15,8 @@
* Size of kernel stack for each process
*/
#ifndef __s390x__
#ifndef __SMALL_STACK
#define THREAD_ORDER 1
#define ASYNC_ORDER 1
#else
#define THREAD_ORDER 0
#define ASYNC_ORDER 0
#endif
#else /* __s390x__ */
#ifndef __SMALL_STACK
#define THREAD_ORDER 2

24
arch/s390/kernel/smp.c
View File

@ -1119,9 +1119,7 @@ out:
return rc;
}
static ssize_t __ref rescan_store(struct sys_device *dev,
struct sysdev_attribute *attr,
const char *buf,
static ssize_t __ref rescan_store(struct sysdev_class *class, const char *buf,
size_t count)
{
int rc;
@ -1129,12 +1127,10 @@ static ssize_t __ref rescan_store(struct sys_device *dev,
rc = smp_rescan_cpus();
return rc ? rc : count;
}
static SYSDEV_ATTR(rescan, 0200, NULL, rescan_store);
static SYSDEV_CLASS_ATTR(rescan, 0200, NULL, rescan_store);
#endif /* CONFIG_HOTPLUG_CPU */
static ssize_t dispatching_show(struct sys_device *dev,
struct sysdev_attribute *attr,
char *buf)
static ssize_t dispatching_show(struct sysdev_class *class, char *buf)
{
ssize_t count;
@ -1144,9 +1140,8 @@ static ssize_t dispatching_show(struct sys_device *dev,
return count;
}
static ssize_t dispatching_store(struct sys_device *dev,
struct sysdev_attribute *attr,
const char *buf, size_t count)
static ssize_t dispatching_store(struct sysdev_class *dev, const char *buf,
size_t count)
{
int val, rc;
char delim;
@ -1168,7 +1163,8 @@ out:
put_online_cpus();
return rc ? rc : count;
}
static SYSDEV_ATTR(dispatching, 0644, dispatching_show, dispatching_store);
static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show,
dispatching_store);
static int __init topology_init(void)
{
@ -1178,13 +1174,11 @@ static int __init topology_init(void)
register_cpu_notifier(&smp_cpu_nb);
#ifdef CONFIG_HOTPLUG_CPU
rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
&attr_rescan.attr);
rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_rescan);
if (rc)
return rc;
#endif
rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
&attr_dispatching.attr);
rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_dispatching);
if (rc)
return rc;
for_each_present_cpu(cpu) {

16
arch/s390/mm/pgtable.c
View File

@ -169,7 +169,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
unsigned long *table;
unsigned long bits;
bits = (mm->context.noexec || mm->context.pgstes) ? 3UL : 1UL;
bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
spin_lock(&mm->page_table_lock);
page = NULL;
if (!list_empty(&mm->context.pgtable_list)) {
@ -186,7 +186,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
pgtable_page_ctor(page);
page->flags &= ~FRAG_MASK;
table = (unsigned long *) page_to_phys(page);
if (mm->context.pgstes)
if (mm->context.has_pgste)
clear_table_pgstes(table);
else
clear_table(table, _PAGE_TYPE_EMPTY, PAGE_SIZE);
@ -210,7 +210,7 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
struct page *page;
unsigned long bits;
bits = (mm->context.noexec || mm->context.pgstes) ? 3UL : 1UL;
bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long);
page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
spin_lock(&mm->page_table_lock);
@ -257,7 +257,7 @@ int s390_enable_sie(void)
struct mm_struct *mm, *old_mm;
/* Do we have pgstes? if yes, we are done */
if (tsk->mm->context.pgstes)
if (tsk->mm->context.has_pgste)
return 0;
/* lets check if we are allowed to replace the mm */
@ -269,14 +269,14 @@ int s390_enable_sie(void)
}
task_unlock(tsk);
/* we copy the mm with pgstes enabled */
tsk->mm->context.pgstes = 1;
/* we copy the mm and let dup_mm create the page tables with_pgstes */
tsk->mm->context.alloc_pgste = 1;
mm = dup_mm(tsk);
tsk->mm->context.pgstes = 0;
tsk->mm->context.alloc_pgste = 0;
if (!mm)
return -ENOMEM;
/* Now lets check again if somebody attached ptrace etc */
/* Now lets check again if something happened */
task_lock(tsk);
if (!tsk->mm || atomic_read(&tsk->mm->mm_users) > 1 ||
tsk->mm != tsk->active_mm || tsk->mm->ioctx_list) {

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