clk: gate: add CLK_GATE_HIWORD_MASK
In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -53,12 +53,18 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
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if (gate->lock)
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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spin_lock_irqsave(gate->lock, flags);
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if (gate->flags & CLK_GATE_HIWORD_MASK) {
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reg = BIT(gate->bit_idx + 16);
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if (set)
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reg |= BIT(gate->bit_idx);
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} else {
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reg = readl(gate->reg);
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reg = readl(gate->reg);
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if (set)
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if (set)
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reg |= BIT(gate->bit_idx);
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reg |= BIT(gate->bit_idx);
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else
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else
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reg &= ~BIT(gate->bit_idx);
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reg &= ~BIT(gate->bit_idx);
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}
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writel(reg, gate->reg);
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writel(reg, gate->reg);
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@ -121,6 +127,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
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struct clk *clk;
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struct clk *clk;
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struct clk_init_data init;
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struct clk_init_data init;
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if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
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if (bit_idx > 16) {
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pr_err("gate bit exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the gate */
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/* allocate the gate */
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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if (!gate) {
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@ -210,6 +210,10 @@ void of_fixed_clk_setup(struct device_node *np);
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* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
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* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
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* enable the clock. Setting this flag does the opposite: setting the bit
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* enable the clock. Setting this flag does the opposite: setting the bit
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* disable the clock and clearing it enables the clock
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* disable the clock and clearing it enables the clock
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* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
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* of this register, and mask of gate bits are in higher 16-bit of this
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* register. While setting the gate bits, higher 16-bit should also be
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* updated to indicate changing gate bits.
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*/
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*/
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struct clk_gate {
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struct clk_gate {
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struct clk_hw hw;
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struct clk_hw hw;
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@ -220,6 +224,7 @@ struct clk_gate {
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};
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};
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#define CLK_GATE_SET_TO_DISABLE BIT(0)
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#define CLK_GATE_SET_TO_DISABLE BIT(0)
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#define CLK_GATE_HIWORD_MASK BIT(1)
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extern const struct clk_ops clk_gate_ops;
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extern const struct clk_ops clk_gate_ops;
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struct clk *clk_register_gate(struct device *dev, const char *name,
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struct clk *clk_register_gate(struct device *dev, const char *name,
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