Merge tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This time we have a very typical update which is mostly fixes and
updates to drivers and no new drivers.
- the biggest change is coming from Peter for edma cleanup which even
caused some last minute regression, things seem settled now
- idma64 and dw updates
- iotdma updates
- module autoload fixes for various drivers
- scatter gather support for hdmac"
* tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (77 commits)
dmaengine: edma: Add dummy driver skeleton for edma3-tptc
Revert "ARM: DTS: am33xx: Use the new DT bindings for the eDMA3"
Revert "ARM: DTS: am437x: Use the new DT bindings for the eDMA3"
dmaengine: dw: some Intel devices has no memcpy support
dmaengine: dw: platform: provide platform data for Intel
dmaengine: dw: don't override platform data with autocfg
dmaengine: hdmac: Add scatter-gathered memset support
dmaengine: hdmac: factorise memset descriptor allocation
dmaengine: virt-dma: Fix kernel-doc annotations
ARM: DTS: am437x: Use the new DT bindings for the eDMA3
ARM: DTS: am33xx: Use the new DT bindings for the eDMA3
dmaengine: edma: New device tree binding
dmaengine: Kconfig: edma: Select TI_DMA_CROSSBAR in case of ARCH_OMAP
dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx
dmaengine: edma: Merge the of parsing functions
dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT boot
dmaengine: edma: Refactor the dma device and channel struct initialization
dmaengine: edma: Get qDMA channel information from HW also
dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq
dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_)
...
This commit is contained in:
Linus Torvalds
@@ -2,9 +2,10 @@ Texas Instruments DMA Crossbar (DMA request router)
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Required properties:
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- compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
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"ti,am335x-edma-crossbar" for AM335x and AM437x
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- reg: Memory map for accessing module
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- #dma-cells: Should be set to <1>.
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Clients should use the crossbar request number (input)
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- #dma-cells: Should be set to to match with the DMA controller's dma-cells
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for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
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- dma-requests: Number of DMA requests the crossbar can receive
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- dma-masters: phandle pointing to the DMA controller
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@@ -14,6 +15,15 @@ The DMA controller node need to have the following poroperties:
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Optional properties:
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- ti,dma-safe-map: Safe routing value for unused request lines
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Notes:
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When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
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the DMA event number as crossbar ID (input to the DMA crossbar).
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For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
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dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC
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the event should be assigned and <1> is the mux selection for in the crossbar.
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When mux 0 is used the DMA channel can be requested directly from edma node.
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Example:
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/* DMA controller */
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@@ -47,6 +57,7 @@ uart1: serial@4806a000 {
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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status = "disabled";
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/* Requesting crossbar input 49 and 50 */
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dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
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dma-names = "tx", "rx";
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};
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@@ -1,4 +1,119 @@
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TI EDMA
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Texas Instruments eDMA
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The eDMA3 consists of two components: Channel controller (CC) and Transfer
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Controller(s) (TC). The CC is the main entry for DMA users since it is
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responsible for the DMA channel handling, while the TCs are responsible to
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execute the actual DMA tansfer.
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------------------------------------------------------------------------------
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eDMA3 Channel Controller
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Required properties:
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- compatible: "ti,edma3-tpcc" for the channel controller(s)
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- #dma-cells: Should be set to <2>. The first number is the DMA request
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number and the second is the TC the channel is serviced on.
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- reg: Memory map of eDMA CC
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- reg-names: "edma3_cc"
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- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
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- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
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- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
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<&tptc_phandle TC_priority_number>. The highest priority is 0.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the eDMA CC
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- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
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these channels will be SW triggered channels. The list must
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contain 16 bits numbers, see example.
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- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
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the driver, they are allocated to be used by for example the
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DSP. See example.
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------------------------------------------------------------------------------
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eDMA3 Transfer Controller
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Required properties:
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- compatible: "ti,edma3-tptc" for the transfer controller(s)
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- reg: Memory map of eDMA TC
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- interrupts: Interrupt number for TCerrint.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the given eDMA TC
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- interrupt-names: "edma3_tcerrint"
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------------------------------------------------------------------------------
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Example:
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
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/* Channel 20 and 21 is allocated for memcpy */
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ti,edma-memcpy-channels = /bits/ 16 <20 21>;
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/* The following PaRAM slots are reserved: 35-45 and 100-110 */
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ti,edma-reserved-slot-ranges = /bits/ 16 <35 10>,
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/bits/ 16 <100 10>;
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <112>;
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interrupt-names = "edm3_tcerrint";
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <113>;
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interrupt-names = "edm3_tcerrint";
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <114>;
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interrupt-names = "edm3_tcerrint";
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};
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sham: sham@53100000 {
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compatible = "ti,omap4-sham";
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ti,hwmods = "sham";
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reg = <0x53100000 0x200>;
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interrupts = <109>;
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/* DMA channel 36 executed on eDMA TC0 - low priority queue */
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dmas = <&edma 36 0>;
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dma-names = "rx";
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};
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mcasp0: mcasp@48038000 {
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compatible = "ti,am33xx-mcasp-audio";
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ti,hwmods = "mcasp0";
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reg = <0x48038000 0x2000>,
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<0x46000000 0x400000>;
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reg-names = "mpu", "dat";
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interrupts = <80>, <81>;
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interrupt-names = "tx", "rx";
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status = "disabled";
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/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
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dmas = <&edma 8 2>,
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<&edma 9 2>;
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dma-names = "tx", "rx";
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};
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------------------------------------------------------------------------------
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DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
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binding.
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Required properties:
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- compatible : "ti,edma3"
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