drm/amdgpu: reverts commit ce316fa55e.
In preparation for doing XGMI reset synchronization using task barrier. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
f06a58db92
commit
041a62bc06
@@ -994,8 +994,6 @@ struct amdgpu_device {
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bool pm_sysfs_en;
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bool pm_sysfs_en;
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bool ucode_sysfs_en;
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bool ucode_sysfs_en;
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bool in_baco;
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};
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};
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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@@ -3797,18 +3797,13 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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return r;
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return r;
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}
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}
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static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
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static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
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struct amdgpu_hive_info *hive,
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struct list_head *device_list_handle,
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struct list_head *device_list_handle,
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bool *need_full_reset_arg)
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bool *need_full_reset_arg)
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{
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{
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struct amdgpu_device *tmp_adev = NULL;
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struct amdgpu_device *tmp_adev = NULL;
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bool need_full_reset = *need_full_reset_arg, vram_lost = false;
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bool need_full_reset = *need_full_reset_arg, vram_lost = false;
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int r = 0;
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int r = 0;
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int cpu = smp_processor_id();
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bool use_baco =
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(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
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true : false;
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/*
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/*
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* ASIC reset has to be done on all HGMI hive nodes ASAP
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* ASIC reset has to be done on all HGMI hive nodes ASAP
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@@ -3816,24 +3811,21 @@ static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
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*/
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*/
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if (need_full_reset) {
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if (need_full_reset) {
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
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/*
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/* For XGMI run all resets in parallel to speed up the process */
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* For XGMI run all resets in parallel to speed up the
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* process by scheduling the highpri wq on different
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* cpus. For XGMI with baco reset, all nodes must enter
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* baco within close proximity before anyone exit.
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*/
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if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
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if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
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if (!queue_work_on(cpu, system_highpri_wq,
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if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
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&tmp_adev->xgmi_reset_work))
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r = -EALREADY;
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r = -EALREADY;
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cpu = cpumask_next(cpu, cpu_online_mask);
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} else
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} else
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r = amdgpu_asic_reset(tmp_adev);
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r = amdgpu_asic_reset(tmp_adev);
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if (r)
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if (r) {
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DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
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r, tmp_adev->ddev->unique);
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break;
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break;
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}
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}
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}
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/* For XGMI wait for all work to complete before proceed */
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/* For XGMI wait for all resets to complete before proceed */
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if (!r) {
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if (!r) {
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list_for_each_entry(tmp_adev, device_list_handle,
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list_for_each_entry(tmp_adev, device_list_handle,
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gmc.xgmi.head) {
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gmc.xgmi.head) {
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@@ -3842,53 +3834,9 @@ static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
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r = tmp_adev->asic_reset_res;
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r = tmp_adev->asic_reset_res;
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if (r)
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if (r)
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break;
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break;
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if (use_baco)
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tmp_adev->in_baco = true;
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}
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}
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}
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}
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}
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}
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/*
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* For XGMI with baco reset, need exit baco phase by scheduling
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* xgmi_reset_work one more time. PSP reset and sGPU skips this
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* phase. Not assume the situation that PSP reset and baco reset
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* coexist within an XGMI hive.
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*/
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if (!r && use_baco) {
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cpu = smp_processor_id();
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list_for_each_entry(tmp_adev, device_list_handle,
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gmc.xgmi.head) {
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if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
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if (!queue_work_on(cpu,
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system_highpri_wq,
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&tmp_adev->xgmi_reset_work))
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r = -EALREADY;
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if (r)
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break;
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cpu = cpumask_next(cpu, cpu_online_mask);
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}
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}
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}
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if (!r && use_baco) {
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list_for_each_entry(tmp_adev, device_list_handle,
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gmc.xgmi.head) {
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if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
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flush_work(&tmp_adev->xgmi_reset_work);
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r = tmp_adev->asic_reset_res;
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if (r)
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break;
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tmp_adev->in_baco = false;
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}
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}
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}
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if (r) {
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DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
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r, tmp_adev->ddev->unique);
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goto end;
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}
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}
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}
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if (!r && amdgpu_ras_intr_triggered())
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if (!r && amdgpu_ras_intr_triggered())
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@@ -4182,8 +4130,7 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */
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if (r)
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if (r)
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adev->asic_reset_res = r;
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adev->asic_reset_res = r;
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} else {
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} else {
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r = amdgpu_do_asic_reset(adev, hive, device_list_handle,
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r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
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&need_full_reset);
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if (r && r == -EAGAIN)
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if (r && r == -EAGAIN)
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goto retry;
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goto retry;
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}
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}
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