forked from Minki/linux
MIPS: Fix a preemption issue with thread's FPU defaults
Fix "BUG: using smp_processor_id() in preemptible" reported in accesses to thread's FPU defaults: the value to initialise FSCR to at program startup, the FCSR r/w mask and the contents of FIR in full FPU emulation, removing a regression introduced with9b26616c
[MIPS: Respect the ISA level in FCSR handling] andf6843626
[MIPS: math-emu: Set FIR feature flags for full emulation]. Use `boot_cpu_data' to obtain the data from, following the approach that `cpu_has_*' macros take and avoiding the call to `smp_processor_id' made in the reference to `current_cpu_data'. The contents of FSCR have to be consistent across processors in an SMP system, the settings there must not change as a thread is migrated across processors. And the contents of FIR are guaranteed to be consistent in FPU emulation, by definition. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Tested-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Tested-by: Paul Martin <paul.martin@codethink.co.uk> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10030/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -304,7 +304,7 @@ do { \
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\
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current->thread.abi = &mips_abi; \
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\
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current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31; \
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current->thread.fpu.fcr31 = boot_cpu_data.fpu_csr31; \
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} while (0)
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#endif /* CONFIG_32BIT */
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@ -366,7 +366,7 @@ do { \
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else \
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current->thread.abi = &mips_abi; \
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\
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current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31; \
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current->thread.fpu.fcr31 = boot_cpu_data.fpu_csr31; \
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\
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p = personality(current->personality); \
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if (p != PER_LINUX32 && p != PER_LINUX) \
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@ -176,7 +176,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
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__get_user(value, data + 64);
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fcr31 = child->thread.fpu.fcr31;
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mask = current_cpu_data.fpu_msk31;
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mask = boot_cpu_data.fpu_msk31;
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child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
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/* FIR may not be written. */
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@ -889,7 +889,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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break;
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case FPCREG_RID:
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value = current_cpu_data.fpu_id;
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value = boot_cpu_data.fpu_id;
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break;
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default:
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@ -921,7 +921,7 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
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/* Preserve read-only bits. */
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mask = current_cpu_data.fpu_msk31;
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mask = boot_cpu_data.fpu_msk31;
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fcr31 = (value & ~mask) | (fcr31 & mask);
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break;
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