Merge branch 'davem-next' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
This commit is contained in:
David S. Miller
commit
030352a9c7
@ -524,6 +524,18 @@ config STNIC
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If unsure, say N.
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config SH_ETH
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tristate "Renesas SuperH Ethernet support"
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depends on SUPERH && \
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(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712)
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select CRC32
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select MII
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select MDIO_BITBANG
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select PHYLIB
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help
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Renesas SuperH Ethernet device driver.
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This driver support SH7710 and SH7712.
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config SUNLANCE
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tristate "Sun LANCE support"
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depends on SBUS
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@ -955,7 +967,7 @@ config SMC911X
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tristate "SMSC LAN911[5678] support"
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select CRC32
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select MII
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depends on ARCH_PXA || SH_MAGIC_PANEL_R2
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depends on ARCH_PXA || SUPERH
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help
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This is a driver for SMSC's LAN911x series of Ethernet chipsets
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including the new LAN9115, LAN9116, LAN9117, and LAN9118.
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@ -80,6 +80,7 @@ obj-$(CONFIG_VIA_RHINE) += via-rhine.o
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obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
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obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
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obj-$(CONFIG_RIONET) += rionet.o
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obj-$(CONFIG_SH_ETH) += sh_eth.o
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#
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# end link order section
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@ -236,6 +237,7 @@ obj-$(CONFIG_USB_CATC) += usb/
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obj-$(CONFIG_USB_KAWETH) += usb/
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obj-$(CONFIG_USB_PEGASUS) += usb/
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obj-$(CONFIG_USB_RTL8150) += usb/
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obj-$(CONFIG_USB_HSO) += usb/
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obj-$(CONFIG_USB_USBNET) += usb/
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obj-$(CONFIG_USB_ZD1201) += usb/
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@ -475,16 +475,12 @@ static irqreturn_t lance_interrupt (int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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struct net_device *last_dev;
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static int lance_open (struct net_device *dev)
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{
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struct lance_private *lp = netdev_priv(dev);
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volatile struct lance_regs *ll = lp->ll;
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int ret;
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last_dev = dev;
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/* Stop the Lance */
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ll->rap = LE_CSR0;
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ll->rdp = LE_C0_STOP;
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@ -243,7 +243,7 @@ struct lance_private {
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/* Possible memory/IO addresses for probing */
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struct lance_addr {
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static struct lance_addr {
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unsigned long memaddr;
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unsigned long ioaddr;
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int slow_flag;
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@ -773,8 +773,6 @@ static irqreturn_t lance_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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struct net_device *last_dev = 0;
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static int lance_open(struct net_device *dev)
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{
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volatile u16 *ib = (volatile u16 *)dev->mem_start;
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@ -782,8 +780,6 @@ static int lance_open(struct net_device *dev)
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volatile struct lance_regs *ll = lp->ll;
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int status = 0;
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last_dev = dev;
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/* Stop the Lance */
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writereg(&ll->rap, LE_CSR0);
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writereg(&ll->rdp, LE_C0_STOP);
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@ -4343,6 +4343,11 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
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netdev->features |= NETIF_F_TSO;
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netdev->features |= NETIF_F_TSO6;
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netdev->vlan_features |= NETIF_F_TSO;
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netdev->vlan_features |= NETIF_F_TSO6;
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netdev->vlan_features |= NETIF_F_HW_CSUM;
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netdev->vlan_features |= NETIF_F_SG;
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if (pci_using_dac)
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netdev->features |= NETIF_F_HIGHDMA;
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@ -220,12 +220,12 @@ static int hplance_close(struct net_device *dev)
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return 0;
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}
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int __init hplance_init_module(void)
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static int __init hplance_init_module(void)
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{
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return dio_register_driver(&hplance_driver);
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}
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void __exit hplance_cleanup_module(void)
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static void __exit hplance_cleanup_module(void)
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{
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dio_unregister_driver(&hplance_driver);
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}
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@ -967,8 +967,13 @@ static int __devinit igb_probe(struct pci_dev *pdev,
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NETIF_F_HW_VLAN_FILTER;
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netdev->features |= NETIF_F_TSO;
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netdev->features |= NETIF_F_TSO6;
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netdev->vlan_features |= NETIF_F_TSO;
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netdev->vlan_features |= NETIF_F_TSO6;
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netdev->vlan_features |= NETIF_F_HW_CSUM;
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netdev->vlan_features |= NETIF_F_SG;
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if (pci_using_dac)
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netdev->features |= NETIF_F_HIGHDMA;
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@ -3518,8 +3518,13 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
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NETIF_F_HW_VLAN_FILTER;
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netdev->features |= NETIF_F_TSO;
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netdev->features |= NETIF_F_TSO6;
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netdev->vlan_features |= NETIF_F_TSO;
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netdev->vlan_features |= NETIF_F_TSO6;
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netdev->vlan_features |= NETIF_F_HW_CSUM;
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netdev->vlan_features |= NETIF_F_SG;
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if (pci_using_dac)
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netdev->features |= NETIF_F_HIGHDMA;
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@ -553,6 +553,8 @@ static void __ei_poll(struct net_device *dev)
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static void ei_tx_err(struct net_device *dev)
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{
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unsigned long e8390_base = dev->base_addr;
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/* ei_local is used on some platforms via the EI_SHIFT macro */
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struct ei_device *ei_local __maybe_unused = netdev_priv(dev);
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unsigned char txsr = ei_inb_p(e8390_base+EN0_TSR);
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unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU);
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@ -815,6 +817,8 @@ static void ei_rx_overrun(struct net_device *dev)
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{
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unsigned long e8390_base = dev->base_addr;
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unsigned char was_txing, must_resend = 0;
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/* ei_local is used on some platforms via the EI_SHIFT macro */
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struct ei_device *ei_local __maybe_unused = netdev_priv(dev);
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/*
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* Record whether a Tx was in progress and then issue the
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@ -117,8 +117,6 @@ enum mac8390_access {
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ACCESS_16,
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};
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extern enum mac8390_type mac8390_ident(struct nubus_dev * dev);
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extern int mac8390_memsize(unsigned long membase);
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extern int mac8390_memtest(struct net_device * dev);
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static int mac8390_initdev(struct net_device * dev, struct nubus_dev * ndev,
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enum mac8390_type type);
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@ -163,7 +161,7 @@ static void slow_sane_block_output(struct net_device *dev, int count,
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static void word_memcpy_tocard(void *tp, const void *fp, int count);
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static void word_memcpy_fromcard(void *tp, const void *fp, int count);
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enum mac8390_type __init mac8390_ident(struct nubus_dev * dev)
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static enum mac8390_type __init mac8390_ident(struct nubus_dev *dev)
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{
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switch (dev->dr_sw) {
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case NUBUS_DRSW_3COM:
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@ -234,7 +232,7 @@ enum mac8390_type __init mac8390_ident(struct nubus_dev * dev)
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return MAC8390_NONE;
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}
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enum mac8390_access __init mac8390_testio(volatile unsigned long membase)
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static enum mac8390_access __init mac8390_testio(volatile unsigned long membase)
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{
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unsigned long outdata = 0xA5A0B5B0;
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unsigned long indata = 0x00000000;
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@ -252,7 +250,7 @@ enum mac8390_access __init mac8390_testio(volatile unsigned long membase)
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return ACCESS_UNKNOWN;
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}
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int __init mac8390_memsize(unsigned long membase)
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static int __init mac8390_memsize(unsigned long membase)
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{
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unsigned long flags;
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int i, j;
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@ -80,8 +80,12 @@ static void __init macb_get_hwaddr(struct macb *bp)
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addr[4] = top & 0xff;
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addr[5] = (top >> 8) & 0xff;
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if (is_valid_ether_addr(addr))
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if (is_valid_ether_addr(addr)) {
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memcpy(bp->dev->dev_addr, addr, sizeof(addr));
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} else {
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dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
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random_ether_addr(bp->dev->dev_addr);
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}
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}
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static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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@ -83,9 +83,6 @@ static unsigned int sonic_debug = 1;
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static int sonic_version_printed;
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extern int mac_onboard_sonic_probe(struct net_device* dev);
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extern int mac_nubus_sonic_probe(struct net_device* dev);
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/* For onboard SONIC */
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#define ONBOARD_SONIC_REGISTERS 0x50F0A000
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#define ONBOARD_SONIC_PROM_BASE 0x50f08000
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@ -170,7 +167,7 @@ static int macsonic_close(struct net_device* dev)
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return err;
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}
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int __init macsonic_init(struct net_device* dev)
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static int __init macsonic_init(struct net_device *dev)
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{
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struct sonic_local* lp = netdev_priv(dev);
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@ -218,7 +215,7 @@ int __init macsonic_init(struct net_device* dev)
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return 0;
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}
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int __init mac_onboard_sonic_ethernet_addr(struct net_device* dev)
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static int __init mac_onboard_sonic_ethernet_addr(struct net_device *dev)
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{
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struct sonic_local *lp = netdev_priv(dev);
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const int prom_addr = ONBOARD_SONIC_PROM_BASE;
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@ -284,7 +281,7 @@ int __init mac_onboard_sonic_ethernet_addr(struct net_device* dev)
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} else return 0;
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}
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int __init mac_onboard_sonic_probe(struct net_device* dev)
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static int __init mac_onboard_sonic_probe(struct net_device *dev)
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{
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/* Bwahahaha */
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static int once_is_more_than_enough;
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@ -405,9 +402,9 @@ int __init mac_onboard_sonic_probe(struct net_device* dev)
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return macsonic_init(dev);
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}
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int __init mac_nubus_sonic_ethernet_addr(struct net_device* dev,
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unsigned long prom_addr,
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int id)
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static int __init mac_nubus_sonic_ethernet_addr(struct net_device *dev,
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unsigned long prom_addr,
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int id)
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{
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int i;
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for(i = 0; i < 6; i++)
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@ -420,7 +417,7 @@ int __init mac_nubus_sonic_ethernet_addr(struct net_device* dev,
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return 0;
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}
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int __init macsonic_ident(struct nubus_dev* ndev)
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static int __init macsonic_ident(struct nubus_dev *ndev)
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{
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if (ndev->dr_hw == NUBUS_DRHW_ASANTE_LC &&
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ndev->dr_sw == NUBUS_DRSW_SONIC_LC)
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@ -445,7 +442,7 @@ int __init macsonic_ident(struct nubus_dev* ndev)
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return -1;
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}
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int __init mac_nubus_sonic_probe(struct net_device* dev)
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static int __init mac_nubus_sonic_probe(struct net_device *dev)
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{
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static int slots;
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struct nubus_dev* ndev = NULL;
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1174
drivers/net/sh_eth.c
Normal file
1174
drivers/net/sh_eth.c
Normal file
File diff suppressed because it is too large
Load Diff
464
drivers/net/sh_eth.h
Normal file
464
drivers/net/sh_eth.h
Normal file
@ -0,0 +1,464 @@
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/*
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* SuperH Ethernet device driver
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||||
*
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||||
* Copyright (C) 2006-2008 Nobuhiro Iwamatsu
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||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
*
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||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*/
|
||||
|
||||
#ifndef __SH_ETH_H__
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#define __SH_ETH_H__
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||||
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||||
#include <linux/module.h>
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||||
#include <linux/kernel.h>
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||||
#include <linux/spinlock.h>
|
||||
#include <linux/workqueue.h>
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||||
#include <linux/netdevice.h>
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||||
#include <linux/phy.h>
|
||||
|
||||
#define CARDNAME "sh-eth"
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||||
#define TX_TIMEOUT (5*HZ)
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||||
|
||||
#define TX_RING_SIZE 128 /* Tx ring size */
|
||||
#define RX_RING_SIZE 128 /* Rx ring size */
|
||||
#define RX_OFFSET 2 /* skb offset */
|
||||
#define ETHERSMALL 60
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||||
#define PKT_BUF_SZ 1538
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||||
|
||||
/* Chip Base Address */
|
||||
#define SH_ETH0_BASE 0xA7000000
|
||||
#define SH_ETH1_BASE 0xA7000400
|
||||
#define SH_TSU_ADDR 0xA7000804
|
||||
|
||||
/* Chip Registers */
|
||||
/* E-DMAC */
|
||||
#define EDMR 0x0000
|
||||
#define EDTRR 0x0004
|
||||
#define EDRRR 0x0008
|
||||
#define TDLAR 0x000C
|
||||
#define RDLAR 0x0010
|
||||
#define EESR 0x0014
|
||||
#define EESIPR 0x0018
|
||||
#define TRSCER 0x001C
|
||||
#define RMFCR 0x0020
|
||||
#define TFTR 0x0024
|
||||
#define FDR 0x0028
|
||||
#define RMCR 0x002C
|
||||
#define EDOCR 0x0030
|
||||
#define FCFTR 0x0034
|
||||
#define RPADIR 0x0038
|
||||
#define TRIMD 0x003C
|
||||
#define RBWAR 0x0040
|
||||
#define RDFAR 0x0044
|
||||
#define TBRAR 0x004C
|
||||
#define TDFAR 0x0050
|
||||
/* Ether Register */
|
||||
#define ECMR 0x0160
|
||||
#define ECSR 0x0164
|
||||
#define ECSIPR 0x0168
|
||||
#define PIR 0x016C
|
||||
#define MAHR 0x0170
|
||||
#define MALR 0x0174
|
||||
#define RFLR 0x0178
|
||||
#define PSR 0x017C
|
||||
#define TROCR 0x0180
|
||||
#define CDCR 0x0184
|
||||
#define LCCR 0x0188
|
||||
#define CNDCR 0x018C
|
||||
#define CEFCR 0x0194
|
||||
#define FRECR 0x0198
|
||||
#define TSFRCR 0x019C
|
||||
#define TLFRCR 0x01A0
|
||||
#define RFCR 0x01A4
|
||||
#define MAFCR 0x01A8
|
||||
#define IPGR 0x01B4
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define APR 0x01B8
|
||||
#define MPR 0x01BC
|
||||
#define TPAUSER 0x1C4
|
||||
#define BCFR 0x1CC
|
||||
#endif /* CONFIG_CPU_SH7710 */
|
||||
|
||||
#define ARSTR 0x0800
|
||||
|
||||
/* TSU */
|
||||
#define TSU_CTRST 0x004
|
||||
#define TSU_FWEN0 0x010
|
||||
#define TSU_FWEN1 0x014
|
||||
#define TSU_FCM 0x018
|
||||
#define TSU_BSYSL0 0x020
|
||||
#define TSU_BSYSL1 0x024
|
||||
#define TSU_PRISL0 0x028
|
||||
#define TSU_PRISL1 0x02C
|
||||
#define TSU_FWSL0 0x030
|
||||
#define TSU_FWSL1 0x034
|
||||
#define TSU_FWSLC 0x038
|
||||
#define TSU_QTAGM0 0x040
|
||||
#define TSU_QTAGM1 0x044
|
||||
#define TSU_ADQT0 0x048
|
||||
#define TSU_ADQT1 0x04C
|
||||
#define TSU_FWSR 0x050
|
||||
#define TSU_FWINMK 0x054
|
||||
#define TSU_ADSBSY 0x060
|
||||
#define TSU_TEN 0x064
|
||||
#define TSU_POST1 0x070
|
||||
#define TSU_POST2 0x074
|
||||
#define TSU_POST3 0x078
|
||||
#define TSU_POST4 0x07C
|
||||
#define TXNLCR0 0x080
|
||||
#define TXALCR0 0x084
|
||||
#define RXNLCR0 0x088
|
||||
#define RXALCR0 0x08C
|
||||
#define FWNLCR0 0x090
|
||||
#define FWALCR0 0x094
|
||||
#define TXNLCR1 0x0A0
|
||||
#define TXALCR1 0x0A4
|
||||
#define RXNLCR1 0x0A8
|
||||
#define RXALCR1 0x0AC
|
||||
#define FWNLCR1 0x0B0
|
||||
#define FWALCR1 0x0B4
|
||||
|
||||
#define TSU_ADRH0 0x0100
|
||||
#define TSU_ADRL0 0x0104
|
||||
#define TSU_ADRL31 0x01FC
|
||||
|
||||
/* Register's bits */
|
||||
|
||||
/* EDMR */
|
||||
enum DMAC_M_BIT {
|
||||
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01,
|
||||
};
|
||||
|
||||
/* EDTRR */
|
||||
enum DMAC_T_BIT {
|
||||
EDTRR_TRNS = 0x01,
|
||||
};
|
||||
|
||||
/* EDRRR*/
|
||||
enum EDRRR_R_BIT {
|
||||
EDRRR_R = 0x01,
|
||||
};
|
||||
|
||||
/* TPAUSER */
|
||||
enum TPAUSER_BIT {
|
||||
TPAUSER_TPAUSE = 0x0000ffff,
|
||||
TPAUSER_UNLIMITED = 0,
|
||||
};
|
||||
|
||||
/* BCFR */
|
||||
enum BCFR_BIT {
|
||||
BCFR_RPAUSE = 0x0000ffff,
|
||||
BCFR_UNLIMITED = 0,
|
||||
};
|
||||
|
||||
/* PIR */
|
||||
enum PIR_BIT {
|
||||
PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
|
||||
};
|
||||
|
||||
/* PSR */
|
||||
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
|
||||
|
||||
/* EESR */
|
||||
enum EESR_BIT {
|
||||
EESR_TWB = 0x40000000, EESR_TABT = 0x04000000,
|
||||
EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
|
||||
EESR_ADE = 0x00800000, EESR_ECI = 0x00400000,
|
||||
EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
|
||||
EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
|
||||
EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
|
||||
EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400,
|
||||
EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100,
|
||||
EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010,
|
||||
EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004,
|
||||
EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001,
|
||||
};
|
||||
|
||||
#define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
|
||||
| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
|
||||
|
||||
/* EESIPR */
|
||||
enum DMAC_IM_BIT {
|
||||
DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
|
||||
DMAC_M_RABT = 0x02000000,
|
||||
DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
|
||||
DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
|
||||
DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
|
||||
DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
|
||||
DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
|
||||
DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
|
||||
DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
|
||||
DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
|
||||
DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
|
||||
DMAC_M_RINT1 = 0x00000001,
|
||||
};
|
||||
|
||||
/* Receive descriptor bit */
|
||||
enum RD_STS_BIT {
|
||||
RD_RACT = 0x80000000, RC_RDEL = 0x40000000,
|
||||
RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000,
|
||||
RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
|
||||
RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
|
||||
RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
|
||||
RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
|
||||
RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
|
||||
RD_RFS1 = 0x00000001,
|
||||
};
|
||||
#define RDF1ST RC_RFP1
|
||||
#define RDFEND RC_RFP0
|
||||
#define RD_RFP (RC_RFP1|RC_RFP0)
|
||||
|
||||
/* FCFTR */
|
||||
enum FCFTR_BIT {
|
||||
FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
|
||||
FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
|
||||
FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
|
||||
};
|
||||
#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
|
||||
#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
|
||||
|
||||
/* Transfer descriptor bit */
|
||||
enum TD_STS_BIT {
|
||||
TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
|
||||
TD_TFP0 = 0x10000000,
|
||||
};
|
||||
#define TDF1ST TD_TFP1
|
||||
#define TDFEND TD_TFP0
|
||||
#define TD_TFP (TD_TFP1|TD_TFP0)
|
||||
|
||||
/* RMCR */
|
||||
enum RECV_RST_BIT { RMCR_RST = 0x01, };
|
||||
/* ECMR */
|
||||
enum FELIC_MODE_BIT {
|
||||
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
|
||||
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
|
||||
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
|
||||
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
|
||||
ECMR_PRM = 0x00000001,
|
||||
};
|
||||
|
||||
/* ECSR */
|
||||
enum ECSR_STATUS_BIT {
|
||||
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04,
|
||||
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
|
||||
};
|
||||
|
||||
/* ECSIPR */
|
||||
enum ECSIPR_STATUS_MASK_BIT {
|
||||
ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04,
|
||||
ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
|
||||
};
|
||||
|
||||
/* APR */
|
||||
enum APR_BIT {
|
||||
APR_AP = 0x00000001,
|
||||
};
|
||||
|
||||
/* MPR */
|
||||
enum MPR_BIT {
|
||||
MPR_MP = 0x00000001,
|
||||
};
|
||||
|
||||
/* TRSCER */
|
||||
enum DESC_I_BIT {
|
||||
DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
|
||||
DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
|
||||
DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
|
||||
DESC_I_RINT1 = 0x0001,
|
||||
};
|
||||
|
||||
/* RPADIR */
|
||||
enum RPADIR_BIT {
|
||||
RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
|
||||
RPADIR_PADR = 0x0003f,
|
||||
};
|
||||
|
||||
/* FDR */
|
||||
enum FIFO_SIZE_BIT {
|
||||
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
|
||||
};
|
||||
enum phy_offsets {
|
||||
PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
|
||||
PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
|
||||
PHY_16 = 16,
|
||||
};
|
||||
|
||||
/* PHY_CTRL */
|
||||
enum PHY_CTRL_BIT {
|
||||
PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
|
||||
PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
|
||||
PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
|
||||
};
|
||||
#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
|
||||
|
||||
/* PHY_STAT */
|
||||
enum PHY_STAT_BIT {
|
||||
PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
|
||||
PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
|
||||
PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
|
||||
PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
|
||||
};
|
||||
|
||||
/* PHY_ANA */
|
||||
enum PHY_ANA_BIT {
|
||||
PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
|
||||
PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
|
||||
PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
|
||||
PHY_A_SEL = 0x001f,
|
||||
};
|
||||
/* PHY_ANL */
|
||||
enum PHY_ANL_BIT {
|
||||
PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
|
||||
PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
|
||||
PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
|
||||
PHY_L_SEL = 0x001f,
|
||||
};
|
||||
|
||||
/* PHY_ANE */
|
||||
enum PHY_ANE_BIT {
|
||||
PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
|
||||
PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
|
||||
};
|
||||
|
||||
/* DM9161 */
|
||||
enum PHY_16_BIT {
|
||||
PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
|
||||
PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
|
||||
PHY_16_TXselect = 0x0400,
|
||||
PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
|
||||
PHY_16_Force100LNK = 0x0080,
|
||||
PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
|
||||
PHY_16_RPDCTR_EN = 0x0010,
|
||||
PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
|
||||
PHY_16_Sleepmode = 0x0002,
|
||||
PHY_16_RemoteLoopOut = 0x0001,
|
||||
};
|
||||
|
||||
#define POST_RX 0x08
|
||||
#define POST_FW 0x04
|
||||
#define POST0_RX (POST_RX)
|
||||
#define POST0_FW (POST_FW)
|
||||
#define POST1_RX (POST_RX >> 2)
|
||||
#define POST1_FW (POST_FW >> 2)
|
||||
#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
|
||||
|
||||
/* ARSTR */
|
||||
enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
|
||||
|
||||
/* TSU_FWEN0 */
|
||||
enum TSU_FWEN0_BIT {
|
||||
TSU_FWEN0_0 = 0x00000001,
|
||||
};
|
||||
|
||||
/* TSU_ADSBSY */
|
||||
enum TSU_ADSBSY_BIT {
|
||||
TSU_ADSBSY_0 = 0x00000001,
|
||||
};
|
||||
|
||||
/* TSU_TEN */
|
||||
enum TSU_TEN_BIT {
|
||||
TSU_TEN_0 = 0x80000000,
|
||||
};
|
||||
|
||||
/* TSU_FWSL0 */
|
||||
enum TSU_FWSL0_BIT {
|
||||
TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
|
||||
TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
|
||||
TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
|
||||
};
|
||||
|
||||
/* TSU_FWSLC */
|
||||
enum TSU_FWSLC_BIT {
|
||||
TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
|
||||
TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
|
||||
TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
|
||||
TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
|
||||
TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
|
||||
};
|
||||
|
||||
/*
|
||||
* The sh ether Tx buffer descriptors.
|
||||
* This structure should be 20 bytes.
|
||||
*/
|
||||
struct sh_eth_txdesc {
|
||||
u32 status; /* TD0 */
|
||||
#if defined(CONFIG_CPU_LITTLE_ENDIAN)
|
||||
u16 pad0; /* TD1 */
|
||||
u16 buffer_length; /* TD1 */
|
||||
#else
|
||||
u16 buffer_length; /* TD1 */
|
||||
u16 pad0; /* TD1 */
|
||||
#endif
|
||||
u32 addr; /* TD2 */
|
||||
u32 pad1; /* padding data */
|
||||
};
|
||||
|
||||
/*
|
||||
* The sh ether Rx buffer descriptors.
|
||||
* This structure should be 20 bytes.
|
||||
*/
|
||||
struct sh_eth_rxdesc {
|
||||
u32 status; /* RD0 */
|
||||
#if defined(CONFIG_CPU_LITTLE_ENDIAN)
|
||||
u16 frame_length; /* RD1 */
|
||||
u16 buffer_length; /* RD1 */
|
||||
#else
|
||||
u16 buffer_length; /* RD1 */
|
||||
u16 frame_length; /* RD1 */
|
||||
#endif
|
||||
u32 addr; /* RD2 */
|
||||
u32 pad0; /* padding data */
|
||||
};
|
||||
|
||||
struct sh_eth_private {
|
||||
dma_addr_t rx_desc_dma;
|
||||
dma_addr_t tx_desc_dma;
|
||||
struct sh_eth_rxdesc *rx_ring;
|
||||
struct sh_eth_txdesc *tx_ring;
|
||||
struct sk_buff **rx_skbuff;
|
||||
struct sk_buff **tx_skbuff;
|
||||
struct net_device_stats stats;
|
||||
struct timer_list timer;
|
||||
spinlock_t lock;
|
||||
u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
|
||||
u32 cur_tx, dirty_tx;
|
||||
u32 rx_buf_sz; /* Based on MTU+slack. */
|
||||
/* MII transceiver section. */
|
||||
u32 phy_id; /* PHY ID */
|
||||
struct mii_bus *mii_bus; /* MDIO bus control */
|
||||
struct phy_device *phydev; /* PHY device control */
|
||||
enum phy_state link;
|
||||
int msg_enable;
|
||||
int speed;
|
||||
int duplex;
|
||||
u32 rx_int_var, tx_int_var; /* interrupt control variables */
|
||||
char post_rx; /* POST receive */
|
||||
char post_fw; /* POST forward */
|
||||
struct net_device_stats tsu_stats; /* TSU forward status */
|
||||
};
|
||||
|
||||
static void swaps(char *src, int len)
|
||||
{
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
u32 *p = (u32 *)src;
|
||||
u32 *maxp;
|
||||
maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
|
||||
|
||||
for (; p < maxp; p++)
|
||||
*p = swab32(*p);
|
||||
#endif
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -29,6 +29,7 @@
|
||||
#ifndef _SMC911X_H_
|
||||
#define _SMC911X_H_
|
||||
|
||||
#include <linux/smc911x.h>
|
||||
/*
|
||||
* Use the DMA feature on PXA chips
|
||||
*/
|
||||
@ -38,42 +39,161 @@
|
||||
#define SMC_USE_32BIT 1
|
||||
#define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
|
||||
#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
|
||||
#define SMC_USE_SH_DMA 0
|
||||
#define SMC_USE_16BIT 0
|
||||
#define SMC_USE_32BIT 1
|
||||
#define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
|
||||
#else
|
||||
/*
|
||||
* Default configuration
|
||||
*/
|
||||
|
||||
#define SMC_DYNAMIC_BUS_CONFIG
|
||||
#endif
|
||||
|
||||
/* store this information for the driver.. */
|
||||
struct smc911x_local {
|
||||
/*
|
||||
* If I have to wait until the DMA is finished and ready to reload a
|
||||
* packet, I will store the skbuff here. Then, the DMA will send it
|
||||
* out and free it.
|
||||
*/
|
||||
struct sk_buff *pending_tx_skb;
|
||||
|
||||
/* version/revision of the SMC911x chip */
|
||||
u16 version;
|
||||
u16 revision;
|
||||
|
||||
/* FIFO sizes */
|
||||
int tx_fifo_kb;
|
||||
int tx_fifo_size;
|
||||
int rx_fifo_size;
|
||||
int afc_cfg;
|
||||
|
||||
/* Contains the current active receive/phy mode */
|
||||
int ctl_rfduplx;
|
||||
int ctl_rspeed;
|
||||
|
||||
u32 msg_enable;
|
||||
u32 phy_type;
|
||||
struct mii_if_info mii;
|
||||
|
||||
/* work queue */
|
||||
struct work_struct phy_configure;
|
||||
int work_pending;
|
||||
|
||||
int tx_throttle;
|
||||
spinlock_t lock;
|
||||
|
||||
struct net_device *netdev;
|
||||
|
||||
#ifdef SMC_USE_DMA
|
||||
/* DMA needs the physical address of the chip */
|
||||
u_long physaddr;
|
||||
int rxdma;
|
||||
int txdma;
|
||||
int rxdma_active;
|
||||
int txdma_active;
|
||||
struct sk_buff *current_rx_skb;
|
||||
struct sk_buff *current_tx_skb;
|
||||
struct device *dev;
|
||||
#endif
|
||||
void __iomem *base;
|
||||
#ifdef SMC_DYNAMIC_BUS_CONFIG
|
||||
struct smc911x_platdata cfg;
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Define the bus width specific IO macros
|
||||
*/
|
||||
|
||||
#ifdef SMC_DYNAMIC_BUS_CONFIG
|
||||
static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
|
||||
{
|
||||
void __iomem *ioaddr = lp->base + reg;
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_32BIT)
|
||||
return readl(ioaddr);
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_16BIT)
|
||||
return readw(ioaddr) | (readw(ioaddr + 2) << 16);
|
||||
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
|
||||
int reg)
|
||||
{
|
||||
void __iomem *ioaddr = lp->base + reg;
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_32BIT) {
|
||||
writel(value, ioaddr);
|
||||
return;
|
||||
}
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_16BIT) {
|
||||
writew(value & 0xffff, ioaddr);
|
||||
writew(value >> 16, ioaddr + 2);
|
||||
return;
|
||||
}
|
||||
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void SMC_insl(struct smc911x_local *lp, int reg,
|
||||
void *addr, unsigned int count)
|
||||
{
|
||||
void __iomem *ioaddr = lp->base + reg;
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_32BIT) {
|
||||
readsl(ioaddr, addr, count);
|
||||
return;
|
||||
}
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_16BIT) {
|
||||
readsw(ioaddr, addr, count * 2);
|
||||
return;
|
||||
}
|
||||
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void SMC_outsl(struct smc911x_local *lp, int reg,
|
||||
void *addr, unsigned int count)
|
||||
{
|
||||
void __iomem *ioaddr = lp->base + reg;
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_32BIT) {
|
||||
writesl(ioaddr, addr, count);
|
||||
return;
|
||||
}
|
||||
|
||||
if (lp->cfg.flags & SMC911X_USE_16BIT) {
|
||||
writesw(ioaddr, addr, count * 2);
|
||||
return;
|
||||
}
|
||||
|
||||
BUG();
|
||||
}
|
||||
#else
|
||||
#if SMC_USE_16BIT
|
||||
#define SMC_inb(a, r) readb((a) + (r))
|
||||
#define SMC_inw(a, r) readw((a) + (r))
|
||||
#define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
|
||||
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
|
||||
#define SMC_outw(v, a, r) writew(v, (a) + (r))
|
||||
#define SMC_outl(v, a, r) \
|
||||
#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
|
||||
#define SMC_outl(v, lp, r) \
|
||||
do{ \
|
||||
writel(v & 0xFFFF, (a) + (r)); \
|
||||
writel(v >> 16, (a) + (r) + 2); \
|
||||
writew(v & 0xFFFF, (lp)->base + (r)); \
|
||||
writew(v >> 16, (lp)->base + (r) + 2); \
|
||||
} while (0)
|
||||
#define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2)
|
||||
#define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2)
|
||||
#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
|
||||
#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
|
||||
|
||||
#elif SMC_USE_32BIT
|
||||
#define SMC_inb(a, r) readb((a) + (r))
|
||||
#define SMC_inw(a, r) readw((a) + (r))
|
||||
#define SMC_inl(a, r) readl((a) + (r))
|
||||
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
|
||||
#define SMC_outl(v, a, r) writel(v, (a) + (r))
|
||||
#define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
|
||||
#define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
|
||||
#define SMC_inl(lp, r) readl((lp)->base + (r))
|
||||
#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
|
||||
#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
|
||||
#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
|
||||
|
||||
#endif /* SMC_USE_16BIT */
|
||||
|
||||
#endif /* SMC_DYNAMIC_BUS_CONFIG */
|
||||
|
||||
|
||||
#ifdef SMC_USE_PXA_DMA
|
||||
@ -110,22 +230,22 @@ static int rx_dmalen, tx_dmalen;
|
||||
|
||||
#ifdef SMC_insl
|
||||
#undef SMC_insl
|
||||
#define SMC_insl(a, r, p, l) \
|
||||
smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
|
||||
#define SMC_insl(lp, r, p, l) \
|
||||
smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
|
||||
|
||||
static inline void
|
||||
smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
|
||||
smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
|
||||
int reg, int dma, u_char *buf, int len)
|
||||
{
|
||||
/* 64 bit alignment is required for memory to memory DMA */
|
||||
if ((long)buf & 4) {
|
||||
*((u32 *)buf) = SMC_inl(ioaddr, reg);
|
||||
*((u32 *)buf) = SMC_inl(lp, reg);
|
||||
buf += 4;
|
||||
len--;
|
||||
}
|
||||
|
||||
len *= 4;
|
||||
rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
|
||||
rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
|
||||
rx_dmalen = len;
|
||||
DCSR(dma) = DCSR_NODESC;
|
||||
DTADR(dma) = rx_dmabuf;
|
||||
@ -136,52 +256,24 @@ smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SMC_insw
|
||||
#undef SMC_insw
|
||||
#define SMC_insw(a, r, p, l) \
|
||||
smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
|
||||
|
||||
static inline void
|
||||
smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
|
||||
int reg, int dma, u_char *buf, int len)
|
||||
{
|
||||
/* 64 bit alignment is required for memory to memory DMA */
|
||||
while ((long)buf & 6) {
|
||||
*((u16 *)buf) = SMC_inw(ioaddr, reg);
|
||||
buf += 2;
|
||||
len--;
|
||||
}
|
||||
|
||||
len *= 2;
|
||||
rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
|
||||
rx_dmalen = len;
|
||||
DCSR(dma) = DCSR_NODESC;
|
||||
DTADR(dma) = rx_dmabuf;
|
||||
DSADR(dma) = physaddr + reg;
|
||||
DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
|
||||
DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
|
||||
DCSR(dma) = DCSR_NODESC | DCSR_RUN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SMC_outsl
|
||||
#undef SMC_outsl
|
||||
#define SMC_outsl(a, r, p, l) \
|
||||
smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
|
||||
#define SMC_outsl(lp, r, p, l) \
|
||||
smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
|
||||
|
||||
static inline void
|
||||
smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
|
||||
smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
|
||||
int reg, int dma, u_char *buf, int len)
|
||||
{
|
||||
/* 64 bit alignment is required for memory to memory DMA */
|
||||
if ((long)buf & 4) {
|
||||
SMC_outl(*((u32 *)buf), ioaddr, reg);
|
||||
SMC_outl(*((u32 *)buf), lp, reg);
|
||||
buf += 4;
|
||||
len--;
|
||||
}
|
||||
|
||||
len *= 4;
|
||||
tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
|
||||
tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
|
||||
tx_dmalen = len;
|
||||
DCSR(dma) = DCSR_NODESC;
|
||||
DSADR(dma) = tx_dmabuf;
|
||||
@ -191,35 +283,6 @@ smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
|
||||
DCSR(dma) = DCSR_NODESC | DCSR_RUN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SMC_outsw
|
||||
#undef SMC_outsw
|
||||
#define SMC_outsw(a, r, p, l) \
|
||||
smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
|
||||
|
||||
static inline void
|
||||
smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
|
||||
int reg, int dma, u_char *buf, int len)
|
||||
{
|
||||
/* 64 bit alignment is required for memory to memory DMA */
|
||||
while ((long)buf & 6) {
|
||||
SMC_outw(*((u16 *)buf), ioaddr, reg);
|
||||
buf += 2;
|
||||
len--;
|
||||
}
|
||||
|
||||
len *= 2;
|
||||
tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
|
||||
tx_dmalen = len;
|
||||
DCSR(dma) = DCSR_NODESC;
|
||||
DSADR(dma) = tx_dmabuf;
|
||||
DTADR(dma) = physaddr + reg;
|
||||
DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
|
||||
DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
|
||||
DCSR(dma) = DCSR_NODESC | DCSR_RUN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SMC_USE_PXA_DMA */
|
||||
|
||||
|
||||
@ -629,213 +692,213 @@ static const struct chip_id chip_ids[] = {
|
||||
* capabilities. Please use those and not the in/out primitives.
|
||||
*/
|
||||
/* FIFO read/write macros */
|
||||
#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
|
||||
#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
|
||||
#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO )
|
||||
#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO )
|
||||
#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
|
||||
#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
|
||||
#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
|
||||
#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
|
||||
|
||||
|
||||
/* I/O mapped register read/write macros */
|
||||
#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO )
|
||||
#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO )
|
||||
#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
|
||||
#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16)
|
||||
#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
|
||||
#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG )
|
||||
#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG )
|
||||
#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS )
|
||||
#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS )
|
||||
#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN )
|
||||
#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN )
|
||||
#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST )
|
||||
#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST )
|
||||
#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT )
|
||||
#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT )
|
||||
#define SMC_SET_FIFO_TDA(x) \
|
||||
#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
|
||||
#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
|
||||
#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
|
||||
#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
|
||||
#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
|
||||
#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
|
||||
#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
|
||||
#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
|
||||
#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
|
||||
#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
|
||||
#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
|
||||
#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
|
||||
#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
|
||||
#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
|
||||
#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
|
||||
#define SMC_SET_FIFO_TDA(lp, x) \
|
||||
do { \
|
||||
unsigned long __flags; \
|
||||
int __mask; \
|
||||
local_irq_save(__flags); \
|
||||
__mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \
|
||||
SMC_SET_FIFO_INT( __mask | (x)<<24 ); \
|
||||
__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
|
||||
SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
|
||||
local_irq_restore(__flags); \
|
||||
} while (0)
|
||||
#define SMC_SET_FIFO_TSL(x) \
|
||||
#define SMC_SET_FIFO_TSL(lp, x) \
|
||||
do { \
|
||||
unsigned long __flags; \
|
||||
int __mask; \
|
||||
local_irq_save(__flags); \
|
||||
__mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \
|
||||
SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
|
||||
__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
|
||||
SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
|
||||
local_irq_restore(__flags); \
|
||||
} while (0)
|
||||
#define SMC_SET_FIFO_RSA(x) \
|
||||
#define SMC_SET_FIFO_RSA(lp, x) \
|
||||
do { \
|
||||
unsigned long __flags; \
|
||||
int __mask; \
|
||||
local_irq_save(__flags); \
|
||||
__mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \
|
||||
SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \
|
||||
__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
|
||||
SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
|
||||
local_irq_restore(__flags); \
|
||||
} while (0)
|
||||
#define SMC_SET_FIFO_RSL(x) \
|
||||
#define SMC_SET_FIFO_RSL(lp, x) \
|
||||
do { \
|
||||
unsigned long __flags; \
|
||||
int __mask; \
|
||||
local_irq_save(__flags); \
|
||||
__mask = SMC_GET_FIFO_INT() & ~0xFF; \
|
||||
SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \
|
||||
__mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
|
||||
SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
|
||||
local_irq_restore(__flags); \
|
||||
} while (0)
|
||||
#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG )
|
||||
#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG )
|
||||
#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG )
|
||||
#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG )
|
||||
#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG )
|
||||
#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG )
|
||||
#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL )
|
||||
#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL )
|
||||
#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL )
|
||||
#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL )
|
||||
#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG )
|
||||
#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG )
|
||||
#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF )
|
||||
#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF )
|
||||
#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF )
|
||||
#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF )
|
||||
#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG )
|
||||
#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG )
|
||||
#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP )
|
||||
#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP )
|
||||
#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD )
|
||||
#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD )
|
||||
#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA )
|
||||
#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA )
|
||||
#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG )
|
||||
#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG )
|
||||
#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD )
|
||||
#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD )
|
||||
#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA )
|
||||
#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA )
|
||||
#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
|
||||
#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
|
||||
#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
|
||||
#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
|
||||
#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
|
||||
#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
|
||||
#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
|
||||
#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
|
||||
#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
|
||||
#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
|
||||
#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
|
||||
#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
|
||||
#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
|
||||
#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
|
||||
#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
|
||||
#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
|
||||
#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
|
||||
#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
|
||||
#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
|
||||
#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
|
||||
#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
|
||||
#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
|
||||
#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
|
||||
#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
|
||||
#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
|
||||
#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
|
||||
#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
|
||||
#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
|
||||
#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
|
||||
#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
|
||||
|
||||
/* MAC register read/write macros */
|
||||
#define SMC_GET_MAC_CSR(a,v) \
|
||||
#define SMC_GET_MAC_CSR(lp,a,v) \
|
||||
do { \
|
||||
while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \
|
||||
while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
|
||||
MAC_CSR_CMD_R_NOT_W_ | (a) ); \
|
||||
while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
v = SMC_GET_MAC_DATA(); \
|
||||
while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
v = SMC_GET_MAC_DATA((lp)); \
|
||||
} while (0)
|
||||
#define SMC_SET_MAC_CSR(a,v) \
|
||||
#define SMC_SET_MAC_CSR(lp,a,v) \
|
||||
do { \
|
||||
while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
SMC_SET_MAC_DATA(v); \
|
||||
SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
|
||||
while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
SMC_SET_MAC_DATA((lp), v); \
|
||||
SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
|
||||
while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
} while (0)
|
||||
#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x )
|
||||
#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x )
|
||||
#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x )
|
||||
#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x )
|
||||
#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x )
|
||||
#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x )
|
||||
#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x )
|
||||
#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x )
|
||||
#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x )
|
||||
#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x )
|
||||
#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x )
|
||||
#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x )
|
||||
#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x )
|
||||
#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x )
|
||||
#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x )
|
||||
#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x )
|
||||
#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x )
|
||||
#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x )
|
||||
#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x )
|
||||
#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x )
|
||||
#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x )
|
||||
#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x )
|
||||
#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x )
|
||||
#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
|
||||
#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
|
||||
#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
|
||||
#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
|
||||
#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
|
||||
#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
|
||||
#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
|
||||
#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
|
||||
#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
|
||||
#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
|
||||
#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
|
||||
#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
|
||||
#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
|
||||
#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
|
||||
#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
|
||||
#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
|
||||
#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
|
||||
#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
|
||||
#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
|
||||
#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
|
||||
#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
|
||||
#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
|
||||
#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
|
||||
|
||||
/* PHY register read/write macros */
|
||||
#define SMC_GET_MII(a,phy,v) \
|
||||
#define SMC_GET_MII(lp,a,phy,v) \
|
||||
do { \
|
||||
u32 __v; \
|
||||
do { \
|
||||
SMC_GET_MII_ACC(__v); \
|
||||
SMC_GET_MII_ACC((lp), __v); \
|
||||
} while ( __v & MII_ACC_MII_BUSY_ ); \
|
||||
SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
|
||||
SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
|
||||
MII_ACC_MII_BUSY_); \
|
||||
do { \
|
||||
SMC_GET_MII_ACC(__v); \
|
||||
SMC_GET_MII_ACC( (lp), __v); \
|
||||
} while ( __v & MII_ACC_MII_BUSY_ ); \
|
||||
SMC_GET_MII_DATA(v); \
|
||||
SMC_GET_MII_DATA((lp), v); \
|
||||
} while (0)
|
||||
#define SMC_SET_MII(a,phy,v) \
|
||||
#define SMC_SET_MII(lp,a,phy,v) \
|
||||
do { \
|
||||
u32 __v; \
|
||||
do { \
|
||||
SMC_GET_MII_ACC(__v); \
|
||||
SMC_GET_MII_ACC((lp), __v); \
|
||||
} while ( __v & MII_ACC_MII_BUSY_ ); \
|
||||
SMC_SET_MII_DATA(v); \
|
||||
SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
|
||||
SMC_SET_MII_DATA((lp), v); \
|
||||
SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
|
||||
MII_ACC_MII_BUSY_ | \
|
||||
MII_ACC_MII_WRITE_ ); \
|
||||
do { \
|
||||
SMC_GET_MII_ACC(__v); \
|
||||
SMC_GET_MII_ACC((lp), __v); \
|
||||
} while ( __v & MII_ACC_MII_BUSY_ ); \
|
||||
} while (0)
|
||||
#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x )
|
||||
#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x )
|
||||
#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x )
|
||||
#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x )
|
||||
#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x )
|
||||
#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x )
|
||||
#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x )
|
||||
#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x )
|
||||
#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x )
|
||||
#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
|
||||
#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
|
||||
#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x )
|
||||
#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x )
|
||||
#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x )
|
||||
#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x )
|
||||
#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x )
|
||||
#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
|
||||
#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
|
||||
#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
|
||||
#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
|
||||
#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
|
||||
#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
|
||||
#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
|
||||
#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
|
||||
#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
|
||||
#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
|
||||
#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
|
||||
#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
|
||||
#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
|
||||
#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
|
||||
#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
|
||||
#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
|
||||
|
||||
|
||||
|
||||
/* Misc read/write macros */
|
||||
|
||||
#ifndef SMC_GET_MAC_ADDR
|
||||
#define SMC_GET_MAC_ADDR(addr) \
|
||||
#define SMC_GET_MAC_ADDR(lp, addr) \
|
||||
do { \
|
||||
unsigned int __v; \
|
||||
\
|
||||
SMC_GET_MAC_CSR(ADDRL, __v); \
|
||||
SMC_GET_MAC_CSR((lp), ADDRL, __v); \
|
||||
addr[0] = __v; addr[1] = __v >> 8; \
|
||||
addr[2] = __v >> 16; addr[3] = __v >> 24; \
|
||||
SMC_GET_MAC_CSR(ADDRH, __v); \
|
||||
SMC_GET_MAC_CSR((lp), ADDRH, __v); \
|
||||
addr[4] = __v; addr[5] = __v >> 8; \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#define SMC_SET_MAC_ADDR(addr) \
|
||||
#define SMC_SET_MAC_ADDR(lp, addr) \
|
||||
do { \
|
||||
SMC_SET_MAC_CSR(ADDRL, \
|
||||
SMC_SET_MAC_CSR((lp), ADDRL, \
|
||||
addr[0] | \
|
||||
(addr[1] << 8) | \
|
||||
(addr[2] << 16) | \
|
||||
(addr[3] << 24)); \
|
||||
SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
|
||||
SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
|
||||
} while (0)
|
||||
|
||||
|
||||
#define SMC_WRITE_EEPROM_CMD(cmd, addr) \
|
||||
#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
|
||||
do { \
|
||||
while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \
|
||||
while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
|
||||
while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
|
||||
} while (0)
|
||||
|
||||
#endif /* _SMC911X_H_ */
|
||||
|
||||
@ -915,15 +915,11 @@ static void build_fake_packet(struct lance_private *lp)
|
||||
lp->tx_new = TX_NEXT(entry);
|
||||
}
|
||||
|
||||
struct net_device *last_dev;
|
||||
|
||||
static int lance_open(struct net_device *dev)
|
||||
{
|
||||
struct lance_private *lp = netdev_priv(dev);
|
||||
int status = 0;
|
||||
|
||||
last_dev = dev;
|
||||
|
||||
STOP_LANCE(lp);
|
||||
|
||||
if (request_irq(dev->irq, &lance_interrupt, IRQF_SHARED,
|
||||
|
||||
@ -154,6 +154,16 @@ config USB_NET_AX8817X
|
||||
This driver creates an interface named "ethX", where X depends on
|
||||
what other networking devices you have in use.
|
||||
|
||||
config USB_HSO
|
||||
tristate "Option USB High Speed Mobile Devices"
|
||||
depends on USB && RFKILL
|
||||
default n
|
||||
help
|
||||
Choose this option if you have an Option HSDPA/HSUPA card.
|
||||
These cards support downlink speeds of 7.2Mbps or greater.
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called hso.
|
||||
|
||||
config USB_NET_CDCETHER
|
||||
tristate "CDC Ethernet support (smart devices such as cable modems)"
|
||||
|
||||
@ -6,6 +6,7 @@ obj-$(CONFIG_USB_CATC) += catc.o
|
||||
obj-$(CONFIG_USB_KAWETH) += kaweth.o
|
||||
obj-$(CONFIG_USB_PEGASUS) += pegasus.o
|
||||
obj-$(CONFIG_USB_RTL8150) += rtl8150.o
|
||||
obj-$(CONFIG_USB_HSO) += hso.o
|
||||
obj-$(CONFIG_USB_NET_AX8817X) += asix.o
|
||||
obj-$(CONFIG_USB_NET_CDCETHER) += cdc_ether.o
|
||||
obj-$(CONFIG_USB_NET_DM9601) += dm9601.o
|
||||
|
||||
2836
drivers/net/usb/hso.c
Normal file
2836
drivers/net/usb/hso.c
Normal file
File diff suppressed because it is too large
Load Diff
12
include/linux/smc911x.h
Normal file
12
include/linux/smc911x.h
Normal file
@ -0,0 +1,12 @@
|
||||
#ifndef __SMC911X_H__
|
||||
#define __SMC911X_H__
|
||||
|
||||
#define SMC911X_USE_16BIT (1 << 0)
|
||||
#define SMC911X_USE_32BIT (1 << 1)
|
||||
|
||||
struct smc911x_platdata {
|
||||
unsigned long flags;
|
||||
unsigned long irq_flags; /* IRQF_... */
|
||||
};
|
||||
|
||||
#endif /* __SMC911X_H__ */
|
||||
Loading…
Reference in New Issue
Block a user