forked from Minki/linux
[ALSA] PCI168 snd-azt3328 Linux driver: another huge update
- figured out 'Digital(ly) Enhanced Game Port' functionality, implemented support for it (eliminating gameport polling overhead) - removed optional joystick activation, gameport now enabled unconditionally, since we now support it via the PCI I/O space, not via conflict-prone legacy I/O (which I was thus able to DISABLE now)! - fix playback bug (a muted wave output would get unmuted upon start of playback, of course this is not what we want, thus remember mute state) - implement partial power management: when idle, lower clock rate and disable codec (reduced noise!), and disable gameport circuit when unused - instantiate OPL3 timer, too - much better implementation of snd_azf3328_mixer_write_volume_gradually() - slightly optimized interrupt handling - lots of cleanup This time, I also found a way to verify proper OPL3 operation via MIDI file playback (emulation via synth hardware). Signed-off-by: Andreas Mohr <andi@lisas.de> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Andreas Mohr
Jaroslav Kysela
parent
f99a633a15
commit
02330fbaad
1200
sound/pci/azt3328.c
1200
sound/pci/azt3328.c
File diff suppressed because it is too large
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@ -54,7 +54,10 @@
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#define SOUNDFORMAT_XTAL1 0x00
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#define SOUNDFORMAT_XTAL2 0x01
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/* all _SUSPECTED_ values are not used by Windows drivers, so we don't
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* have any hard facts, only rough measurements */
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* have any hard facts, only rough measurements.
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* All we know is that the crystal used on the board has 24.576MHz,
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* like many soundcards (which results in the frequencies below when
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* using certain divider values selected by the values below) */
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#define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a | SOUNDFORMAT_XTAL1
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#define SOUNDFORMAT_FREQ_5510 0x0c | SOUNDFORMAT_XTAL2
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@ -72,6 +75,26 @@
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#define SOUNDFORMAT_FLAG_16BIT 0x0010
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#define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
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/* define frequency helpers, for maximum value safety */
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enum {
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#define AZF_FREQ(rate) AZF_FREQ_##rate = rate
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AZF_FREQ(4000),
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AZF_FREQ(4800),
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AZF_FREQ(5512),
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AZF_FREQ(6620),
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AZF_FREQ(8000),
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AZF_FREQ(9600),
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AZF_FREQ(11025),
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AZF_FREQ(13240),
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AZF_FREQ(16000),
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AZF_FREQ(22050),
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AZF_FREQ(32000),
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AZF_FREQ(44100),
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AZF_FREQ(48000),
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AZF_FREQ(66200),
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#undef AZF_FREQ
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} AZF_FREQUENCIES;
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/** recording area (see also: playback bit flag definitions) **/
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#define IDX_IO_REC_FLAGS 0x20 /* ??, PU:0x0000 */
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#define IDX_IO_REC_IRQTYPE 0x22 /* ??, PU:0x0000 */
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@ -97,40 +120,164 @@
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/** DirectX timer, main interrupt area (FIXME: and something else?) **/
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#define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */
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#define TIMER_VALUE_MASK 0x000fffffUL /* timer countdown value; triggers IRQ when timer is finished */
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#define TIMER_ENABLE_COUNTDOWN 0x01000000UL /* activate the timer countdown */
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#define TIMER_ENABLE_IRQ 0x02000000UL /* trigger timer IRQ on zero transition */
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#define TIMER_ACK_IRQ 0x04000000UL /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) had 0x0020 set upon IRQ handler */
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/* timer countdown value; triggers IRQ when timer is finished */
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#define TIMER_VALUE_MASK 0x000fffffUL
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/* activate timer countdown */
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#define TIMER_COUNTDOWN_ENABLE 0x01000000UL
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/* trigger timer IRQ on zero transition */
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#define TIMER_IRQ_ENABLE 0x02000000UL
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/* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?)
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* had 0x0020 set upon IRQ handler */
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#define TIMER_IRQ_ACK 0x04000000UL
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#define IDX_IO_IRQSTATUS 0x64
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#define IRQ_PLAYBACK 0x0001
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#define IRQ_RECORDING 0x0002
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#define IRQ_MPU401 0x0010
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#define IRQ_TIMER 0x0020 /* DirectX timer */
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#define IRQ_UNKNOWN1 0x0040 /* probably unused, or possibly I2S port? or gameport IRQ? */
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#define IRQ_UNKNOWN2 0x0080 /* probably unused, or possibly I2S port? or gameport IRQ? */
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/* some IRQ bit in here might also be used to signal a power-management timer
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* timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).
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* Some OPL3 hardware (e.g. in LM4560) has some special timer hardware which
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* can trigger an OPL3 timer IRQ, so maybe there's such a thing as well... */
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#define IRQ_PLAYBACK 0x0001
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#define IRQ_RECORDING 0x0002
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#define IRQ_UNKNOWN1 0x0004 /* most probably I2S port */
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#define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
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#define IRQ_MPU401 0x0010
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#define IRQ_TIMER 0x0020 /* DirectX timer */
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#define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly I2S port? */
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#define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly I2S port? */
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#define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */
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#define IDX_IO_SOME_VALUE 0x68 /* this is set to e.g. 0x3ff or 0x300, and writable; maybe some buffer limit, but I couldn't find out more, PU:0x00ff */
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#define IDX_IO_6AH 0x6A /* this WORD can be set to have bits 0x0028 activated (FIXME: correct??); actually inhibits PCM playback!!! maybe power management?? */
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#define IO_6A_PAUSE_PLAYBACK 0x0200 /* bit 9; sure, this pauses playback, but what the heck is this really about?? */
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#define IDX_IO_6CH 0x6C
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#define IDX_IO_6EH 0x6E /* writing 0xffff returns 0x83fe */
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/* further I/O indices not saved/restored, so probably not used */
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/* this is set to e.g. 0x3ff or 0x300, and writable;
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* maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
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#define IDX_IO_SOME_VALUE 0x68
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#define IO_68_RANDOM_TOGGLE1 0x0100 /* toggles randomly */
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#define IO_68_RANDOM_TOGGLE2 0x0200 /* toggles randomly */
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/* umm, nope, behaviour of these bits changes depending on what we wrote
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* to 0x6b!! */
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/* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);
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* actually inhibits PCM playback!!! maybe power management??: */
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#define IDX_IO_6AH 0x6A
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/* bit 5: enabling this will activate permanent counting of bytes 2/3
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* at gameport I/O (0xb402/3) (equal values each) and cause
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* gameport legacy I/O at 0x0200 to be _DISABLED_!
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* Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode
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* for Enhanced Digital Gameport (see 4D Wave DX card): */
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#define IO_6A_SOMETHING1_GAMEPORT 0x0020
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/* bit 8; sure, this _pauses_ playback (later resumes at same spot!),
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* but what the heck is this really about??: */
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#define IO_6A_PAUSE_PLAYBACK_BIT8 0x0100
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/* bit 9; sure, this _pauses_ playback (later resumes at same spot!),
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* but what the heck is this really about??: */
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#define IO_6A_PAUSE_PLAYBACK_BIT9 0x0200
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/* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback,
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* thus it suggests influence on PCM only!!
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* However OTOH there seems to be no bit anywhere around here
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* which is able to disable OPL3... */
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/* bit 10: enabling this actually changes values at legacy gameport
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* I/O address (0x200); is this enabling of the Digital Enhanced Game Port???
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* Or maybe this simply switches off the NE558 circuit, since enabling this
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* still lets us evaluate button states, but not axis states */
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#define IO_6A_SOMETHING2_GAMEPORT 0x0400
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/* writing 0x0300: causes quite some crackling during
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* PC activity such as switching windows (PCI traffic??
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* --> FIFO/timing settings???) */
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/* writing 0x0100 plus/or 0x0200 inhibits playback */
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/* since the Windows .INF file has Flag_Enable_JoyStick and
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* Flag_Enable_SB_DOS_Emulation directly together, it stands to reason
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* that some other bit in this same register might be responsible
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* for SB DOS Emulation activation (note that the file did NOT define
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* a switch for OPL3!) */
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#define IDX_IO_6CH 0x6C /* unknown; fully read-writable */
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#define IDX_IO_6EH 0x6E
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/* writing 0xffff returns 0x83fe (or 0x03fe only).
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* writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch
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* from 0000 to ffff. */
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/* further I/O indices not saved/restored and not readable after writing,
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* so probably not used */
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/*** I/O 2 area port indices ***/
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/*** Gameport area port indices ***/
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/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
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#define AZF_IO_SIZE_IO2 0x08
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#define AZF_IO_SIZE_IO2_PM 0x06
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#define AZF_IO_SIZE_GAME 0x08
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#define AZF_IO_SIZE_GAME_PM 0x06
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#define IDX_IO2_LEGACY_ADDR 0x04
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#define LEGACY_SOMETHING 0x01 /* OPL3?? */
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#define LEGACY_JOY 0x08
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enum {
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AZF_GAME_LEGACY_IO_PORT = 0x200
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} AZF_GAME_CONFIGS;
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#define IDX_GAME_LEGACY_COMPATIBLE 0x00
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/* in some operation mode, writing anything to this port
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* triggers an interrupt:
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* yup, that's in case IDX_GAME_01H has one of the
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* axis measurement bits enabled
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* (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */
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#define IDX_GAME_AXES_CONFIG 0x01
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/* NOTE: layout of this register awfully similar (read: "identical??")
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* to AD1815JS.pdf (p.29) */
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/* enables axis 1 (X axis) measurement: */
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#define GAME_AXES_ENABLE_1 0x01
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/* enables axis 2 (Y axis) measurement: */
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#define GAME_AXES_ENABLE_2 0x02
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/* enables axis 3 (X axis) measurement: */
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#define GAME_AXES_ENABLE_3 0x04
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/* enables axis 4 (Y axis) measurement: */
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#define GAME_AXES_ENABLE_4 0x08
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/* selects the current axis to read the measured value of
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* (at IDX_GAME_AXIS_VALUE):
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* 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */
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#define GAME_AXES_READ_MASK 0x30
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/* enable to have the latch continuously accept ADC values
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* (and continuously cause interrupts in case interrupts are enabled);
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* AD1815JS.pdf says it's ~16ms interval there: */
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#define GAME_AXES_LATCH_ENABLE 0x40
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/* joystick data (measured axes) ready for reading: */
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#define GAME_AXES_SAMPLING_READY 0x80
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/* NOTE: other card specs (SiS960 and others!) state that the
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* game position latches should be frozen when reading and be freed
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* (== reset?) after reading!!!
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* Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE),
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* but how to free the value? */
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/* An internet search for "gameport latch ADC" should provide some insight
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* into how to program such a gameport system. */
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/* writing 0xf0 to 01H once reset both counters to 0, in some special mode!?
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* yup, in case 6AH 0x20 is not enabled
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* (and 0x40 is sufficient, 0xf0 is not needed) */
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#define IDX_GAME_AXIS_VALUE 0x02
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/* R: value of currently configured axis (word value!);
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* W: trigger axis measurement */
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#define IDX_GAME_HWCONFIG 0x04
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/* note: bits 4 to 7 are never set (== 0) when reading!
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* --> reserved bits? */
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/* enables IRQ notification upon axes measurement ready: */
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#define GAME_HWCFG_IRQ_ENABLE 0x01
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/* these bits choose a different frequency for the
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* internal ADC counter increment.
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* hmm, seems to be a combo of bits:
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* 00 --> standard frequency
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* 10 --> 1/2
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* 01 --> 1/20
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* 11 --> 1/200: */
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#define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06
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/* enable gameport legacy I/O address (0x200)
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* I was unable to locate any configurability for a different address: */
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#define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08
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/*** MPU401 ***/
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#define AZF_IO_SIZE_MPU 0x04
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#define AZF_IO_SIZE_MPU_PM 0x04
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#define AZF_IO_SIZE_SYNTH 0x08
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#define AZF_IO_SIZE_SYNTH_PM 0x06
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/*** OPL3 synth ***/
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#define AZF_IO_SIZE_OPL3 0x08
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#define AZF_IO_SIZE_OPL3_PM 0x06
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/* hmm, given that a standard OPL3 has 4 registers only,
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* there might be some enhanced functionality lurking at the end
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* (especially since register 0x04 has a "non-empty" value 0xfe) */
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/*** mixer I/O area port indices ***/
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/* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
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