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[PATCH] ppc32: ppc440 pagetable attributes (comments updates)

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Here's an incremental patch with comment updates and some additional
grammar cleanups.

Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Matt Porter 2005-08-06 07:21:06 -07:00 committed by Linus Torvalds
parent 534afb90a9
commit 021a52ac70
1 changed files with 13 additions and 13 deletions
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26
include/asm-ppc/pgtable.h
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@ -227,21 +227,21 @@ extern unsigned long ioremap_bot, ioremap_base;
* doesn't support SMP. So we can use this as software bit, like * doesn't support SMP. So we can use this as software bit, like
* DIRTY. * DIRTY.
* *
* PPC Book-E Linux implementation uses PPC HW PTE bit field definition, * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
* even it doesn't have HW PTE. 0-11th LSB of PTE stand for memory * for memory protection related functions (see PTE structure in
* protection-related function. (See PTE structure in include/asm-ppc/mmu.h) * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
* Definition of _PAGE_XXX in "include/asm-ppc/pagetable.h" stands for * above bits. Note that the bit values are CPU specific, not architecture
* above bits. Note that those bits values are CPU dependent, not * specific.
* architecture.
* *
* Kernel PTE entry holds arch-dependent swp_entry structure under certain * The kernel PTE entry holds an arch-dependent swp_entry structure under
* situation. In other words, in such situation, some portion of PTE bits * certain situations. In other words, in such situations some portion of
* are used as swp_entry. In PPC implementation, 3-24th LSB are shared with * the PTE bits are used as a swp_entry. In the PPC implementation, the
* swp_entry, however 0-2nd three LSB still hold protection values. * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
* That means three protection bits are reserved for both PTE and SWAP * hold protection values. That means the three protection bits are
* entry at the most three LSBs. * reserved for both PTE and SWAP entry at the most significant three
* LSBs.
* *
* There are three protection bits available for SWAP entry; * There are three protection bits available for SWAP entry:
* _PAGE_PRESENT * _PAGE_PRESENT
* _PAGE_FILE * _PAGE_FILE
* _PAGE_HASHPTE (if HW has) * _PAGE_HASHPTE (if HW has)