ath9k_hw: increase tx status ring buffer size
AR9003 chips read tx status from ring buffer whose max number of status descriptor is mininal compared to max number of tx buffers. On a stress condition, it can be easily overflown which might cause false tx hung detection. Though increasing number of max status descriptors consumes more memory, it helps to avoid false positive chip resets. Cc: Paul Stewart <pstew@google.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -583,7 +583,7 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
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void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
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u32 ts_paddr_start,
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u8 size)
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u16 size)
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{
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ah->ts_paddr_start = ts_paddr_start;
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@ -118,5 +118,5 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
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void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
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void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
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u32 ts_paddr_start,
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u8 size);
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u16 size);
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#endif
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@ -97,7 +97,7 @@ enum buffer_type {
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#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
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#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
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#define ATH_TXSTATUS_RING_SIZE 64
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#define ATH_TXSTATUS_RING_SIZE 512
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#define DS2PHYS(_dd, _ds) \
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((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
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@ -1016,7 +1016,7 @@ struct ath_hw {
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u32 ts_paddr_start;
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u32 ts_paddr_end;
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u16 ts_tail;
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u8 ts_size;
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u16 ts_size;
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u32 bb_watchdog_last_status;
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u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
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