Merge branch 'acpica'

* acpica: (22 commits)
  ACPICA: Update version to 20170119
  ACPICA: Tools: Update common signon, remove compilation bit width
  ACPICA: Source tree: Update copyright notices to 2017
  ACPICA: Linuxize: Restore and fix Intel compiler build
  ACPICA: Update version to 20161222
  ACPICA: Parser: Update parse info table for some operators
  ACPICA: Fix a problem with recent extra support for control method invocations
  ACPICA: Parser: Allow method invocations as target operands
  ACPICA: Fix for implicit result conversion for the ToXXX functions
  ACPICA: Resources: Not a valid resource if buffer length too long
  ACPICA: Utilities: Update debug output
  ACPICA: Disassembler: Add Switch/Case disassembly support
  ACPICA: EFI: Add efihello demo application
  ACPICA: MSVC: Fix MSVC6 build issues
  ACPICA: Linux-specific header: Add support for s390x compilation
  ACPICA: Hardware: Add sleep register hooks
  ACPICA: Macro header: Fix some typos in comments
  ACPICA: Hardware: Sort access bit width algorithm
  ACPICA: Utilities: Add power of two rounding support
  ACPICA: Hardware: Add access_width/bit_offset support in acpi_hw_write()
  ...
This commit is contained in:
Rafael J. Wysocki 2017-02-20 14:27:08 +01:00
commit 014f40393e
226 changed files with 720 additions and 385 deletions

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -51,26 +51,26 @@
/* Common info for tool signons */
#define ACPICA_NAME "Intel ACPI Component Architecture"
#define ACPICA_COPYRIGHT "Copyright (c) 2000 - 2016 Intel Corporation"
#define ACPICA_COPYRIGHT "Copyright (c) 2000 - 2017 Intel Corporation"
#if ACPI_MACHINE_WIDTH == 64
#define ACPI_WIDTH "-64"
#define ACPI_WIDTH " (64-bit version)"
#elif ACPI_MACHINE_WIDTH == 32
#define ACPI_WIDTH "-32"
#define ACPI_WIDTH " (32-bit version)"
#else
#error unknown ACPI_MACHINE_WIDTH
#define ACPI_WIDTH "-??"
#define ACPI_WIDTH " (unknown bit width, not 32 or 64)"
#endif
/* Macros for signons and file headers */
#define ACPI_COMMON_SIGNON(utility_name) \
"\n%s\n%s version %8.8X%s\n%s\n\n", \
"\n%s\n%s version %8.8X\n%s\n\n", \
ACPICA_NAME, \
utility_name, ((u32) ACPI_CA_VERSION), ACPI_WIDTH, \
utility_name, ((u32) ACPI_CA_VERSION), \
ACPICA_COPYRIGHT
#define ACPI_COMMON_HEADER(utility_name, prefix) \

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -770,7 +770,7 @@ union acpi_parse_value {
char *operator_symbol;/* Used for C-style operator name strings */\
char aml_op_name[16]) /* Op name (debug only) */
/* Flags for disasm_flags field above */
/* Internal opcodes for disasm_opcode field above */
#define ACPI_DASM_BUFFER 0x00 /* Buffer is a simple data buffer */
#define ACPI_DASM_RESOURCE 0x01 /* Buffer is a Resource Descriptor */
@ -783,7 +783,10 @@ union acpi_parse_value {
#define ACPI_DASM_LNOT_PREFIX 0x08 /* Start of a Lnot_equal (etc.) pair of opcodes */
#define ACPI_DASM_LNOT_SUFFIX 0x09 /* End of a Lnot_equal (etc.) pair of opcodes */
#define ACPI_DASM_HID_STRING 0x0A /* String is a _HID or _CID */
#define ACPI_DASM_IGNORE 0x0B /* Not used at this time */
#define ACPI_DASM_IGNORE_SINGLE 0x0B /* Ignore the opcode but not it's children */
#define ACPI_DASM_SWITCH_PREDICATE 0x0C /* Object is a predicate for a Switch or Case block */
#define ACPI_DASM_CASE 0x0D /* If/Else is a Case in a Switch/Case block */
#define ACPI_DASM_DEFAULT 0x0E /* Else is a Default in a Switch/Case block */
/*
* Generic operation (for example: If, While, Store)

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -46,7 +46,7 @@
/*
* Extract data using a pointer. Any more than a byte and we
* get into potential aligment issues -- see the STORE macros below.
* get into potential alignment issues -- see the STORE macros below.
* Use with care.
*/
#define ACPI_CAST8(ptr) ACPI_CAST_PTR (u8, (ptr))
@ -63,7 +63,7 @@
#define ACPI_SET64(ptr, val) (*ACPI_CAST64 (ptr) = (u64) (val))
/*
* printf() format helper. This macros is a workaround for the difficulties
* printf() format helper. This macro is a workaround for the difficulties
* with emitting 64-bit integers and 64-bit pointers with the same code
* for both 32-bit and 64-bit hosts.
*/
@ -260,8 +260,70 @@
#define ACPI_IS_MISALIGNED(value) (((acpi_size) value) & (sizeof(acpi_size)-1))
/* Generic bit manipulation */
#ifndef ACPI_USE_NATIVE_BIT_FINDER
#define __ACPI_FIND_LAST_BIT_2(a, r) ((((u8) (a)) & 0x02) ? (r)+1 : (r))
#define __ACPI_FIND_LAST_BIT_4(a, r) ((((u8) (a)) & 0x0C) ? \
__ACPI_FIND_LAST_BIT_2 ((a)>>2, (r)+2) : \
__ACPI_FIND_LAST_BIT_2 ((a), (r)))
#define __ACPI_FIND_LAST_BIT_8(a, r) ((((u8) (a)) & 0xF0) ? \
__ACPI_FIND_LAST_BIT_4 ((a)>>4, (r)+4) : \
__ACPI_FIND_LAST_BIT_4 ((a), (r)))
#define __ACPI_FIND_LAST_BIT_16(a, r) ((((u16) (a)) & 0xFF00) ? \
__ACPI_FIND_LAST_BIT_8 ((a)>>8, (r)+8) : \
__ACPI_FIND_LAST_BIT_8 ((a), (r)))
#define __ACPI_FIND_LAST_BIT_32(a, r) ((((u32) (a)) & 0xFFFF0000) ? \
__ACPI_FIND_LAST_BIT_16 ((a)>>16, (r)+16) : \
__ACPI_FIND_LAST_BIT_16 ((a), (r)))
#define __ACPI_FIND_LAST_BIT_64(a, r) ((((u64) (a)) & 0xFFFFFFFF00000000) ? \
__ACPI_FIND_LAST_BIT_32 ((a)>>32, (r)+32) : \
__ACPI_FIND_LAST_BIT_32 ((a), (r)))
#define ACPI_FIND_LAST_BIT_8(a) ((a) ? __ACPI_FIND_LAST_BIT_8 (a, 1) : 0)
#define ACPI_FIND_LAST_BIT_16(a) ((a) ? __ACPI_FIND_LAST_BIT_16 (a, 1) : 0)
#define ACPI_FIND_LAST_BIT_32(a) ((a) ? __ACPI_FIND_LAST_BIT_32 (a, 1) : 0)
#define ACPI_FIND_LAST_BIT_64(a) ((a) ? __ACPI_FIND_LAST_BIT_64 (a, 1) : 0)
#define __ACPI_FIND_FIRST_BIT_2(a, r) ((((u8) (a)) & 0x01) ? (r) : (r)+1)
#define __ACPI_FIND_FIRST_BIT_4(a, r) ((((u8) (a)) & 0x03) ? \
__ACPI_FIND_FIRST_BIT_2 ((a), (r)) : \
__ACPI_FIND_FIRST_BIT_2 ((a)>>2, (r)+2))
#define __ACPI_FIND_FIRST_BIT_8(a, r) ((((u8) (a)) & 0x0F) ? \
__ACPI_FIND_FIRST_BIT_4 ((a), (r)) : \
__ACPI_FIND_FIRST_BIT_4 ((a)>>4, (r)+4))
#define __ACPI_FIND_FIRST_BIT_16(a, r) ((((u16) (a)) & 0x00FF) ? \
__ACPI_FIND_FIRST_BIT_8 ((a), (r)) : \
__ACPI_FIND_FIRST_BIT_8 ((a)>>8, (r)+8))
#define __ACPI_FIND_FIRST_BIT_32(a, r) ((((u32) (a)) & 0x0000FFFF) ? \
__ACPI_FIND_FIRST_BIT_16 ((a), (r)) : \
__ACPI_FIND_FIRST_BIT_16 ((a)>>16, (r)+16))
#define __ACPI_FIND_FIRST_BIT_64(a, r) ((((u64) (a)) & 0x00000000FFFFFFFF) ? \
__ACPI_FIND_FIRST_BIT_32 ((a), (r)) : \
__ACPI_FIND_FIRST_BIT_32 ((a)>>32, (r)+32))
#define ACPI_FIND_FIRST_BIT_8(a) ((a) ? __ACPI_FIND_FIRST_BIT_8 (a, 1) : 0)
#define ACPI_FIND_FIRST_BIT_16(a) ((a) ? __ACPI_FIND_FIRST_BIT_16 (a, 1) : 0)
#define ACPI_FIND_FIRST_BIT_32(a) ((a) ? __ACPI_FIND_FIRST_BIT_32 (a, 1) : 0)
#define ACPI_FIND_FIRST_BIT_64(a) ((a) ? __ACPI_FIND_FIRST_BIT_64 (a, 1) : 0)
#endif /* ACPI_USE_NATIVE_BIT_FINDER */
/* Generic (power-of-two) rounding */
#define ACPI_ROUND_UP_POWER_OF_TWO_8(a) ((u8) \
(((u16) 1) << ACPI_FIND_LAST_BIT_8 ((a) - 1)))
#define ACPI_ROUND_DOWN_POWER_OF_TWO_8(a) ((u8) \
(((u16) 1) << (ACPI_FIND_LAST_BIT_8 ((a)) - 1)))
#define ACPI_ROUND_UP_POWER_OF_TWO_16(a) ((u16) \
(((u32) 1) << ACPI_FIND_LAST_BIT_16 ((a) - 1)))
#define ACPI_ROUND_DOWN_POWER_OF_TWO_16(a) ((u16) \
(((u32) 1) << (ACPI_FIND_LAST_BIT_16 ((a)) - 1)))
#define ACPI_ROUND_UP_POWER_OF_TWO_32(a) ((u32) \
(((u64) 1) << ACPI_FIND_LAST_BIT_32 ((a) - 1)))
#define ACPI_ROUND_DOWN_POWER_OF_TWO_32(a) ((u32) \
(((u64) 1) << (ACPI_FIND_LAST_BIT_32 ((a)) - 1)))
#define ACPI_IS_ALIGNED(a, s) (((a) & ((s) - 1)) == 0)
#define ACPI_IS_POWER_OF_TWO(a) ACPI_IS_ALIGNED(a, a)
@ -270,8 +332,8 @@
* Bit positions start at zero.
* MASK_BITS_ABOVE creates a mask starting AT the position and above
* MASK_BITS_BELOW creates a mask starting one bit BELOW the position
* MASK_BITS_ABOVE/BELOW accpets a bit offset to create a mask
* MASK_BITS_ABOVE/BELOW_32/64 accpets a bit width to create a mask
* MASK_BITS_ABOVE/BELOW accepts a bit offset to create a mask
* MASK_BITS_ABOVE/BELOW_32/64 accepts a bit width to create a mask
* Note: The ACPI_INTEGER_BIT_SIZE check is used to bypass compiler
* differences with the shift operator
*/
@ -389,7 +451,7 @@
*/
#ifndef ACPI_NO_ERROR_MESSAGES
/*
* Error reporting. Callers module and line number are inserted by AE_INFO,
* Error reporting. The callers module and line number are inserted by AE_INFO,
* the plist contains a set of parens to allow variable-length lists.
* These macros are used for both the debug and non-debug versions of the code.
*/

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -92,7 +92,7 @@
#define ARGP_BYTELIST_OP ARGP_LIST1 (ARGP_NAMESTRING)
#define ARGP_CONCAT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET)
#define ARGP_CONCAT_RES_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET)
#define ARGP_COND_REF_OF_OP ARGP_LIST2 (ARGP_NAME_OR_REF,ARGP_TARGET)
#define ARGP_COND_REF_OF_OP ARGP_LIST2 (ARGP_SIMPLENAME, ARGP_TARGET)
#define ARGP_CONNECTFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING)
#define ARGP_CONTINUE_OP ARG_NONE
#define ARGP_COPY_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_SIMPLENAME)
@ -105,7 +105,7 @@
#define ARGP_DATA_REGION_OP ARGP_LIST4 (ARGP_NAME, ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG)
#define ARGP_DEBUG_OP ARG_NONE
#define ARGP_DECREMENT_OP ARGP_LIST1 (ARGP_SUPERNAME)
#define ARGP_DEREF_OF_OP ARGP_LIST1 (ARGP_TERMARG)
#define ARGP_DEREF_OF_OP ARGP_LIST1 (ARGP_SUPERNAME)
#define ARGP_DEVICE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_OBJLIST)
#define ARGP_DIVIDE_OP ARGP_LIST4 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET, ARGP_TARGET)
#define ARGP_DWORD_OP ARGP_LIST1 (ARGP_DWORDDATA)
@ -152,14 +152,14 @@
#define ARGP_NAMEPATH_OP ARGP_LIST1 (ARGP_NAMESTRING)
#define ARGP_NOOP_OP ARG_NONE
#define ARGP_NOTIFY_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_TERMARG)
#define ARGP_OBJECT_TYPE_OP ARGP_LIST1 (ARGP_NAME_OR_REF)
#define ARGP_OBJECT_TYPE_OP ARGP_LIST1 (ARGP_SIMPLENAME)
#define ARGP_ONE_OP ARG_NONE
#define ARGP_ONES_OP ARG_NONE
#define ARGP_PACKAGE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_BYTEDATA, ARGP_DATAOBJLIST)
#define ARGP_POWER_RES_OP ARGP_LIST5 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_BYTEDATA, ARGP_WORDDATA, ARGP_OBJLIST)
#define ARGP_PROCESSOR_OP ARGP_LIST6 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_BYTEDATA, ARGP_DWORDDATA, ARGP_BYTEDATA, ARGP_OBJLIST)
#define ARGP_QWORD_OP ARGP_LIST1 (ARGP_QWORDDATA)
#define ARGP_REF_OF_OP ARGP_LIST1 (ARGP_NAME_OR_REF)
#define ARGP_REF_OF_OP ARGP_LIST1 (ARGP_SIMPLENAME)
#define ARGP_REGION_OP ARGP_LIST4 (ARGP_NAME, ARGP_BYTEDATA, ARGP_TERMARG, ARGP_TERMARG)
#define ARGP_RELEASE_OP ARGP_LIST1 (ARGP_SUPERNAME)
#define ARGP_RESERVEDFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING)
@ -249,7 +249,7 @@
#define ARGI_FIELD_OP ARGI_INVALID_OPCODE
#define ARGI_FIND_SET_LEFT_BIT_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF)
#define ARGI_FIND_SET_RIGHT_BIT_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF)
#define ARGI_FROM_BCD_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_FIXED_TARGET)
#define ARGI_FROM_BCD_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF)
#define ARGI_IF_OP ARGI_INVALID_OPCODE
#define ARGI_INCREMENT_OP ARGI_LIST1 (ARGI_TARGETREF)
#define ARGI_INDEX_FIELD_OP ARGI_INVALID_OPCODE
@ -313,12 +313,12 @@
#define ARGI_SUBTRACT_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF)
#define ARGI_THERMAL_ZONE_OP ARGI_INVALID_OPCODE
#define ARGI_TIMER_OP ARG_NONE
#define ARGI_TO_BCD_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_FIXED_TARGET)
#define ARGI_TO_BUFFER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
#define ARGI_TO_DEC_STR_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
#define ARGI_TO_HEX_STR_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
#define ARGI_TO_INTEGER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
#define ARGI_TO_STRING_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_FIXED_TARGET)
#define ARGI_TO_BCD_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF)
#define ARGI_TO_BUFFER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_TARGETREF)
#define ARGI_TO_DEC_STR_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_TARGETREF)
#define ARGI_TO_HEX_STR_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_TARGETREF)
#define ARGI_TO_INTEGER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_TARGETREF)
#define ARGI_TO_STRING_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_TARGETREF)
#define ARGI_UNLOAD_OP ARGI_LIST1 (ARGI_DDBHANDLE)
#define ARGI_VAR_PACKAGE_OP ARGI_LIST1 (ARGI_INTEGER)
#define ARGI_WAIT_OP ARGI_LIST2 (ARGI_EVENT, ARGI_INTEGER)

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -7,7 +7,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -277,9 +277,23 @@
#define ARGI_DEVICE_REF 0x0D
#define ARGI_REFERENCE 0x0E
#define ARGI_TARGETREF 0x0F /* Target, subject to implicit conversion */
#define ARGI_FIXED_TARGET 0x10 /* Target, no implicit conversion */
#define ARGI_SIMPLE_TARGET 0x11 /* Name, Local, Arg -- no implicit conversion */
#define ARGI_STORE_TARGET 0x12 /* Target for store is TARGETREF + package objects */
#define ARGI_SIMPLE_TARGET 0x10 /* Name, Local, Arg -- no implicit conversion */
#define ARGI_STORE_TARGET 0x11 /* Target for store is TARGETREF + package objects */
/*
* #define ARGI_FIXED_TARGET 0x10 Target, no implicit conversion
*
* Removed 10/2016. ARGI_FIXED_TARGET was used for these operators:
* from_BCD
* to_BCD
* to_decimal_string
* to_hex_string
* to_integer
* to_buffer
* The purpose of this type was to disable "implicit result conversion",
* but this was incorrect per the ACPI spec and other ACPI implementations.
* These operators now have the target operand defined as a normal
* ARGI_TARGETREF.
*/
/* Multiple/complex types */

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -6,7 +6,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -430,7 +430,7 @@ acpi_status acpi_initialize_debugger(void)
/* These were created with one unit, grab it */
status = acpi_os_initialize_command_signals();
status = acpi_os_initialize_debugger();
if (ACPI_FAILURE(status)) {
acpi_os_printf("Could not get debugger mutex\n");
return_ACPI_STATUS(status);
@ -482,7 +482,7 @@ void acpi_terminate_debugger(void)
acpi_os_sleep(100);
}
acpi_os_terminate_command_signals();
acpi_os_terminate_debugger();
}
if (acpi_gbl_db_buffer) {

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -592,7 +592,6 @@ acpi_ex_convert_to_target_type(acpi_object_type destination_type,
*/
switch (GET_CURRENT_ARG_TYPE(walk_state->op_info->runtime_args)) {
case ARGI_SIMPLE_TARGET:
case ARGI_FIXED_TARGET:
case ARGI_INTEGER_REF: /* Handles Increment, Decrement cases */
switch (destination_type) {

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -305,7 +305,6 @@ acpi_ex_resolve_operands(u16 opcode,
case ARGI_OBJECT_REF:
case ARGI_DEVICE_REF:
case ARGI_TARGETREF: /* Allows implicit conversion rules before store */
case ARGI_FIXED_TARGET: /* No implicit conversion before store to target */
case ARGI_SIMPLE_TARGET: /* Name, Local, or arg - no implicit conversion */
case ARGI_STORE_TARGET:

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -43,7 +43,6 @@
*/
#include <acpi/acpi.h>
#include <linux/acpi.h>
#include "accommon.h"
#define _COMPONENT ACPI_HARDWARE
@ -103,7 +102,7 @@ void acpi_hw_execute_sleep_method(char *method_pathname, u32 integer_argument)
acpi_status acpi_hw_extended_sleep(u8 sleep_state)
{
acpi_status status;
u8 sleep_type_value;
u8 sleep_control;
u64 sleep_status;
ACPI_FUNCTION_TRACE(hw_extended_sleep);
@ -125,18 +124,6 @@ acpi_status acpi_hw_extended_sleep(u8 sleep_state)
acpi_gbl_system_awake_and_running = FALSE;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE();
status = acpi_os_prepare_extended_sleep(sleep_state,
acpi_gbl_sleep_type_a,
acpi_gbl_sleep_type_b);
if (ACPI_SKIP(status))
return_ACPI_STATUS(AE_OK);
if (ACPI_FAILURE(status))
return_ACPI_STATUS(status);
/*
* Set the SLP_TYP and SLP_EN bits.
*
@ -146,12 +133,22 @@ acpi_status acpi_hw_extended_sleep(u8 sleep_state)
ACPI_DEBUG_PRINT((ACPI_DB_INIT,
"Entering sleep state [S%u]\n", sleep_state));
sleep_type_value =
((acpi_gbl_sleep_type_a << ACPI_X_SLEEP_TYPE_POSITION) &
ACPI_X_SLEEP_TYPE_MASK);
sleep_control = ((acpi_gbl_sleep_type_a << ACPI_X_SLEEP_TYPE_POSITION) &
ACPI_X_SLEEP_TYPE_MASK) | ACPI_X_SLEEP_ENABLE;
status = acpi_write((u64)(sleep_type_value | ACPI_X_SLEEP_ENABLE),
&acpi_gbl_FADT.sleep_control);
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE();
status = acpi_os_enter_sleep(sleep_state, sleep_control, 0);
if (status == AE_CTRL_TERMINATE) {
return_ACPI_STATUS(AE_OK);
}
if (ACPI_FAILURE(status)) {
return_ACPI_STATUS(status);
}
status = acpi_write((u64)sleep_control, &acpi_gbl_FADT.sleep_control);
if (ACPI_FAILURE(status)) {
return_ACPI_STATUS(status);
}

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,7 +6,7 @@
******************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -52,7 +52,8 @@ ACPI_MODULE_NAME("hwregs")
#if (!ACPI_REDUCED_HARDWARE)
/* Local Prototypes */
static u8
acpi_hw_get_access_bit_width(struct acpi_generic_address *reg,
acpi_hw_get_access_bit_width(u64 address,
struct acpi_generic_address *reg,
u8 max_bit_width);
static acpi_status
@ -71,7 +72,8 @@ acpi_hw_write_multiple(u32 value,
*
* FUNCTION: acpi_hw_get_access_bit_width
*
* PARAMETERS: reg - GAS register structure
* PARAMETERS: address - GAS register address
* reg - GAS register structure
* max_bit_width - Max bit_width supported (32 or 64)
*
* RETURN: Status
@ -81,27 +83,59 @@ acpi_hw_write_multiple(u32 value,
******************************************************************************/
static u8
acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, u8 max_bit_width)
acpi_hw_get_access_bit_width(u64 address,
struct acpi_generic_address *reg, u8 max_bit_width)
{
if (!reg->access_width) {
if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
max_bit_width = 32;
}
u8 access_bit_width;
/*
* Detect old register descriptors where only the bit_width field
* makes senses.
*/
if (reg->bit_width < max_bit_width &&
!reg->bit_offset && reg->bit_width &&
ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
ACPI_IS_ALIGNED(reg->bit_width, 8)) {
return (reg->bit_width);
}
return (max_bit_width);
/*
* GAS format "register", used by FADT:
* 1. Detected if bit_offset is 0 and bit_width is 8/16/32/64;
* 2. access_size field is ignored and bit_width field is used for
* determining the boundary of the IO accesses.
* GAS format "region", used by APEI registers:
* 1. Detected if bit_offset is not 0 or bit_width is not 8/16/32/64;
* 2. access_size field is used for determining the boundary of the
* IO accesses;
* 3. bit_offset/bit_width fields are used to describe the "region".
*
* Note: This algorithm assumes that the "Address" fields should always
* contain aligned values.
*/
if (!reg->bit_offset && reg->bit_width &&
ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
ACPI_IS_ALIGNED(reg->bit_width, 8)) {
access_bit_width = reg->bit_width;
} else if (reg->access_width) {
access_bit_width = (1 << (reg->access_width + 2));
} else {
return (1 << (reg->access_width + 2));
access_bit_width =
ACPI_ROUND_UP_POWER_OF_TWO_8(reg->bit_offset +
reg->bit_width);
if (access_bit_width <= 8) {
access_bit_width = 8;
} else {
while (!ACPI_IS_ALIGNED(address, access_bit_width >> 3)) {
access_bit_width >>= 1;
}
}
}
/* Maximum IO port access bit width is 32 */
if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
max_bit_width = 32;
}
/*
* Return access width according to the requested maximum access bit width,
* as the caller should know the format of the register and may enforce
* a 32-bit accesses.
*/
if (access_bit_width < max_bit_width) {
return (access_bit_width);
}
return (max_bit_width);
}
/******************************************************************************
@ -163,7 +197,8 @@ acpi_hw_validate_register(struct acpi_generic_address *reg,
/* Validate the bit_width, convert access_width into number of bits */
access_width = acpi_hw_get_access_bit_width(reg, max_bit_width);
access_width =
acpi_hw_get_access_bit_width(*address, reg, max_bit_width);
bit_width =
ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width);
if (max_bit_width < bit_width) {
@ -219,7 +254,7 @@ acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
* into number of bits based
*/
*value = 0;
access_width = acpi_hw_get_access_bit_width(reg, 32);
access_width = acpi_hw_get_access_bit_width(address, reg, 32);
bit_width = reg->bit_offset + reg->bit_width;
bit_offset = reg->bit_offset;
@ -252,20 +287,6 @@ acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
&value32,
access_width);
}
/*
* Use offset style bit masks because:
* bit_offset < access_width/bit_width < access_width, and
* access_width is ensured to be less than 32-bits by
* acpi_hw_validate_register().
*/
if (bit_offset) {
value32 &= ACPI_MASK_BITS_BELOW(bit_offset);
bit_offset = 0;
}
if (bit_width < access_width) {
value32 &= ACPI_MASK_BITS_ABOVE(bit_width);
}
}
/*
@ -306,6 +327,12 @@ acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
{
u64 address;
u8 access_width;
u32 bit_width;
u8 bit_offset;
u64 value64;
u32 value32;
u8 index;
acpi_status status;
ACPI_FUNCTION_NAME(hw_write);
@ -317,23 +344,61 @@ acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
return (status);
}
/* Convert access_width into number of bits based */
access_width = acpi_hw_get_access_bit_width(address, reg, 32);
bit_width = reg->bit_offset + reg->bit_width;
bit_offset = reg->bit_offset;
/*
* Two address spaces supported: Memory or IO. PCI_Config is
* not supported here because the GAS structure is insufficient
*/
if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
status = acpi_os_write_memory((acpi_physical_address)
address, (u64)value,
reg->bit_width);
} else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
index = 0;
while (bit_width) {
/*
* Use offset style bit reads because "Index * AccessWidth" is
* ensured to be less than 32-bits by acpi_hw_validate_register().
*/
value32 = ACPI_GET_BITS(&value, index * access_width,
ACPI_MASK_BITS_ABOVE_32(access_width));
status = acpi_hw_write_port((acpi_io_address)
address, value, reg->bit_width);
if (bit_offset >= access_width) {
bit_offset -= access_width;
} else {
if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
value64 = (u64)value32;
status =
acpi_os_write_memory((acpi_physical_address)
address +
index *
ACPI_DIV_8
(access_width),
value64, access_width);
} else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
status = acpi_hw_write_port((acpi_io_address)
address +
index *
ACPI_DIV_8
(access_width),
value32,
access_width);
}
}
/*
* Index * access_width is ensured to be less than 32-bits by
* acpi_hw_validate_register().
*/
bit_width -=
bit_width > access_width ? access_width : bit_width;
index++;
}
ACPI_DEBUG_PRINT((ACPI_DB_IO,
"Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
value, reg->bit_width, ACPI_FORMAT_UINT64(address),
value, access_width, ACPI_FORMAT_UINT64(address),
acpi_ut_get_region_name(reg->space_id)));
return (status);

View File

@ -6,7 +6,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -43,7 +43,6 @@
*/
#include <acpi/acpi.h>
#include <linux/acpi.h>
#include "accommon.h"
#define _COMPONENT ACPI_HARDWARE
@ -152,12 +151,14 @@ acpi_status acpi_hw_legacy_sleep(u8 sleep_state)
ACPI_FLUSH_CPU_CACHE();
status = acpi_os_prepare_sleep(sleep_state, pm1a_control,
pm1b_control);
if (ACPI_SKIP(status))
status = acpi_os_enter_sleep(sleep_state, pm1a_control, pm1b_control);
if (status == AE_CTRL_TERMINATE) {
return_ACPI_STATUS(AE_OK);
if (ACPI_FAILURE(status))
}
if (ACPI_FAILURE(status)) {
return_ACPI_STATUS(status);
}
/* Write #2: Write both SLP_TYP + SLP_EN */
status = acpi_hw_write_pm1_control(pm1a_control, pm1b_control);

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2016, Intel Corp.
* Copyright (C) 2000 - 2017, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

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