drm/amdgpu: split pipeline sync out of SDMA vm_flush() as well
Code it similar to how we did it for the gfx and compute engines. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -822,19 +822,14 @@ static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
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}
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/**
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* cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
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* cik_sdma_ring_emit_pipeline_sync - sync the pipeline
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*
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* @ring: amdgpu_ring pointer
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* @vm: amdgpu_vm pointer
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*
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* Update the page table base and flush the VM TLB
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* using sDMA (CIK).
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* Make sure all previous operations are completed (CIK).
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*/
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static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
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{
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u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
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SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
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uint32_t seq = ring->fence_drv.sync_seq;
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uint64_t addr = ring->fence_drv.gpu_addr;
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@ -848,7 +843,22 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, seq); /* reference */
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amdgpu_ring_write(ring, 0xfffffff); /* mask */
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amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
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}
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/**
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* cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
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*
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* @ring: amdgpu_ring pointer
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* @vm: amdgpu_vm pointer
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*
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* Update the page table base and flush the VM TLB
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* using sDMA (CIK).
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*/
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static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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{
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u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
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SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
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amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
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if (vm_id < 8) {
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@ -1290,6 +1300,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
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.parse_cs = NULL,
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.emit_ib = cik_sdma_ring_emit_ib,
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.emit_fence = cik_sdma_ring_emit_fence,
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.emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
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.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
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.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
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.emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
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@ -880,16 +880,13 @@ static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib
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}
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/**
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* sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
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* sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
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*
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* @ring: amdgpu_ring pointer
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* @vm: amdgpu_vm pointer
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*
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* Update the page table base and flush the VM TLB
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* using sDMA (VI).
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* Make sure all previous operations are completed (CIK).
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*/
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static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
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{
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uint32_t seq = ring->fence_drv.sync_seq;
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uint64_t addr = ring->fence_drv.gpu_addr;
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@ -905,7 +902,20 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, 0xfffffff); /* mask */
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amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
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SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
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}
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/**
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* sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
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*
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* @ring: amdgpu_ring pointer
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* @vm: amdgpu_vm pointer
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*
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* Update the page table base and flush the VM TLB
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* using sDMA (VI).
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*/
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static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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{
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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if (vm_id < 8) {
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@ -1295,6 +1305,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
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.parse_cs = NULL,
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.emit_ib = sdma_v2_4_ring_emit_ib,
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.emit_fence = sdma_v2_4_ring_emit_fence,
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.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
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.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
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.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
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.emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
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@ -1031,16 +1031,13 @@ static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib
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}
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/**
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* sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
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* sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
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*
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* @ring: amdgpu_ring pointer
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* @vm: amdgpu_vm pointer
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*
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* Update the page table base and flush the VM TLB
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* using sDMA (VI).
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* Make sure all previous operations are completed (CIK).
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*/
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static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
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{
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uint32_t seq = ring->fence_drv.sync_seq;
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uint64_t addr = ring->fence_drv.gpu_addr;
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@ -1056,7 +1053,20 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, 0xfffffff); /* mask */
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amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
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SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
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}
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/**
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* sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
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*
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* @ring: amdgpu_ring pointer
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* @vm: amdgpu_vm pointer
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*
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* Update the page table base and flush the VM TLB
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* using sDMA (VI).
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*/
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static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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{
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
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SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
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if (vm_id < 8) {
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@ -1563,6 +1573,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
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.parse_cs = NULL,
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.emit_ib = sdma_v3_0_ring_emit_ib,
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.emit_fence = sdma_v3_0_ring_emit_fence,
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.emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
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.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
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.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
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.emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
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