2018-05-14 20:56:35 -04:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Renesas R-Car MIPI CSI-2 Receiver
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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2019-03-12 19:49:30 -04:00
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#include <linux/reset.h>
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2018-05-14 20:56:35 -04:00
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#include <linux/sys_soc.h>
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2022-01-23 16:58:17 +01:00
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#include <media/mipi-csi2.h>
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2018-05-14 20:56:35 -04:00
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-mc.h>
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#include <media/v4l2-subdev.h>
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struct rcar_csi2;
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/* Register offsets and bits */
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/* Control Timing Select */
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#define TREF_REG 0x00
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#define TREF_TREF BIT(0)
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/* Software Reset */
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#define SRST_REG 0x04
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#define SRST_SRST BIT(0)
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/* PHY Operation Control */
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#define PHYCNT_REG 0x08
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#define PHYCNT_SHUTDOWNZ BIT(17)
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#define PHYCNT_RSTZ BIT(16)
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#define PHYCNT_ENABLECLK BIT(4)
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#define PHYCNT_ENABLE_3 BIT(3)
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#define PHYCNT_ENABLE_2 BIT(2)
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#define PHYCNT_ENABLE_1 BIT(1)
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#define PHYCNT_ENABLE_0 BIT(0)
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/* Checksum Control */
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#define CHKSUM_REG 0x0c
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#define CHKSUM_ECC_EN BIT(1)
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#define CHKSUM_CRC_EN BIT(0)
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/*
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* Channel Data Type Select
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2020-04-24 12:39:45 +02:00
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* VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
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* VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
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2018-05-14 20:56:35 -04:00
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*/
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#define VCDT_REG 0x10
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#define VCDT2_REG 0x14
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#define VCDT_VCDTN_EN BIT(15)
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#define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
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#define VCDT_SEL_DTN_ON BIT(6)
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#define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
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/* Frame Data Type Select */
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#define FRDT_REG 0x18
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/* Field Detection Control */
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#define FLD_REG 0x1c
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#define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
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2019-04-11 16:34:44 -04:00
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#define FLD_DET_SEL(n) (((n) & 0x3) << 4)
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2018-05-14 20:56:35 -04:00
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#define FLD_FLD_EN4 BIT(3)
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#define FLD_FLD_EN3 BIT(2)
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#define FLD_FLD_EN2 BIT(1)
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#define FLD_FLD_EN BIT(0)
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/* Automatic Standby Control */
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#define ASTBY_REG 0x20
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/* Long Data Type Setting 0 */
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#define LNGDT0_REG 0x28
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/* Long Data Type Setting 1 */
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#define LNGDT1_REG 0x2c
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/* Interrupt Enable */
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#define INTEN_REG 0x30
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2019-04-11 16:30:58 -04:00
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#define INTEN_INT_AFIFO_OF BIT(27)
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#define INTEN_INT_ERRSOTHS BIT(4)
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#define INTEN_INT_ERRSOTSYNCHS BIT(3)
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2018-05-14 20:56:35 -04:00
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/* Interrupt Source Mask */
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#define INTCLOSE_REG 0x34
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/* Interrupt Status Monitor */
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#define INTSTATE_REG 0x38
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#define INTSTATE_INT_ULPS_START BIT(7)
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#define INTSTATE_INT_ULPS_END BIT(6)
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/* Interrupt Error Status Monitor */
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#define INTERRSTATE_REG 0x3c
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/* Short Packet Data */
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#define SHPDAT_REG 0x40
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/* Short Packet Count */
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#define SHPCNT_REG 0x44
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/* LINK Operation Control */
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#define LINKCNT_REG 0x48
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#define LINKCNT_MONITOR_EN BIT(31)
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#define LINKCNT_REG_MONI_PACT_EN BIT(25)
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#define LINKCNT_ICLK_NONSTOP BIT(24)
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/* Lane Swap */
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#define LSWAP_REG 0x4c
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#define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
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#define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
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#define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
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#define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
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/* PHY Test Interface Write Register */
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#define PHTW_REG 0x50
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#define PHTW_DWEN BIT(24)
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#define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
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#define PHTW_CWEN BIT(8)
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#define PHTW_TESTDIN_CODE(n) ((n & 0xff))
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2021-06-12 10:46:29 +02:00
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#define PHYFRX_REG 0x64
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#define PHYFRX_FORCERX_MODE_3 BIT(3)
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#define PHYFRX_FORCERX_MODE_2 BIT(2)
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#define PHYFRX_FORCERX_MODE_1 BIT(1)
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#define PHYFRX_FORCERX_MODE_0 BIT(0)
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2018-05-14 20:56:35 -04:00
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struct phtw_value {
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u16 data;
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u16 code;
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};
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struct rcsi2_mbps_reg {
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u16 mbps;
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u16 reg;
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};
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2021-06-12 10:46:29 +02:00
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static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = {
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{ .mbps = 1500, .reg = 0xcc },
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{ .mbps = 1550, .reg = 0x1d },
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{ .mbps = 1600, .reg = 0x27 },
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{ .mbps = 1650, .reg = 0x30 },
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{ .mbps = 1700, .reg = 0x39 },
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{ .mbps = 1750, .reg = 0x42 },
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{ .mbps = 1800, .reg = 0x4b },
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{ .mbps = 1850, .reg = 0x55 },
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{ .mbps = 1900, .reg = 0x5e },
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{ .mbps = 1950, .reg = 0x67 },
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{ .mbps = 2000, .reg = 0x71 },
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{ .mbps = 2050, .reg = 0x79 },
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{ .mbps = 2100, .reg = 0x83 },
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{ .mbps = 2150, .reg = 0x8c },
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{ .mbps = 2200, .reg = 0x95 },
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{ .mbps = 2250, .reg = 0x9e },
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{ .mbps = 2300, .reg = 0xa7 },
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{ .mbps = 2350, .reg = 0xb0 },
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{ .mbps = 2400, .reg = 0xba },
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{ .mbps = 2450, .reg = 0xc3 },
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{ .mbps = 2500, .reg = 0xcc },
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{ /* sentinel */ },
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};
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2018-05-14 20:56:35 -04:00
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static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
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{ .mbps = 80, .reg = 0x86 },
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{ .mbps = 90, .reg = 0x86 },
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{ .mbps = 100, .reg = 0x87 },
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{ .mbps = 110, .reg = 0x87 },
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{ .mbps = 120, .reg = 0x88 },
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{ .mbps = 130, .reg = 0x88 },
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{ .mbps = 140, .reg = 0x89 },
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{ .mbps = 150, .reg = 0x89 },
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{ .mbps = 160, .reg = 0x8a },
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{ .mbps = 170, .reg = 0x8a },
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{ .mbps = 180, .reg = 0x8b },
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{ .mbps = 190, .reg = 0x8b },
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{ .mbps = 205, .reg = 0x8c },
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{ .mbps = 220, .reg = 0x8d },
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{ .mbps = 235, .reg = 0x8e },
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{ .mbps = 250, .reg = 0x8e },
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{ /* sentinel */ },
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};
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static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
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2018-12-10 09:53:55 -05:00
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{ .mbps = 80, .reg = 0x00 },
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{ .mbps = 90, .reg = 0x20 },
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{ .mbps = 100, .reg = 0x40 },
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{ .mbps = 110, .reg = 0x02 },
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{ .mbps = 130, .reg = 0x22 },
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{ .mbps = 140, .reg = 0x42 },
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{ .mbps = 150, .reg = 0x04 },
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{ .mbps = 170, .reg = 0x24 },
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{ .mbps = 180, .reg = 0x44 },
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{ .mbps = 200, .reg = 0x06 },
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{ .mbps = 220, .reg = 0x26 },
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{ .mbps = 240, .reg = 0x46 },
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{ .mbps = 250, .reg = 0x08 },
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{ .mbps = 270, .reg = 0x28 },
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{ .mbps = 300, .reg = 0x0a },
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{ .mbps = 330, .reg = 0x2a },
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{ .mbps = 360, .reg = 0x4a },
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{ .mbps = 400, .reg = 0x0c },
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{ .mbps = 450, .reg = 0x2c },
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{ .mbps = 500, .reg = 0x0e },
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{ .mbps = 550, .reg = 0x2e },
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{ .mbps = 600, .reg = 0x10 },
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{ .mbps = 650, .reg = 0x30 },
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{ .mbps = 700, .reg = 0x12 },
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{ .mbps = 750, .reg = 0x32 },
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{ .mbps = 800, .reg = 0x52 },
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{ .mbps = 850, .reg = 0x72 },
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{ .mbps = 900, .reg = 0x14 },
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{ .mbps = 950, .reg = 0x34 },
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{ .mbps = 1000, .reg = 0x54 },
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{ .mbps = 1050, .reg = 0x74 },
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2018-05-14 20:56:35 -04:00
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{ .mbps = 1125, .reg = 0x16 },
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{ /* sentinel */ },
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};
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/* PHY Test Interface Clear */
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#define PHTC_REG 0x58
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#define PHTC_TESTCLR BIT(0)
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/* PHY Frequency Control */
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#define PHYPLL_REG 0x68
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#define PHYPLL_HSFREQRANGE(n) ((n) << 16)
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2021-06-12 10:46:29 +02:00
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static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = {
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{ .mbps = 80, .reg = 0x00 },
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{ .mbps = 90, .reg = 0x10 },
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{ .mbps = 100, .reg = 0x20 },
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{ .mbps = 110, .reg = 0x30 },
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{ .mbps = 120, .reg = 0x01 },
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{ .mbps = 130, .reg = 0x11 },
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{ .mbps = 140, .reg = 0x21 },
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{ .mbps = 150, .reg = 0x31 },
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{ .mbps = 160, .reg = 0x02 },
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{ .mbps = 170, .reg = 0x12 },
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{ .mbps = 180, .reg = 0x22 },
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{ .mbps = 190, .reg = 0x32 },
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{ .mbps = 205, .reg = 0x03 },
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{ .mbps = 220, .reg = 0x13 },
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{ .mbps = 235, .reg = 0x23 },
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{ .mbps = 250, .reg = 0x33 },
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{ .mbps = 275, .reg = 0x04 },
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{ .mbps = 300, .reg = 0x14 },
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{ .mbps = 325, .reg = 0x25 },
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{ .mbps = 350, .reg = 0x35 },
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{ .mbps = 400, .reg = 0x05 },
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{ .mbps = 450, .reg = 0x16 },
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{ .mbps = 500, .reg = 0x26 },
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{ .mbps = 550, .reg = 0x37 },
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{ .mbps = 600, .reg = 0x07 },
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{ .mbps = 650, .reg = 0x18 },
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{ .mbps = 700, .reg = 0x28 },
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{ .mbps = 750, .reg = 0x39 },
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{ .mbps = 800, .reg = 0x09 },
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{ .mbps = 850, .reg = 0x19 },
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{ .mbps = 900, .reg = 0x29 },
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{ .mbps = 950, .reg = 0x3a },
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{ .mbps = 1000, .reg = 0x0a },
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{ .mbps = 1050, .reg = 0x1a },
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{ .mbps = 1100, .reg = 0x2a },
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{ .mbps = 1150, .reg = 0x3b },
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{ .mbps = 1200, .reg = 0x0b },
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{ .mbps = 1250, .reg = 0x1b },
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{ .mbps = 1300, .reg = 0x2b },
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{ .mbps = 1350, .reg = 0x3c },
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{ .mbps = 1400, .reg = 0x0c },
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{ .mbps = 1450, .reg = 0x1c },
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{ .mbps = 1500, .reg = 0x2c },
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{ .mbps = 1550, .reg = 0x3d },
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{ .mbps = 1600, .reg = 0x0d },
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{ .mbps = 1650, .reg = 0x1d },
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{ .mbps = 1700, .reg = 0x2e },
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|
|
{ .mbps = 1750, .reg = 0x3e },
|
|
|
|
|
{ .mbps = 1800, .reg = 0x0e },
|
|
|
|
|
{ .mbps = 1850, .reg = 0x1e },
|
|
|
|
|
{ .mbps = 1900, .reg = 0x2f },
|
|
|
|
|
{ .mbps = 1950, .reg = 0x3f },
|
|
|
|
|
{ .mbps = 2000, .reg = 0x0f },
|
|
|
|
|
{ .mbps = 2050, .reg = 0x40 },
|
|
|
|
|
{ .mbps = 2100, .reg = 0x41 },
|
|
|
|
|
{ .mbps = 2150, .reg = 0x42 },
|
|
|
|
|
{ .mbps = 2200, .reg = 0x43 },
|
|
|
|
|
{ .mbps = 2300, .reg = 0x45 },
|
|
|
|
|
{ .mbps = 2350, .reg = 0x46 },
|
|
|
|
|
{ .mbps = 2400, .reg = 0x47 },
|
|
|
|
|
{ .mbps = 2450, .reg = 0x48 },
|
|
|
|
|
{ .mbps = 2500, .reg = 0x49 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
|
|
|
|
|
{ .mbps = 80, .reg = 0x00 },
|
|
|
|
|
{ .mbps = 90, .reg = 0x10 },
|
|
|
|
|
{ .mbps = 100, .reg = 0x20 },
|
|
|
|
|
{ .mbps = 110, .reg = 0x30 },
|
|
|
|
|
{ .mbps = 120, .reg = 0x01 },
|
|
|
|
|
{ .mbps = 130, .reg = 0x11 },
|
|
|
|
|
{ .mbps = 140, .reg = 0x21 },
|
|
|
|
|
{ .mbps = 150, .reg = 0x31 },
|
|
|
|
|
{ .mbps = 160, .reg = 0x02 },
|
|
|
|
|
{ .mbps = 170, .reg = 0x12 },
|
|
|
|
|
{ .mbps = 180, .reg = 0x22 },
|
|
|
|
|
{ .mbps = 190, .reg = 0x32 },
|
|
|
|
|
{ .mbps = 205, .reg = 0x03 },
|
|
|
|
|
{ .mbps = 220, .reg = 0x13 },
|
|
|
|
|
{ .mbps = 235, .reg = 0x23 },
|
|
|
|
|
{ .mbps = 250, .reg = 0x33 },
|
|
|
|
|
{ .mbps = 275, .reg = 0x04 },
|
|
|
|
|
{ .mbps = 300, .reg = 0x14 },
|
|
|
|
|
{ .mbps = 325, .reg = 0x25 },
|
|
|
|
|
{ .mbps = 350, .reg = 0x35 },
|
|
|
|
|
{ .mbps = 400, .reg = 0x05 },
|
|
|
|
|
{ .mbps = 450, .reg = 0x16 },
|
|
|
|
|
{ .mbps = 500, .reg = 0x26 },
|
|
|
|
|
{ .mbps = 550, .reg = 0x37 },
|
|
|
|
|
{ .mbps = 600, .reg = 0x07 },
|
|
|
|
|
{ .mbps = 650, .reg = 0x18 },
|
|
|
|
|
{ .mbps = 700, .reg = 0x28 },
|
|
|
|
|
{ .mbps = 750, .reg = 0x39 },
|
|
|
|
|
{ .mbps = 800, .reg = 0x09 },
|
|
|
|
|
{ .mbps = 850, .reg = 0x19 },
|
|
|
|
|
{ .mbps = 900, .reg = 0x29 },
|
|
|
|
|
{ .mbps = 950, .reg = 0x3a },
|
|
|
|
|
{ .mbps = 1000, .reg = 0x0a },
|
|
|
|
|
{ .mbps = 1050, .reg = 0x1a },
|
|
|
|
|
{ .mbps = 1100, .reg = 0x2a },
|
|
|
|
|
{ .mbps = 1150, .reg = 0x3b },
|
|
|
|
|
{ .mbps = 1200, .reg = 0x0b },
|
|
|
|
|
{ .mbps = 1250, .reg = 0x1b },
|
|
|
|
|
{ .mbps = 1300, .reg = 0x2b },
|
|
|
|
|
{ .mbps = 1350, .reg = 0x3c },
|
|
|
|
|
{ .mbps = 1400, .reg = 0x0c },
|
|
|
|
|
{ .mbps = 1450, .reg = 0x1c },
|
|
|
|
|
{ .mbps = 1500, .reg = 0x2c },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
|
|
|
|
|
{ .mbps = 80, .reg = 0x00 },
|
|
|
|
|
{ .mbps = 90, .reg = 0x10 },
|
|
|
|
|
{ .mbps = 100, .reg = 0x20 },
|
|
|
|
|
{ .mbps = 110, .reg = 0x30 },
|
|
|
|
|
{ .mbps = 120, .reg = 0x01 },
|
|
|
|
|
{ .mbps = 130, .reg = 0x11 },
|
|
|
|
|
{ .mbps = 140, .reg = 0x21 },
|
|
|
|
|
{ .mbps = 150, .reg = 0x31 },
|
|
|
|
|
{ .mbps = 160, .reg = 0x02 },
|
|
|
|
|
{ .mbps = 170, .reg = 0x12 },
|
|
|
|
|
{ .mbps = 180, .reg = 0x22 },
|
|
|
|
|
{ .mbps = 190, .reg = 0x32 },
|
|
|
|
|
{ .mbps = 205, .reg = 0x03 },
|
|
|
|
|
{ .mbps = 220, .reg = 0x13 },
|
|
|
|
|
{ .mbps = 235, .reg = 0x23 },
|
|
|
|
|
{ .mbps = 250, .reg = 0x33 },
|
|
|
|
|
{ .mbps = 275, .reg = 0x04 },
|
|
|
|
|
{ .mbps = 300, .reg = 0x14 },
|
|
|
|
|
{ .mbps = 325, .reg = 0x05 },
|
|
|
|
|
{ .mbps = 350, .reg = 0x15 },
|
|
|
|
|
{ .mbps = 400, .reg = 0x25 },
|
|
|
|
|
{ .mbps = 450, .reg = 0x06 },
|
|
|
|
|
{ .mbps = 500, .reg = 0x16 },
|
|
|
|
|
{ .mbps = 550, .reg = 0x07 },
|
|
|
|
|
{ .mbps = 600, .reg = 0x17 },
|
|
|
|
|
{ .mbps = 650, .reg = 0x08 },
|
|
|
|
|
{ .mbps = 700, .reg = 0x18 },
|
|
|
|
|
{ .mbps = 750, .reg = 0x09 },
|
|
|
|
|
{ .mbps = 800, .reg = 0x19 },
|
|
|
|
|
{ .mbps = 850, .reg = 0x29 },
|
|
|
|
|
{ .mbps = 900, .reg = 0x39 },
|
|
|
|
|
{ .mbps = 950, .reg = 0x0a },
|
|
|
|
|
{ .mbps = 1000, .reg = 0x1a },
|
|
|
|
|
{ .mbps = 1050, .reg = 0x2a },
|
|
|
|
|
{ .mbps = 1100, .reg = 0x3a },
|
|
|
|
|
{ .mbps = 1150, .reg = 0x0b },
|
|
|
|
|
{ .mbps = 1200, .reg = 0x1b },
|
|
|
|
|
{ .mbps = 1250, .reg = 0x2b },
|
|
|
|
|
{ .mbps = 1300, .reg = 0x3b },
|
|
|
|
|
{ .mbps = 1350, .reg = 0x0c },
|
|
|
|
|
{ .mbps = 1400, .reg = 0x1c },
|
|
|
|
|
{ .mbps = 1450, .reg = 0x2c },
|
|
|
|
|
{ .mbps = 1500, .reg = 0x3c },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* PHY ESC Error Monitor */
|
|
|
|
|
#define PHEERM_REG 0x74
|
|
|
|
|
|
|
|
|
|
/* PHY Clock Lane Monitor */
|
|
|
|
|
#define PHCLM_REG 0x78
|
|
|
|
|
#define PHCLM_STOPSTATECKL BIT(0)
|
|
|
|
|
|
|
|
|
|
/* PHY Data Lane Monitor */
|
|
|
|
|
#define PHDLM_REG 0x7c
|
|
|
|
|
|
|
|
|
|
/* CSI0CLK Frequency Configuration Preset Register */
|
|
|
|
|
#define CSI0CLKFCPR_REG 0x260
|
|
|
|
|
#define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
|
|
|
|
|
|
|
|
|
|
struct rcar_csi2_format {
|
|
|
|
|
u32 code;
|
|
|
|
|
unsigned int datatype;
|
|
|
|
|
unsigned int bpp;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rcar_csi2_format rcar_csi2_formats[] = {
|
2022-01-23 16:58:17 +01:00
|
|
|
{
|
|
|
|
|
.code = MEDIA_BUS_FMT_RGB888_1X24,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RGB888,
|
|
|
|
|
.bpp = 24,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_UYVY8_1X16,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_YUV422_8B,
|
|
|
|
|
.bpp = 16,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_YUYV8_1X16,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_YUV422_8B,
|
|
|
|
|
.bpp = 16,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_UYVY8_2X8,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_YUV422_8B,
|
|
|
|
|
.bpp = 16,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_YUYV10_2X10,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_YUV422_8B,
|
|
|
|
|
.bpp = 20,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_Y10_1X10,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RAW10,
|
|
|
|
|
.bpp = 10,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_SBGGR8_1X8,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RAW8,
|
|
|
|
|
.bpp = 8,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_SGBRG8_1X8,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RAW8,
|
|
|
|
|
.bpp = 8,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_SGRBG8_1X8,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RAW8,
|
|
|
|
|
.bpp = 8,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_SRGGB8_1X8,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RAW8,
|
|
|
|
|
.bpp = 8,
|
|
|
|
|
}, {
|
|
|
|
|
.code = MEDIA_BUS_FMT_Y8_1X8,
|
|
|
|
|
.datatype = MIPI_CSI2_DT_RAW8,
|
|
|
|
|
.bpp = 8,
|
|
|
|
|
},
|
2018-05-14 20:56:35 -04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
|
|
|
|
|
if (rcar_csi2_formats[i].code == code)
|
|
|
|
|
return &rcar_csi2_formats[i];
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
enum rcar_csi2_pads {
|
|
|
|
|
RCAR_CSI2_SINK,
|
|
|
|
|
RCAR_CSI2_SOURCE_VC0,
|
|
|
|
|
RCAR_CSI2_SOURCE_VC1,
|
|
|
|
|
RCAR_CSI2_SOURCE_VC2,
|
|
|
|
|
RCAR_CSI2_SOURCE_VC3,
|
|
|
|
|
NR_OF_RCAR_CSI2_PAD,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct rcar_csi2_info {
|
|
|
|
|
int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
|
2020-06-11 21:32:32 +02:00
|
|
|
int (*phy_post_init)(struct rcar_csi2 *priv);
|
2018-05-14 20:56:35 -04:00
|
|
|
const struct rcsi2_mbps_reg *hsfreqrange;
|
|
|
|
|
unsigned int csi0clkfreqrange;
|
2018-11-06 05:54:27 -05:00
|
|
|
unsigned int num_channels;
|
2018-05-14 20:56:35 -04:00
|
|
|
bool clear_ulps;
|
2021-06-12 10:46:29 +02:00
|
|
|
bool use_isp;
|
2018-05-14 20:56:35 -04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct rcar_csi2 {
|
|
|
|
|
struct device *dev;
|
|
|
|
|
void __iomem *base;
|
|
|
|
|
const struct rcar_csi2_info *info;
|
2019-03-12 19:49:30 -04:00
|
|
|
struct reset_control *rstc;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
struct v4l2_subdev subdev;
|
|
|
|
|
struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
|
|
|
|
|
|
|
|
|
|
struct v4l2_async_notifier notifier;
|
|
|
|
|
struct v4l2_subdev *remote;
|
2020-07-17 16:53:24 +02:00
|
|
|
unsigned int remote_pad;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
media: rcar-{csi2,vin}: Move to full Virtual Channel routing per CSI-2 IP
When Gen3 support was first added to this R-Car VIN and CSI-2 driver the
routing was centred around the CHSEL register which multiplexes the
different parallel buses that sit between the CSI-2 receivers source
side and the VIN dma engines. This was a bad design as the multiplexing
do allow for only a few combinations and do not play nice with many
video streams in the system.
For example it's only possible for CSI-2 Virtual Channels 0 and 1 of any
given CSI-2 receiver to be used together with the scaler.
Later datasheets have expanded the documentation and it is now possible
to improve on this design by allowing any Virtual Channel to be routed
to any R-Car VIN instance, provided that there exists a parallel bus
between them. This increases the flexibility as all Virtual Channels can
now be used together with the scaler for example.
The redesign is not however perfect. While the new design allows for
many more routes, two constrains limit a small portion of routes that
was possible in the old design but are no more.
- It is no longer possible to route the same CSI-2 and VC to more then
one VIN at a time. This was theoretically possible before if the
specific SoC allowed for the same CSI-2 and VC to be routed to two
different VIN capture groups.
- It is no longer possible to simultaneously mix links from two CSI-2 IP
blocks to the same VIN capture group.
For example if VIN2 is capturing from CSI40 then VIN{0,1,3} must also
capture from CSI40. While VIN{4,5,6,7} is still free to capture from
any other CSI-2 IP in the system. Once all VIN{0,1,2,3} links to CSI40
are disabled that VIN capture group is free again to capture from any
other CSI-2 IP it is connected to.
At the core of the redesign is greater cooperator of the R-Car VIN and
CSI-2 drivers in configuring the routing. The VIN driver is after this
change only responsible to configure the full VIN capture groups
parallel buses to be to a particular CSI-2 IP. While the configuration
of which CSI-2 Virtual Channel is outputted on which of the R-Car CSI-2
IP output ports is handled by the CSI-2 driver.
Before this change the CSI-2 Virtual Channel to output port was static
in the CSI-2 driver and the different links only manipulated the VIN
capture groups CHSEL register. With this change both the CHSEl register
and the CSI-2 routing VCDT registers are modified for greater
flexibility.
This change touches both the R-Car VIN and R-Car CSI-2 drivers in the
same commit as both drivers cooperate closely and one change without the
other would more or less break video capture.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: fix two trivial checkpatch whitespace issues]
2022-01-24 13:48:58 +01:00
|
|
|
int channel_vc[4];
|
|
|
|
|
|
2021-09-15 03:50:13 +02:00
|
|
|
struct mutex lock; /* Protects mf and stream_count. */
|
2018-05-14 20:56:35 -04:00
|
|
|
struct v4l2_mbus_framefmt mf;
|
|
|
|
|
int stream_count;
|
|
|
|
|
|
|
|
|
|
unsigned short lanes;
|
|
|
|
|
unsigned char lane_swap[4];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
|
|
|
|
|
{
|
|
|
|
|
return container_of(sd, struct rcar_csi2, subdev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
|
|
|
|
|
{
|
|
|
|
|
return container_of(n, struct rcar_csi2, notifier);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
|
|
|
|
|
{
|
|
|
|
|
return ioread32(priv->base + reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
|
|
|
|
|
{
|
|
|
|
|
iowrite32(data, priv->base + reg);
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-12 19:49:30 -04:00
|
|
|
static void rcsi2_enter_standby(struct rcar_csi2 *priv)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
2019-03-12 19:49:30 -04:00
|
|
|
rcsi2_write(priv, PHYCNT_REG, 0);
|
|
|
|
|
rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
|
|
|
|
|
reset_control_assert(priv->rstc);
|
2018-05-14 20:56:35 -04:00
|
|
|
usleep_range(100, 150);
|
2019-03-12 19:49:30 -04:00
|
|
|
pm_runtime_put(priv->dev);
|
|
|
|
|
}
|
|
|
|
|
|
2021-04-23 17:19:20 +02:00
|
|
|
static int rcsi2_exit_standby(struct rcar_csi2 *priv)
|
2019-03-12 19:49:30 -04:00
|
|
|
{
|
2021-04-23 17:19:20 +02:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = pm_runtime_resume_and_get(priv->dev);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2019-03-12 19:49:30 -04:00
|
|
|
reset_control_deassert(priv->rstc);
|
2021-04-23 17:19:20 +02:00
|
|
|
|
|
|
|
|
return 0;
|
2018-05-14 20:56:35 -04:00
|
|
|
}
|
|
|
|
|
|
2020-07-17 16:53:24 +02:00
|
|
|
static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
|
|
|
|
|
unsigned int lanes)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
unsigned int timeout;
|
|
|
|
|
|
|
|
|
|
/* Wait for the clock and data lanes to enter LP-11 state. */
|
|
|
|
|
for (timeout = 0; timeout <= 20; timeout++) {
|
2020-07-17 16:53:24 +02:00
|
|
|
const u32 lane_mask = (1 << lanes) - 1;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
|
|
|
|
|
(rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
|
|
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
|
|
|
|
|
{
|
|
|
|
|
const struct rcsi2_mbps_reg *hsfreq;
|
2021-08-13 17:07:54 +02:00
|
|
|
const struct rcsi2_mbps_reg *hsfreq_prev = NULL;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2021-08-13 17:07:55 +02:00
|
|
|
if (mbps < priv->info->hsfreqrange->mbps)
|
|
|
|
|
dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps",
|
|
|
|
|
mbps, priv->info->hsfreqrange->mbps);
|
|
|
|
|
|
2021-08-13 17:07:54 +02:00
|
|
|
for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) {
|
2018-05-14 20:56:35 -04:00
|
|
|
if (hsfreq->mbps >= mbps)
|
|
|
|
|
break;
|
2021-08-13 17:07:54 +02:00
|
|
|
hsfreq_prev = hsfreq;
|
|
|
|
|
}
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
if (!hsfreq->mbps) {
|
|
|
|
|
dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
|
|
|
|
|
return -ERANGE;
|
|
|
|
|
}
|
|
|
|
|
|
2021-08-13 17:07:54 +02:00
|
|
|
if (hsfreq_prev &&
|
|
|
|
|
((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps)))
|
|
|
|
|
hsfreq = hsfreq_prev;
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-17 16:53:24 +02:00
|
|
|
static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
|
|
|
|
|
unsigned int lanes)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
struct v4l2_subdev *source;
|
|
|
|
|
struct v4l2_ctrl *ctrl;
|
|
|
|
|
u64 mbps;
|
|
|
|
|
|
|
|
|
|
if (!priv->remote)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
source = priv->remote;
|
|
|
|
|
|
|
|
|
|
/* Read the pixel rate control from remote. */
|
|
|
|
|
ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
|
|
|
|
|
if (!ctrl) {
|
|
|
|
|
dev_err(priv->dev, "no pixel rate control in subdev %s\n",
|
|
|
|
|
source->name);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Calculate the phypll in mbps.
|
|
|
|
|
* link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
|
|
|
|
|
* bps = link_freq * 2
|
|
|
|
|
*/
|
|
|
|
|
mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
|
2020-07-17 16:53:24 +02:00
|
|
|
do_div(mbps, lanes * 1000000);
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
return mbps;
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-17 16:53:24 +02:00
|
|
|
static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
|
|
|
|
|
unsigned int *lanes)
|
|
|
|
|
{
|
|
|
|
|
struct v4l2_mbus_config mbus_config = { 0 };
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
*lanes = priv->lanes;
|
|
|
|
|
|
|
|
|
|
ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
|
|
|
|
|
priv->remote_pad, &mbus_config);
|
|
|
|
|
if (ret == -ENOIOCTLCMD) {
|
|
|
|
|
dev_dbg(priv->dev, "No remote mbus configuration available\n");
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(priv->dev, "Failed to get remote mbus configuration\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
|
|
|
|
|
dev_err(priv->dev, "Unsupported media bus type %u\n",
|
|
|
|
|
mbus_config.type);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2022-01-03 17:24:11 +01:00
|
|
|
if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) {
|
2020-07-17 16:53:24 +02:00
|
|
|
dev_err(priv->dev,
|
|
|
|
|
"Unsupported mbus config: too many data lanes %u\n",
|
2022-01-03 17:24:11 +01:00
|
|
|
mbus_config.bus.mipi_csi2.num_data_lanes);
|
2020-07-17 16:53:24 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2022-01-03 17:24:11 +01:00
|
|
|
*lanes = mbus_config.bus.mipi_csi2.num_data_lanes;
|
2020-07-17 16:53:24 +02:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-12 19:49:30 -04:00
|
|
|
static int rcsi2_start_receiver(struct rcar_csi2 *priv)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
const struct rcar_csi2_format *format;
|
2019-04-11 16:34:44 -04:00
|
|
|
u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
|
2020-07-17 16:53:24 +02:00
|
|
|
unsigned int lanes;
|
2018-05-14 20:56:35 -04:00
|
|
|
unsigned int i;
|
|
|
|
|
int mbps, ret;
|
|
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
|
|
|
|
|
priv->mf.width, priv->mf.height,
|
|
|
|
|
priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
|
|
|
|
|
|
|
|
|
|
/* Code is validated in set_fmt. */
|
|
|
|
|
format = rcsi2_code_to_fmt(priv->mf.code);
|
2021-08-11 19:18:16 +02:00
|
|
|
if (!format)
|
|
|
|
|
return -EINVAL;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
/*
|
2018-11-06 05:54:27 -05:00
|
|
|
* Enable all supported CSI-2 channels with virtual channel and
|
|
|
|
|
* data type matching.
|
2018-05-14 20:56:35 -04:00
|
|
|
*
|
|
|
|
|
* NOTE: It's not possible to get individual datatype for each
|
|
|
|
|
* source virtual channel. Once this is possible in V4L2
|
|
|
|
|
* it should be used here.
|
|
|
|
|
*/
|
2018-11-06 05:54:27 -05:00
|
|
|
for (i = 0; i < priv->info->num_channels; i++) {
|
2018-05-14 20:56:35 -04:00
|
|
|
u32 vcdt_part;
|
|
|
|
|
|
media: rcar-{csi2,vin}: Move to full Virtual Channel routing per CSI-2 IP
When Gen3 support was first added to this R-Car VIN and CSI-2 driver the
routing was centred around the CHSEL register which multiplexes the
different parallel buses that sit between the CSI-2 receivers source
side and the VIN dma engines. This was a bad design as the multiplexing
do allow for only a few combinations and do not play nice with many
video streams in the system.
For example it's only possible for CSI-2 Virtual Channels 0 and 1 of any
given CSI-2 receiver to be used together with the scaler.
Later datasheets have expanded the documentation and it is now possible
to improve on this design by allowing any Virtual Channel to be routed
to any R-Car VIN instance, provided that there exists a parallel bus
between them. This increases the flexibility as all Virtual Channels can
now be used together with the scaler for example.
The redesign is not however perfect. While the new design allows for
many more routes, two constrains limit a small portion of routes that
was possible in the old design but are no more.
- It is no longer possible to route the same CSI-2 and VC to more then
one VIN at a time. This was theoretically possible before if the
specific SoC allowed for the same CSI-2 and VC to be routed to two
different VIN capture groups.
- It is no longer possible to simultaneously mix links from two CSI-2 IP
blocks to the same VIN capture group.
For example if VIN2 is capturing from CSI40 then VIN{0,1,3} must also
capture from CSI40. While VIN{4,5,6,7} is still free to capture from
any other CSI-2 IP in the system. Once all VIN{0,1,2,3} links to CSI40
are disabled that VIN capture group is free again to capture from any
other CSI-2 IP it is connected to.
At the core of the redesign is greater cooperator of the R-Car VIN and
CSI-2 drivers in configuring the routing. The VIN driver is after this
change only responsible to configure the full VIN capture groups
parallel buses to be to a particular CSI-2 IP. While the configuration
of which CSI-2 Virtual Channel is outputted on which of the R-Car CSI-2
IP output ports is handled by the CSI-2 driver.
Before this change the CSI-2 Virtual Channel to output port was static
in the CSI-2 driver and the different links only manipulated the VIN
capture groups CHSEL register. With this change both the CHSEl register
and the CSI-2 routing VCDT registers are modified for greater
flexibility.
This change touches both the R-Car VIN and R-Car CSI-2 drivers in the
same commit as both drivers cooperate closely and one change without the
other would more or less break video capture.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: fix two trivial checkpatch whitespace issues]
2022-01-24 13:48:58 +01:00
|
|
|
if (priv->channel_vc[i] < 0)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN |
|
|
|
|
|
VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype);
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
/* Store in correct reg and offset. */
|
|
|
|
|
if (i < 2)
|
|
|
|
|
vcdt |= vcdt_part << ((i % 2) * 16);
|
|
|
|
|
else
|
|
|
|
|
vcdt2 |= vcdt_part << ((i % 2) * 16);
|
|
|
|
|
}
|
|
|
|
|
|
2019-04-11 16:34:44 -04:00
|
|
|
if (priv->mf.field == V4L2_FIELD_ALTERNATE) {
|
|
|
|
|
fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
|
|
|
|
|
| FLD_FLD_EN;
|
|
|
|
|
|
|
|
|
|
if (priv->mf.height == 240)
|
|
|
|
|
fld |= FLD_FLD_NUM(0);
|
|
|
|
|
else
|
|
|
|
|
fld |= FLD_FLD_NUM(1);
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-17 16:53:24 +02:00
|
|
|
/*
|
|
|
|
|
* Get the number of active data lanes inspecting the remote mbus
|
|
|
|
|
* configuration.
|
|
|
|
|
*/
|
|
|
|
|
ret = rcsi2_get_active_lanes(priv, &lanes);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
phycnt = PHYCNT_ENABLECLK;
|
2020-07-17 16:53:24 +02:00
|
|
|
phycnt |= (1 << lanes) - 1;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2020-07-17 16:53:24 +02:00
|
|
|
mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
|
2018-05-14 20:56:35 -04:00
|
|
|
if (mbps < 0)
|
|
|
|
|
return mbps;
|
|
|
|
|
|
2019-04-11 16:30:58 -04:00
|
|
|
/* Enable interrupts. */
|
|
|
|
|
rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
|
|
|
|
|
| INTEN_INT_ERRSOTSYNCHS);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
/* Init */
|
|
|
|
|
rcsi2_write(priv, TREF_REG, TREF_TREF);
|
|
|
|
|
rcsi2_write(priv, PHTC_REG, 0);
|
|
|
|
|
|
|
|
|
|
/* Configure */
|
2021-06-12 10:46:29 +02:00
|
|
|
if (!priv->info->use_isp) {
|
|
|
|
|
rcsi2_write(priv, VCDT_REG, vcdt);
|
|
|
|
|
if (vcdt2)
|
|
|
|
|
rcsi2_write(priv, VCDT2_REG, vcdt2);
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
/* Lanes are zero indexed. */
|
|
|
|
|
rcsi2_write(priv, LSWAP_REG,
|
|
|
|
|
LSWAP_L0SEL(priv->lane_swap[0] - 1) |
|
|
|
|
|
LSWAP_L1SEL(priv->lane_swap[1] - 1) |
|
|
|
|
|
LSWAP_L2SEL(priv->lane_swap[2] - 1) |
|
|
|
|
|
LSWAP_L3SEL(priv->lane_swap[3] - 1));
|
|
|
|
|
|
|
|
|
|
/* Start */
|
|
|
|
|
if (priv->info->init_phtw) {
|
|
|
|
|
ret = priv->info->init_phtw(priv, mbps);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (priv->info->hsfreqrange) {
|
|
|
|
|
ret = rcsi2_set_phypll(priv, mbps);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (priv->info->csi0clkfreqrange)
|
|
|
|
|
rcsi2_write(priv, CSI0CLKFCPR_REG,
|
|
|
|
|
CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
|
|
|
|
|
|
2021-06-12 10:46:29 +02:00
|
|
|
if (priv->info->use_isp)
|
|
|
|
|
rcsi2_write(priv, PHYFRX_REG,
|
|
|
|
|
PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 |
|
|
|
|
|
PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
rcsi2_write(priv, PHYCNT_REG, phycnt);
|
|
|
|
|
rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
|
|
|
|
|
LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
|
2019-04-11 16:34:44 -04:00
|
|
|
rcsi2_write(priv, FLD_REG, fld);
|
2018-05-14 20:56:35 -04:00
|
|
|
rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
|
|
|
|
|
rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
|
|
|
|
|
|
2020-07-17 16:53:24 +02:00
|
|
|
ret = rcsi2_wait_phy_start(priv, lanes);
|
2018-05-14 20:56:35 -04:00
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2021-06-12 10:46:29 +02:00
|
|
|
if (priv->info->use_isp)
|
|
|
|
|
rcsi2_write(priv, PHYFRX_REG, 0);
|
|
|
|
|
|
2020-06-11 21:32:32 +02:00
|
|
|
/* Run post PHY start initialization, if needed. */
|
|
|
|
|
if (priv->info->phy_post_init) {
|
|
|
|
|
ret = priv->info->phy_post_init(priv);
|
2018-07-26 18:36:57 -04:00
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
/* Clear Ultra Low Power interrupt. */
|
|
|
|
|
if (priv->info->clear_ulps)
|
|
|
|
|
rcsi2_write(priv, INTSTATE_REG,
|
|
|
|
|
INTSTATE_INT_ULPS_START |
|
|
|
|
|
INTSTATE_INT_ULPS_END);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-12 19:49:30 -04:00
|
|
|
static int rcsi2_start(struct rcar_csi2 *priv)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
2019-03-12 19:49:30 -04:00
|
|
|
int ret;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2021-04-23 17:19:20 +02:00
|
|
|
ret = rcsi2_exit_standby(priv);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2019-03-12 19:49:30 -04:00
|
|
|
ret = rcsi2_start_receiver(priv);
|
|
|
|
|
if (ret) {
|
|
|
|
|
rcsi2_enter_standby(priv);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
|
|
|
|
|
if (ret) {
|
|
|
|
|
rcsi2_enter_standby(priv);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rcsi2_stop(struct rcar_csi2 *priv)
|
|
|
|
|
{
|
|
|
|
|
rcsi2_enter_standby(priv);
|
|
|
|
|
v4l2_subdev_call(priv->remote, video, s_stream, 0);
|
2018-05-14 20:56:35 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = sd_to_csi2(sd);
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&priv->lock);
|
|
|
|
|
|
|
|
|
|
if (!priv->remote) {
|
|
|
|
|
ret = -ENODEV;
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (enable && priv->stream_count == 0) {
|
|
|
|
|
ret = rcsi2_start(priv);
|
2019-03-12 19:49:30 -04:00
|
|
|
if (ret)
|
2018-05-14 20:56:35 -04:00
|
|
|
goto out;
|
|
|
|
|
} else if (!enable && priv->stream_count == 1) {
|
|
|
|
|
rcsi2_stop(priv);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->stream_count += enable ? 1 : -1;
|
|
|
|
|
out:
|
|
|
|
|
mutex_unlock(&priv->lock);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
|
media: v4l2-subdev: add subdev-wide state struct
We have 'struct v4l2_subdev_pad_config' which contains configuration for
a single pad used for the TRY functionality, and an array of those
structs is passed to various v4l2_subdev_pad_ops.
I was working on subdev internal routing between pads, and realized that
there's no way to add TRY functionality for routes, which is not pad
specific configuration. Adding a separate struct for try-route config
wouldn't work either, as e.g. set-fmt needs to know the try-route
configuration to propagate the settings.
This patch adds a new struct, 'struct v4l2_subdev_state' (which at the
moment only contains the v4l2_subdev_pad_config array) and the new
struct is used in most of the places where v4l2_subdev_pad_config was
used. All v4l2_subdev_pad_ops functions taking v4l2_subdev_pad_config
are changed to instead take v4l2_subdev_state.
The changes to drivers/media/v4l2-core/v4l2-subdev.c and
include/media/v4l2-subdev.h were written by hand, and all the driver
changes were done with the semantic patch below. The spatch needs to be
applied to a select list of directories. I used the following shell
commands to apply the spatch:
dirs="drivers/media/i2c drivers/media/platform drivers/media/usb drivers/media/test-drivers/vimc drivers/media/pci drivers/staging/media"
for dir in $dirs; do spatch -j8 --dir --include-headers --no-show-diff --in-place --sp-file v4l2-subdev-state.cocci $dir; done
Note that Coccinelle chokes on a few drivers (gcc extensions?). With
minor changes we can make Coccinelle run fine, and these changes can be
reverted after spatch. The diff for these changes is:
For drivers/media/i2c/s5k5baf.c:
@@ -1481,7 +1481,7 @@ static int s5k5baf_set_selection(struct v4l2_subdev *sd,
&s5k5baf_cis_rect,
v4l2_subdev_get_try_crop(sd, cfg, PAD_CIS),
v4l2_subdev_get_try_compose(sd, cfg, PAD_CIS),
- v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT)
+ v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT),
};
s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
return 0;
For drivers/media/platform/s3c-camif/camif-capture.c:
@@ -1230,7 +1230,7 @@ static int s3c_camif_subdev_get_fmt(struct v4l2_subdev *sd,
*mf = camif->mbus_fmt;
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* crop rectangle at camera interface input */
mf->width = camif->camif_crop.width;
mf->height = camif->camif_crop.height;
@@ -1332,7 +1332,7 @@ static int s3c_camif_subdev_set_fmt(struct v4l2_subdev *sd,
}
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* Pixel format can be only changed on the sink pad. */
mf->code = camif->mbus_fmt.code;
mf->width = crop->width;
The semantic patch is:
// <smpl>
// Change function parameter
@@
identifier func;
identifier cfg;
@@
func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...)
{
<...
- cfg
+ sd_state
...>
}
// Change function declaration parameter
@@
identifier func;
identifier cfg;
type T;
@@
T func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...);
// Change function return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...)
{
...
}
// Change function declaration return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...);
// Some drivers pass a local pad_cfg for a single pad to a called function. Wrap it
// inside a pad_state.
@@
identifier func;
identifier pad_cfg;
@@
func(...)
{
...
struct v4l2_subdev_pad_config pad_cfg;
+ struct v4l2_subdev_state pad_state = { .pads = &pad_cfg };
<+...
(
v4l2_subdev_call
|
sensor_call
|
isi_try_fse
|
isc_try_fse
|
saa_call_all
)
(...,
- &pad_cfg
+ &pad_state
,...)
...+>
}
// If the function uses fields from pad_config, access via state->pads
@@
identifier func;
identifier state;
@@
func(...,
struct v4l2_subdev_state *state
, ...)
{
<...
(
- state->try_fmt
+ state->pads->try_fmt
|
- state->try_crop
+ state->pads->try_crop
|
- state->try_compose
+ state->pads->try_compose
)
...>
}
// If the function accesses the filehandle, use fh->state instead
@@
struct v4l2_subdev_fh *fh;
@@
- fh->pad
+ fh->state
@@
struct v4l2_subdev_fh fh;
@@
- fh.pad
+ fh.state
// Start of vsp1 specific
@@
@@
struct vsp1_entity {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
};
@@
symbol entity;
@@
vsp1_entity_init(...)
{
...
entity->config =
- v4l2_subdev_alloc_pad_config
+ v4l2_subdev_alloc_state
(&entity->subdev);
...
}
@@
symbol entity;
@@
vsp1_entity_destroy(...)
{
...
- v4l2_subdev_free_pad_config
+ v4l2_subdev_free_state
(entity->config);
...
}
@exists@
identifier func =~ "(^vsp1.*)|(hsit_set_format)|(sru_enum_frame_size)|(sru_set_format)|(uif_get_selection)|(uif_set_selection)|(uds_enum_frame_size)|(uds_set_format)|(brx_set_format)|(brx_get_selection)|(histo_get_selection)|(histo_set_selection)|(brx_set_selection)";
symbol config;
@@
func(...) {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
}
// End of vsp1 specific
// Start of rcar specific
@@
identifier sd;
identifier pad_cfg;
@@
rvin_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
// End of rcar specific
// Start of rockchip specific
@@
identifier func =~ "(rkisp1_rsz_get_pad_fmt)|(rkisp1_rsz_get_pad_crop)|(rkisp1_rsz_register)";
symbol rsz;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = rsz->pad_cfg };
...
- rsz->pad_cfg
+ &state
...
}
@@
identifier func =~ "(rkisp1_isp_get_pad_fmt)|(rkisp1_isp_get_pad_crop)";
symbol isp;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = isp->pad_cfg };
...
- isp->pad_cfg
+ &state
...
}
@@
symbol rkisp1;
symbol isp;
symbol pad_cfg;
@@
rkisp1_isp_register(...)
{
+ struct v4l2_subdev_state state = { .pads = rkisp1->isp.pad_cfg };
...
- rkisp1->isp.pad_cfg
+ &state
...
}
// End of rockchip specific
// Start of tegra-video specific
@@
identifier sd;
identifier pad_cfg;
@@
__tegra_channel_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
@@
identifier sd_state;
@@
__tegra_channel_try_format(...)
{
...
struct v4l2_subdev_state *sd_state;
<...
- sd_state->try_crop
+ sd_state->pads->try_crop
...>
}
// End of tegra-video specific
// </smpl>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-10 17:55:58 +03:00
|
|
|
struct v4l2_subdev_state *sd_state,
|
2018-05-14 20:56:35 -04:00
|
|
|
struct v4l2_subdev_format *format)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = sd_to_csi2(sd);
|
|
|
|
|
struct v4l2_mbus_framefmt *framefmt;
|
|
|
|
|
|
2021-09-15 03:50:13 +02:00
|
|
|
mutex_lock(&priv->lock);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
if (!rcsi2_code_to_fmt(format->format.code))
|
2018-05-16 19:04:33 -04:00
|
|
|
format->format.code = rcar_csi2_formats[0].code;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
|
|
|
|
|
priv->mf = format->format;
|
|
|
|
|
} else {
|
media: v4l2-subdev: add subdev-wide state struct
We have 'struct v4l2_subdev_pad_config' which contains configuration for
a single pad used for the TRY functionality, and an array of those
structs is passed to various v4l2_subdev_pad_ops.
I was working on subdev internal routing between pads, and realized that
there's no way to add TRY functionality for routes, which is not pad
specific configuration. Adding a separate struct for try-route config
wouldn't work either, as e.g. set-fmt needs to know the try-route
configuration to propagate the settings.
This patch adds a new struct, 'struct v4l2_subdev_state' (which at the
moment only contains the v4l2_subdev_pad_config array) and the new
struct is used in most of the places where v4l2_subdev_pad_config was
used. All v4l2_subdev_pad_ops functions taking v4l2_subdev_pad_config
are changed to instead take v4l2_subdev_state.
The changes to drivers/media/v4l2-core/v4l2-subdev.c and
include/media/v4l2-subdev.h were written by hand, and all the driver
changes were done with the semantic patch below. The spatch needs to be
applied to a select list of directories. I used the following shell
commands to apply the spatch:
dirs="drivers/media/i2c drivers/media/platform drivers/media/usb drivers/media/test-drivers/vimc drivers/media/pci drivers/staging/media"
for dir in $dirs; do spatch -j8 --dir --include-headers --no-show-diff --in-place --sp-file v4l2-subdev-state.cocci $dir; done
Note that Coccinelle chokes on a few drivers (gcc extensions?). With
minor changes we can make Coccinelle run fine, and these changes can be
reverted after spatch. The diff for these changes is:
For drivers/media/i2c/s5k5baf.c:
@@ -1481,7 +1481,7 @@ static int s5k5baf_set_selection(struct v4l2_subdev *sd,
&s5k5baf_cis_rect,
v4l2_subdev_get_try_crop(sd, cfg, PAD_CIS),
v4l2_subdev_get_try_compose(sd, cfg, PAD_CIS),
- v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT)
+ v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT),
};
s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
return 0;
For drivers/media/platform/s3c-camif/camif-capture.c:
@@ -1230,7 +1230,7 @@ static int s3c_camif_subdev_get_fmt(struct v4l2_subdev *sd,
*mf = camif->mbus_fmt;
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* crop rectangle at camera interface input */
mf->width = camif->camif_crop.width;
mf->height = camif->camif_crop.height;
@@ -1332,7 +1332,7 @@ static int s3c_camif_subdev_set_fmt(struct v4l2_subdev *sd,
}
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* Pixel format can be only changed on the sink pad. */
mf->code = camif->mbus_fmt.code;
mf->width = crop->width;
The semantic patch is:
// <smpl>
// Change function parameter
@@
identifier func;
identifier cfg;
@@
func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...)
{
<...
- cfg
+ sd_state
...>
}
// Change function declaration parameter
@@
identifier func;
identifier cfg;
type T;
@@
T func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...);
// Change function return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...)
{
...
}
// Change function declaration return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...);
// Some drivers pass a local pad_cfg for a single pad to a called function. Wrap it
// inside a pad_state.
@@
identifier func;
identifier pad_cfg;
@@
func(...)
{
...
struct v4l2_subdev_pad_config pad_cfg;
+ struct v4l2_subdev_state pad_state = { .pads = &pad_cfg };
<+...
(
v4l2_subdev_call
|
sensor_call
|
isi_try_fse
|
isc_try_fse
|
saa_call_all
)
(...,
- &pad_cfg
+ &pad_state
,...)
...+>
}
// If the function uses fields from pad_config, access via state->pads
@@
identifier func;
identifier state;
@@
func(...,
struct v4l2_subdev_state *state
, ...)
{
<...
(
- state->try_fmt
+ state->pads->try_fmt
|
- state->try_crop
+ state->pads->try_crop
|
- state->try_compose
+ state->pads->try_compose
)
...>
}
// If the function accesses the filehandle, use fh->state instead
@@
struct v4l2_subdev_fh *fh;
@@
- fh->pad
+ fh->state
@@
struct v4l2_subdev_fh fh;
@@
- fh.pad
+ fh.state
// Start of vsp1 specific
@@
@@
struct vsp1_entity {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
};
@@
symbol entity;
@@
vsp1_entity_init(...)
{
...
entity->config =
- v4l2_subdev_alloc_pad_config
+ v4l2_subdev_alloc_state
(&entity->subdev);
...
}
@@
symbol entity;
@@
vsp1_entity_destroy(...)
{
...
- v4l2_subdev_free_pad_config
+ v4l2_subdev_free_state
(entity->config);
...
}
@exists@
identifier func =~ "(^vsp1.*)|(hsit_set_format)|(sru_enum_frame_size)|(sru_set_format)|(uif_get_selection)|(uif_set_selection)|(uds_enum_frame_size)|(uds_set_format)|(brx_set_format)|(brx_get_selection)|(histo_get_selection)|(histo_set_selection)|(brx_set_selection)";
symbol config;
@@
func(...) {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
}
// End of vsp1 specific
// Start of rcar specific
@@
identifier sd;
identifier pad_cfg;
@@
rvin_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
// End of rcar specific
// Start of rockchip specific
@@
identifier func =~ "(rkisp1_rsz_get_pad_fmt)|(rkisp1_rsz_get_pad_crop)|(rkisp1_rsz_register)";
symbol rsz;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = rsz->pad_cfg };
...
- rsz->pad_cfg
+ &state
...
}
@@
identifier func =~ "(rkisp1_isp_get_pad_fmt)|(rkisp1_isp_get_pad_crop)";
symbol isp;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = isp->pad_cfg };
...
- isp->pad_cfg
+ &state
...
}
@@
symbol rkisp1;
symbol isp;
symbol pad_cfg;
@@
rkisp1_isp_register(...)
{
+ struct v4l2_subdev_state state = { .pads = rkisp1->isp.pad_cfg };
...
- rkisp1->isp.pad_cfg
+ &state
...
}
// End of rockchip specific
// Start of tegra-video specific
@@
identifier sd;
identifier pad_cfg;
@@
__tegra_channel_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
@@
identifier sd_state;
@@
__tegra_channel_try_format(...)
{
...
struct v4l2_subdev_state *sd_state;
<...
- sd_state->try_crop
+ sd_state->pads->try_crop
...>
}
// End of tegra-video specific
// </smpl>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-10 17:55:58 +03:00
|
|
|
framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
|
2018-05-14 20:56:35 -04:00
|
|
|
*framefmt = format->format;
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-15 03:50:13 +02:00
|
|
|
mutex_unlock(&priv->lock);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
|
media: v4l2-subdev: add subdev-wide state struct
We have 'struct v4l2_subdev_pad_config' which contains configuration for
a single pad used for the TRY functionality, and an array of those
structs is passed to various v4l2_subdev_pad_ops.
I was working on subdev internal routing between pads, and realized that
there's no way to add TRY functionality for routes, which is not pad
specific configuration. Adding a separate struct for try-route config
wouldn't work either, as e.g. set-fmt needs to know the try-route
configuration to propagate the settings.
This patch adds a new struct, 'struct v4l2_subdev_state' (which at the
moment only contains the v4l2_subdev_pad_config array) and the new
struct is used in most of the places where v4l2_subdev_pad_config was
used. All v4l2_subdev_pad_ops functions taking v4l2_subdev_pad_config
are changed to instead take v4l2_subdev_state.
The changes to drivers/media/v4l2-core/v4l2-subdev.c and
include/media/v4l2-subdev.h were written by hand, and all the driver
changes were done with the semantic patch below. The spatch needs to be
applied to a select list of directories. I used the following shell
commands to apply the spatch:
dirs="drivers/media/i2c drivers/media/platform drivers/media/usb drivers/media/test-drivers/vimc drivers/media/pci drivers/staging/media"
for dir in $dirs; do spatch -j8 --dir --include-headers --no-show-diff --in-place --sp-file v4l2-subdev-state.cocci $dir; done
Note that Coccinelle chokes on a few drivers (gcc extensions?). With
minor changes we can make Coccinelle run fine, and these changes can be
reverted after spatch. The diff for these changes is:
For drivers/media/i2c/s5k5baf.c:
@@ -1481,7 +1481,7 @@ static int s5k5baf_set_selection(struct v4l2_subdev *sd,
&s5k5baf_cis_rect,
v4l2_subdev_get_try_crop(sd, cfg, PAD_CIS),
v4l2_subdev_get_try_compose(sd, cfg, PAD_CIS),
- v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT)
+ v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT),
};
s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
return 0;
For drivers/media/platform/s3c-camif/camif-capture.c:
@@ -1230,7 +1230,7 @@ static int s3c_camif_subdev_get_fmt(struct v4l2_subdev *sd,
*mf = camif->mbus_fmt;
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* crop rectangle at camera interface input */
mf->width = camif->camif_crop.width;
mf->height = camif->camif_crop.height;
@@ -1332,7 +1332,7 @@ static int s3c_camif_subdev_set_fmt(struct v4l2_subdev *sd,
}
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* Pixel format can be only changed on the sink pad. */
mf->code = camif->mbus_fmt.code;
mf->width = crop->width;
The semantic patch is:
// <smpl>
// Change function parameter
@@
identifier func;
identifier cfg;
@@
func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...)
{
<...
- cfg
+ sd_state
...>
}
// Change function declaration parameter
@@
identifier func;
identifier cfg;
type T;
@@
T func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...);
// Change function return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...)
{
...
}
// Change function declaration return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...);
// Some drivers pass a local pad_cfg for a single pad to a called function. Wrap it
// inside a pad_state.
@@
identifier func;
identifier pad_cfg;
@@
func(...)
{
...
struct v4l2_subdev_pad_config pad_cfg;
+ struct v4l2_subdev_state pad_state = { .pads = &pad_cfg };
<+...
(
v4l2_subdev_call
|
sensor_call
|
isi_try_fse
|
isc_try_fse
|
saa_call_all
)
(...,
- &pad_cfg
+ &pad_state
,...)
...+>
}
// If the function uses fields from pad_config, access via state->pads
@@
identifier func;
identifier state;
@@
func(...,
struct v4l2_subdev_state *state
, ...)
{
<...
(
- state->try_fmt
+ state->pads->try_fmt
|
- state->try_crop
+ state->pads->try_crop
|
- state->try_compose
+ state->pads->try_compose
)
...>
}
// If the function accesses the filehandle, use fh->state instead
@@
struct v4l2_subdev_fh *fh;
@@
- fh->pad
+ fh->state
@@
struct v4l2_subdev_fh fh;
@@
- fh.pad
+ fh.state
// Start of vsp1 specific
@@
@@
struct vsp1_entity {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
};
@@
symbol entity;
@@
vsp1_entity_init(...)
{
...
entity->config =
- v4l2_subdev_alloc_pad_config
+ v4l2_subdev_alloc_state
(&entity->subdev);
...
}
@@
symbol entity;
@@
vsp1_entity_destroy(...)
{
...
- v4l2_subdev_free_pad_config
+ v4l2_subdev_free_state
(entity->config);
...
}
@exists@
identifier func =~ "(^vsp1.*)|(hsit_set_format)|(sru_enum_frame_size)|(sru_set_format)|(uif_get_selection)|(uif_set_selection)|(uds_enum_frame_size)|(uds_set_format)|(brx_set_format)|(brx_get_selection)|(histo_get_selection)|(histo_set_selection)|(brx_set_selection)";
symbol config;
@@
func(...) {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
}
// End of vsp1 specific
// Start of rcar specific
@@
identifier sd;
identifier pad_cfg;
@@
rvin_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
// End of rcar specific
// Start of rockchip specific
@@
identifier func =~ "(rkisp1_rsz_get_pad_fmt)|(rkisp1_rsz_get_pad_crop)|(rkisp1_rsz_register)";
symbol rsz;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = rsz->pad_cfg };
...
- rsz->pad_cfg
+ &state
...
}
@@
identifier func =~ "(rkisp1_isp_get_pad_fmt)|(rkisp1_isp_get_pad_crop)";
symbol isp;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = isp->pad_cfg };
...
- isp->pad_cfg
+ &state
...
}
@@
symbol rkisp1;
symbol isp;
symbol pad_cfg;
@@
rkisp1_isp_register(...)
{
+ struct v4l2_subdev_state state = { .pads = rkisp1->isp.pad_cfg };
...
- rkisp1->isp.pad_cfg
+ &state
...
}
// End of rockchip specific
// Start of tegra-video specific
@@
identifier sd;
identifier pad_cfg;
@@
__tegra_channel_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
@@
identifier sd_state;
@@
__tegra_channel_try_format(...)
{
...
struct v4l2_subdev_state *sd_state;
<...
- sd_state->try_crop
+ sd_state->pads->try_crop
...>
}
// End of tegra-video specific
// </smpl>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-10 17:55:58 +03:00
|
|
|
struct v4l2_subdev_state *sd_state,
|
2018-05-14 20:56:35 -04:00
|
|
|
struct v4l2_subdev_format *format)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = sd_to_csi2(sd);
|
|
|
|
|
|
2021-09-15 03:50:13 +02:00
|
|
|
mutex_lock(&priv->lock);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
|
|
|
|
|
format->format = priv->mf;
|
|
|
|
|
else
|
media: v4l2-subdev: add subdev-wide state struct
We have 'struct v4l2_subdev_pad_config' which contains configuration for
a single pad used for the TRY functionality, and an array of those
structs is passed to various v4l2_subdev_pad_ops.
I was working on subdev internal routing between pads, and realized that
there's no way to add TRY functionality for routes, which is not pad
specific configuration. Adding a separate struct for try-route config
wouldn't work either, as e.g. set-fmt needs to know the try-route
configuration to propagate the settings.
This patch adds a new struct, 'struct v4l2_subdev_state' (which at the
moment only contains the v4l2_subdev_pad_config array) and the new
struct is used in most of the places where v4l2_subdev_pad_config was
used. All v4l2_subdev_pad_ops functions taking v4l2_subdev_pad_config
are changed to instead take v4l2_subdev_state.
The changes to drivers/media/v4l2-core/v4l2-subdev.c and
include/media/v4l2-subdev.h were written by hand, and all the driver
changes were done with the semantic patch below. The spatch needs to be
applied to a select list of directories. I used the following shell
commands to apply the spatch:
dirs="drivers/media/i2c drivers/media/platform drivers/media/usb drivers/media/test-drivers/vimc drivers/media/pci drivers/staging/media"
for dir in $dirs; do spatch -j8 --dir --include-headers --no-show-diff --in-place --sp-file v4l2-subdev-state.cocci $dir; done
Note that Coccinelle chokes on a few drivers (gcc extensions?). With
minor changes we can make Coccinelle run fine, and these changes can be
reverted after spatch. The diff for these changes is:
For drivers/media/i2c/s5k5baf.c:
@@ -1481,7 +1481,7 @@ static int s5k5baf_set_selection(struct v4l2_subdev *sd,
&s5k5baf_cis_rect,
v4l2_subdev_get_try_crop(sd, cfg, PAD_CIS),
v4l2_subdev_get_try_compose(sd, cfg, PAD_CIS),
- v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT)
+ v4l2_subdev_get_try_crop(sd, cfg, PAD_OUT),
};
s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
return 0;
For drivers/media/platform/s3c-camif/camif-capture.c:
@@ -1230,7 +1230,7 @@ static int s3c_camif_subdev_get_fmt(struct v4l2_subdev *sd,
*mf = camif->mbus_fmt;
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* crop rectangle at camera interface input */
mf->width = camif->camif_crop.width;
mf->height = camif->camif_crop.height;
@@ -1332,7 +1332,7 @@ static int s3c_camif_subdev_set_fmt(struct v4l2_subdev *sd,
}
break;
- case CAMIF_SD_PAD_SOURCE_C...CAMIF_SD_PAD_SOURCE_P:
+ case CAMIF_SD_PAD_SOURCE_C:
/* Pixel format can be only changed on the sink pad. */
mf->code = camif->mbus_fmt.code;
mf->width = crop->width;
The semantic patch is:
// <smpl>
// Change function parameter
@@
identifier func;
identifier cfg;
@@
func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...)
{
<...
- cfg
+ sd_state
...>
}
// Change function declaration parameter
@@
identifier func;
identifier cfg;
type T;
@@
T func(...,
- struct v4l2_subdev_pad_config *cfg
+ struct v4l2_subdev_state *sd_state
, ...);
// Change function return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...)
{
...
}
// Change function declaration return value
@@
identifier func;
@@
- struct v4l2_subdev_pad_config
+ struct v4l2_subdev_state
*func(...);
// Some drivers pass a local pad_cfg for a single pad to a called function. Wrap it
// inside a pad_state.
@@
identifier func;
identifier pad_cfg;
@@
func(...)
{
...
struct v4l2_subdev_pad_config pad_cfg;
+ struct v4l2_subdev_state pad_state = { .pads = &pad_cfg };
<+...
(
v4l2_subdev_call
|
sensor_call
|
isi_try_fse
|
isc_try_fse
|
saa_call_all
)
(...,
- &pad_cfg
+ &pad_state
,...)
...+>
}
// If the function uses fields from pad_config, access via state->pads
@@
identifier func;
identifier state;
@@
func(...,
struct v4l2_subdev_state *state
, ...)
{
<...
(
- state->try_fmt
+ state->pads->try_fmt
|
- state->try_crop
+ state->pads->try_crop
|
- state->try_compose
+ state->pads->try_compose
)
...>
}
// If the function accesses the filehandle, use fh->state instead
@@
struct v4l2_subdev_fh *fh;
@@
- fh->pad
+ fh->state
@@
struct v4l2_subdev_fh fh;
@@
- fh.pad
+ fh.state
// Start of vsp1 specific
@@
@@
struct vsp1_entity {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
};
@@
symbol entity;
@@
vsp1_entity_init(...)
{
...
entity->config =
- v4l2_subdev_alloc_pad_config
+ v4l2_subdev_alloc_state
(&entity->subdev);
...
}
@@
symbol entity;
@@
vsp1_entity_destroy(...)
{
...
- v4l2_subdev_free_pad_config
+ v4l2_subdev_free_state
(entity->config);
...
}
@exists@
identifier func =~ "(^vsp1.*)|(hsit_set_format)|(sru_enum_frame_size)|(sru_set_format)|(uif_get_selection)|(uif_set_selection)|(uds_enum_frame_size)|(uds_set_format)|(brx_set_format)|(brx_get_selection)|(histo_get_selection)|(histo_set_selection)|(brx_set_selection)";
symbol config;
@@
func(...) {
...
- struct v4l2_subdev_pad_config *config;
+ struct v4l2_subdev_state *config;
...
}
// End of vsp1 specific
// Start of rcar specific
@@
identifier sd;
identifier pad_cfg;
@@
rvin_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
// End of rcar specific
// Start of rockchip specific
@@
identifier func =~ "(rkisp1_rsz_get_pad_fmt)|(rkisp1_rsz_get_pad_crop)|(rkisp1_rsz_register)";
symbol rsz;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = rsz->pad_cfg };
...
- rsz->pad_cfg
+ &state
...
}
@@
identifier func =~ "(rkisp1_isp_get_pad_fmt)|(rkisp1_isp_get_pad_crop)";
symbol isp;
symbol pad_cfg;
@@
func(...)
{
+ struct v4l2_subdev_state state = { .pads = isp->pad_cfg };
...
- isp->pad_cfg
+ &state
...
}
@@
symbol rkisp1;
symbol isp;
symbol pad_cfg;
@@
rkisp1_isp_register(...)
{
+ struct v4l2_subdev_state state = { .pads = rkisp1->isp.pad_cfg };
...
- rkisp1->isp.pad_cfg
+ &state
...
}
// End of rockchip specific
// Start of tegra-video specific
@@
identifier sd;
identifier pad_cfg;
@@
__tegra_channel_try_format(...)
{
...
- struct v4l2_subdev_pad_config *pad_cfg;
+ struct v4l2_subdev_state *sd_state;
...
- pad_cfg = v4l2_subdev_alloc_pad_config(sd);
+ sd_state = v4l2_subdev_alloc_state(sd);
<...
- pad_cfg
+ sd_state
...>
- v4l2_subdev_free_pad_config(pad_cfg);
+ v4l2_subdev_free_state(sd_state);
...
}
@@
identifier sd_state;
@@
__tegra_channel_try_format(...)
{
...
struct v4l2_subdev_state *sd_state;
<...
- sd_state->try_crop
+ sd_state->pads->try_crop
...>
}
// End of tegra-video specific
// </smpl>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-10 17:55:58 +03:00
|
|
|
format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2021-09-15 03:50:13 +02:00
|
|
|
mutex_unlock(&priv->lock);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
|
|
|
|
|
.s_stream = rcsi2_s_stream,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
|
|
|
|
|
.set_fmt = rcsi2_set_pad_format,
|
|
|
|
|
.get_fmt = rcsi2_get_pad_format,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
|
|
|
|
|
.video = &rcar_csi2_video_ops,
|
|
|
|
|
.pad = &rcar_csi2_pad_ops,
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-11 16:30:58 -04:00
|
|
|
static irqreturn_t rcsi2_irq(int irq, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = data;
|
|
|
|
|
u32 status, err_status;
|
|
|
|
|
|
|
|
|
|
status = rcsi2_read(priv, INTSTATE_REG);
|
|
|
|
|
err_status = rcsi2_read(priv, INTERRSTATE_REG);
|
|
|
|
|
|
|
|
|
|
if (!status)
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
|
|
|
|
rcsi2_write(priv, INTSTATE_REG, status);
|
|
|
|
|
|
|
|
|
|
if (!err_status)
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
|
|
|
|
rcsi2_write(priv, INTERRSTATE_REG, err_status);
|
|
|
|
|
|
|
|
|
|
dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
|
|
|
|
|
|
|
|
|
|
return IRQ_WAKE_THREAD;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t rcsi2_irq_thread(int irq, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = data;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&priv->lock);
|
|
|
|
|
rcsi2_stop(priv);
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
|
if (rcsi2_start(priv))
|
|
|
|
|
dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
|
|
|
|
|
mutex_unlock(&priv->lock);
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
/* -----------------------------------------------------------------------------
|
|
|
|
|
* Async handling and registration of subdevices and links.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
|
|
|
|
|
struct v4l2_subdev *subdev,
|
|
|
|
|
struct v4l2_async_subdev *asd)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = notifier_to_csi2(notifier);
|
|
|
|
|
int pad;
|
|
|
|
|
|
|
|
|
|
pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
|
|
|
|
|
MEDIA_PAD_FL_SOURCE);
|
|
|
|
|
if (pad < 0) {
|
|
|
|
|
dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
|
|
|
|
|
return pad;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->remote = subdev;
|
2020-07-17 16:53:24 +02:00
|
|
|
priv->remote_pad = pad;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
|
|
|
|
|
|
|
|
|
|
return media_create_pad_link(&subdev->entity, pad,
|
|
|
|
|
&priv->subdev.entity, 0,
|
|
|
|
|
MEDIA_LNK_FL_ENABLED |
|
|
|
|
|
MEDIA_LNK_FL_IMMUTABLE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
|
|
|
|
|
struct v4l2_subdev *subdev,
|
|
|
|
|
struct v4l2_async_subdev *asd)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = notifier_to_csi2(notifier);
|
|
|
|
|
|
|
|
|
|
priv->remote = NULL;
|
|
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
|
|
|
|
|
.bound = rcsi2_notify_bound,
|
|
|
|
|
.unbind = rcsi2_notify_unbind,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
|
|
|
|
|
struct v4l2_fwnode_endpoint *vep)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
/* Only port 0 endpoint 0 is valid. */
|
|
|
|
|
if (vep->base.port || vep->base.id)
|
|
|
|
|
return -ENOTCONN;
|
|
|
|
|
|
2018-07-03 17:19:27 -04:00
|
|
|
if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
|
2018-05-14 20:56:35 -04:00
|
|
|
dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
|
|
|
|
|
if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
|
|
|
|
|
dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
|
|
|
|
|
priv->lanes);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
|
|
|
|
|
priv->lane_swap[i] = i < priv->lanes ?
|
|
|
|
|
vep->bus.mipi_csi2.data_lanes[i] : i;
|
|
|
|
|
|
|
|
|
|
/* Check for valid lane number. */
|
|
|
|
|
if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
|
|
|
|
|
dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_parse_dt(struct rcar_csi2 *priv)
|
|
|
|
|
{
|
2020-08-11 22:59:38 +02:00
|
|
|
struct v4l2_async_subdev *asd;
|
|
|
|
|
struct fwnode_handle *fwnode;
|
2020-09-14 23:50:10 +02:00
|
|
|
struct fwnode_handle *ep;
|
2020-09-14 23:50:11 +02:00
|
|
|
struct v4l2_fwnode_endpoint v4l2_ep = {
|
|
|
|
|
.bus_type = V4L2_MBUS_CSI2_DPHY
|
|
|
|
|
};
|
2018-05-14 20:56:35 -04:00
|
|
|
int ret;
|
|
|
|
|
|
2020-09-14 23:50:10 +02:00
|
|
|
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
|
2018-05-14 20:56:35 -04:00
|
|
|
if (!ep) {
|
|
|
|
|
dev_err(priv->dev, "Not connected to subdevice\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-14 23:50:10 +02:00
|
|
|
ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
|
2018-05-14 20:56:35 -04:00
|
|
|
if (ret) {
|
|
|
|
|
dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
|
2020-09-14 23:50:10 +02:00
|
|
|
fwnode_handle_put(ep);
|
2018-05-14 20:56:35 -04:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
|
|
|
|
|
if (ret) {
|
2020-09-14 23:50:10 +02:00
|
|
|
fwnode_handle_put(ep);
|
2018-05-14 20:56:35 -04:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-14 23:50:10 +02:00
|
|
|
fwnode = fwnode_graph_get_remote_endpoint(ep);
|
|
|
|
|
fwnode_handle_put(ep);
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2020-08-11 22:59:38 +02:00
|
|
|
dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
|
2018-09-29 15:54:18 -04:00
|
|
|
|
2021-03-05 18:13:12 +01:00
|
|
|
v4l2_async_nf_init(&priv->notifier);
|
2018-05-14 20:56:35 -04:00
|
|
|
priv->notifier.ops = &rcar_csi2_notify_ops;
|
|
|
|
|
|
2021-03-05 18:13:12 +01:00
|
|
|
asd = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode,
|
|
|
|
|
struct v4l2_async_subdev);
|
2020-08-11 22:59:38 +02:00
|
|
|
fwnode_handle_put(fwnode);
|
|
|
|
|
if (IS_ERR(asd))
|
|
|
|
|
return PTR_ERR(asd);
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2021-03-05 18:13:12 +01:00
|
|
|
ret = v4l2_async_subdev_nf_register(&priv->subdev, &priv->notifier);
|
2018-09-29 15:54:18 -04:00
|
|
|
if (ret)
|
2021-03-05 18:13:12 +01:00
|
|
|
v4l2_async_nf_cleanup(&priv->notifier);
|
2018-09-29 15:54:18 -04:00
|
|
|
|
|
|
|
|
return ret;
|
2018-05-14 20:56:35 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
|
|
|
* PHTW initialization sequences.
|
|
|
|
|
*
|
|
|
|
|
* NOTE: Magic values are from the datasheet and lack documentation.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
|
|
|
|
|
{
|
|
|
|
|
unsigned int timeout;
|
|
|
|
|
|
|
|
|
|
rcsi2_write(priv, PHTW_REG,
|
|
|
|
|
PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
|
|
|
|
|
PHTW_CWEN | PHTW_TESTDIN_CODE(code));
|
|
|
|
|
|
|
|
|
|
/* Wait for DWEN and CWEN to be cleared by hardware. */
|
|
|
|
|
for (timeout = 0; timeout <= 20; timeout++) {
|
|
|
|
|
if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
|
|
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
|
|
|
|
|
const struct phtw_value *values)
|
|
|
|
|
{
|
|
|
|
|
const struct phtw_value *value;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
for (value = values; value->data || value->code; value++) {
|
|
|
|
|
ret = rcsi2_phtw_write(priv, value->data, value->code);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
|
|
|
|
|
const struct rcsi2_mbps_reg *values, u16 code)
|
|
|
|
|
{
|
|
|
|
|
const struct rcsi2_mbps_reg *value;
|
2021-08-13 17:07:56 +02:00
|
|
|
const struct rcsi2_mbps_reg *prev_value = NULL;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2021-08-13 17:07:56 +02:00
|
|
|
for (value = values; value->mbps; value++) {
|
2018-05-14 20:56:35 -04:00
|
|
|
if (value->mbps >= mbps)
|
|
|
|
|
break;
|
2021-08-13 17:07:56 +02:00
|
|
|
prev_value = value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (prev_value &&
|
|
|
|
|
((mbps - prev_value->mbps) <= (value->mbps - mbps)))
|
|
|
|
|
value = prev_value;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
if (!value->mbps) {
|
|
|
|
|
dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
|
|
|
|
|
return -ERANGE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return rcsi2_phtw_write(priv, value->reg, code);
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-12 19:50:18 -04:00
|
|
|
static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
|
|
|
|
|
unsigned int mbps)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
static const struct phtw_value step1[] = {
|
|
|
|
|
{ .data = 0xcc, .code = 0xe2 },
|
|
|
|
|
{ .data = 0x01, .code = 0xe3 },
|
|
|
|
|
{ .data = 0x11, .code = 0xe4 },
|
|
|
|
|
{ .data = 0x01, .code = 0xe5 },
|
|
|
|
|
{ .data = 0x10, .code = 0x04 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct phtw_value step2[] = {
|
|
|
|
|
{ .data = 0x38, .code = 0x08 },
|
|
|
|
|
{ .data = 0x01, .code = 0x00 },
|
|
|
|
|
{ .data = 0x4b, .code = 0xac },
|
|
|
|
|
{ .data = 0x03, .code = 0x00 },
|
|
|
|
|
{ .data = 0x80, .code = 0x07 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_phtw_write_array(priv, step1);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2019-03-12 19:50:18 -04:00
|
|
|
if (mbps != 0 && mbps <= 250) {
|
2018-05-14 20:56:35 -04:00
|
|
|
ret = rcsi2_phtw_write(priv, 0x39, 0x05);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
|
|
|
|
|
0xf1);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return rcsi2_phtw_write_array(priv, step2);
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-12 19:50:18 -04:00
|
|
|
static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
|
|
|
|
|
{
|
|
|
|
|
return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
|
|
|
|
|
{
|
|
|
|
|
return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
|
2018-07-26 18:36:57 -04:00
|
|
|
{
|
|
|
|
|
return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-11 21:32:32 +02:00
|
|
|
static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
static const struct phtw_value step1[] = {
|
2019-03-12 19:50:17 -04:00
|
|
|
{ .data = 0xee, .code = 0x34 },
|
|
|
|
|
{ .data = 0xee, .code = 0x44 },
|
|
|
|
|
{ .data = 0xee, .code = 0x54 },
|
|
|
|
|
{ .data = 0xee, .code = 0x84 },
|
|
|
|
|
{ .data = 0xee, .code = 0x94 },
|
2018-05-14 20:56:35 -04:00
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
return rcsi2_phtw_write_array(priv, step1);
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-12 10:46:29 +02:00
|
|
|
static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv,
|
|
|
|
|
unsigned int mbps)
|
|
|
|
|
{
|
|
|
|
|
/* In case of 1500Mbps or less */
|
|
|
|
|
static const struct phtw_value step1[] = {
|
|
|
|
|
{ .data = 0xcc, .code = 0xe2 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct phtw_value step2[] = {
|
|
|
|
|
{ .data = 0x01, .code = 0xe3 },
|
|
|
|
|
{ .data = 0x11, .code = 0xe4 },
|
|
|
|
|
{ .data = 0x01, .code = 0xe5 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* In case of 1500Mbps or less */
|
|
|
|
|
static const struct phtw_value step3[] = {
|
|
|
|
|
{ .data = 0x38, .code = 0x08 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct phtw_value step4[] = {
|
|
|
|
|
{ .data = 0x01, .code = 0x00 },
|
|
|
|
|
{ .data = 0x4b, .code = 0xac },
|
|
|
|
|
{ .data = 0x03, .code = 0x00 },
|
|
|
|
|
{ .data = 0x80, .code = 0x07 },
|
|
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
if (mbps != 0 && mbps <= 1500)
|
|
|
|
|
ret = rcsi2_phtw_write_array(priv, step1);
|
|
|
|
|
else
|
|
|
|
|
ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_phtw_write_array(priv, step2);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
if (mbps != 0 && mbps <= 1500) {
|
|
|
|
|
ret = rcsi2_phtw_write_array(priv, step3);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_phtw_write_array(priv, step4);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
/* -----------------------------------------------------------------------------
|
|
|
|
|
* Platform Device Driver.
|
|
|
|
|
*/
|
|
|
|
|
|
media: rcar-{csi2,vin}: Move to full Virtual Channel routing per CSI-2 IP
When Gen3 support was first added to this R-Car VIN and CSI-2 driver the
routing was centred around the CHSEL register which multiplexes the
different parallel buses that sit between the CSI-2 receivers source
side and the VIN dma engines. This was a bad design as the multiplexing
do allow for only a few combinations and do not play nice with many
video streams in the system.
For example it's only possible for CSI-2 Virtual Channels 0 and 1 of any
given CSI-2 receiver to be used together with the scaler.
Later datasheets have expanded the documentation and it is now possible
to improve on this design by allowing any Virtual Channel to be routed
to any R-Car VIN instance, provided that there exists a parallel bus
between them. This increases the flexibility as all Virtual Channels can
now be used together with the scaler for example.
The redesign is not however perfect. While the new design allows for
many more routes, two constrains limit a small portion of routes that
was possible in the old design but are no more.
- It is no longer possible to route the same CSI-2 and VC to more then
one VIN at a time. This was theoretically possible before if the
specific SoC allowed for the same CSI-2 and VC to be routed to two
different VIN capture groups.
- It is no longer possible to simultaneously mix links from two CSI-2 IP
blocks to the same VIN capture group.
For example if VIN2 is capturing from CSI40 then VIN{0,1,3} must also
capture from CSI40. While VIN{4,5,6,7} is still free to capture from
any other CSI-2 IP in the system. Once all VIN{0,1,2,3} links to CSI40
are disabled that VIN capture group is free again to capture from any
other CSI-2 IP it is connected to.
At the core of the redesign is greater cooperator of the R-Car VIN and
CSI-2 drivers in configuring the routing. The VIN driver is after this
change only responsible to configure the full VIN capture groups
parallel buses to be to a particular CSI-2 IP. While the configuration
of which CSI-2 Virtual Channel is outputted on which of the R-Car CSI-2
IP output ports is handled by the CSI-2 driver.
Before this change the CSI-2 Virtual Channel to output port was static
in the CSI-2 driver and the different links only manipulated the VIN
capture groups CHSEL register. With this change both the CHSEl register
and the CSI-2 routing VCDT registers are modified for greater
flexibility.
This change touches both the R-Car VIN and R-Car CSI-2 drivers in the
same commit as both drivers cooperate closely and one change without the
other would more or less break video capture.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: fix two trivial checkpatch whitespace issues]
2022-01-24 13:48:58 +01:00
|
|
|
static int rcsi2_link_setup(struct media_entity *entity,
|
|
|
|
|
const struct media_pad *local,
|
|
|
|
|
const struct media_pad *remote, u32 flags)
|
|
|
|
|
{
|
|
|
|
|
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
|
|
|
|
|
struct rcar_csi2 *priv = sd_to_csi2(sd);
|
|
|
|
|
struct video_device *vdev;
|
|
|
|
|
int channel, vc;
|
|
|
|
|
u32 id;
|
|
|
|
|
|
|
|
|
|
if (!is_media_entity_v4l2_video_device(remote->entity)) {
|
|
|
|
|
dev_err(priv->dev, "Remote is not a video device\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vdev = media_entity_to_video_device(remote->entity);
|
|
|
|
|
|
|
|
|
|
if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) {
|
|
|
|
|
dev_err(priv->dev, "No renesas,id, can't configure routing\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
channel = id % 4;
|
|
|
|
|
|
|
|
|
|
if (flags & MEDIA_LNK_FL_ENABLED) {
|
|
|
|
|
if (media_entity_remote_pad(local)) {
|
|
|
|
|
dev_dbg(priv->dev,
|
|
|
|
|
"Each VC can only be routed to one output channel\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vc = local->index - 1;
|
|
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n",
|
|
|
|
|
vc, id, channel);
|
|
|
|
|
} else {
|
|
|
|
|
vc = -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
priv->channel_vc[channel] = vc;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
static const struct media_entity_operations rcar_csi2_entity_ops = {
|
media: rcar-{csi2,vin}: Move to full Virtual Channel routing per CSI-2 IP
When Gen3 support was first added to this R-Car VIN and CSI-2 driver the
routing was centred around the CHSEL register which multiplexes the
different parallel buses that sit between the CSI-2 receivers source
side and the VIN dma engines. This was a bad design as the multiplexing
do allow for only a few combinations and do not play nice with many
video streams in the system.
For example it's only possible for CSI-2 Virtual Channels 0 and 1 of any
given CSI-2 receiver to be used together with the scaler.
Later datasheets have expanded the documentation and it is now possible
to improve on this design by allowing any Virtual Channel to be routed
to any R-Car VIN instance, provided that there exists a parallel bus
between them. This increases the flexibility as all Virtual Channels can
now be used together with the scaler for example.
The redesign is not however perfect. While the new design allows for
many more routes, two constrains limit a small portion of routes that
was possible in the old design but are no more.
- It is no longer possible to route the same CSI-2 and VC to more then
one VIN at a time. This was theoretically possible before if the
specific SoC allowed for the same CSI-2 and VC to be routed to two
different VIN capture groups.
- It is no longer possible to simultaneously mix links from two CSI-2 IP
blocks to the same VIN capture group.
For example if VIN2 is capturing from CSI40 then VIN{0,1,3} must also
capture from CSI40. While VIN{4,5,6,7} is still free to capture from
any other CSI-2 IP in the system. Once all VIN{0,1,2,3} links to CSI40
are disabled that VIN capture group is free again to capture from any
other CSI-2 IP it is connected to.
At the core of the redesign is greater cooperator of the R-Car VIN and
CSI-2 drivers in configuring the routing. The VIN driver is after this
change only responsible to configure the full VIN capture groups
parallel buses to be to a particular CSI-2 IP. While the configuration
of which CSI-2 Virtual Channel is outputted on which of the R-Car CSI-2
IP output ports is handled by the CSI-2 driver.
Before this change the CSI-2 Virtual Channel to output port was static
in the CSI-2 driver and the different links only manipulated the VIN
capture groups CHSEL register. With this change both the CHSEl register
and the CSI-2 routing VCDT registers are modified for greater
flexibility.
This change touches both the R-Car VIN and R-Car CSI-2 drivers in the
same commit as both drivers cooperate closely and one change without the
other would more or less break video capture.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: fix two trivial checkpatch whitespace issues]
2022-01-24 13:48:58 +01:00
|
|
|
.link_setup = rcsi2_link_setup,
|
2018-05-14 20:56:35 -04:00
|
|
|
.link_validate = v4l2_subdev_link_validate,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int rcsi2_probe_resources(struct rcar_csi2 *priv,
|
|
|
|
|
struct platform_device *pdev)
|
|
|
|
|
{
|
2019-04-11 16:30:58 -04:00
|
|
|
int irq, ret;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
2021-09-01 07:55:09 +02:00
|
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
2018-05-14 20:56:35 -04:00
|
|
|
if (IS_ERR(priv->base))
|
|
|
|
|
return PTR_ERR(priv->base);
|
|
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
|
if (irq < 0)
|
|
|
|
|
return irq;
|
|
|
|
|
|
2019-04-11 16:30:58 -04:00
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
|
|
|
|
|
rcsi2_irq_thread, IRQF_SHARED,
|
|
|
|
|
KBUILD_MODNAME, priv);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2019-03-12 19:49:30 -04:00
|
|
|
priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
|
|
|
|
|
|
2019-05-15 20:35:38 -04:00
|
|
|
return PTR_ERR_OR_ZERO(priv->rstc);
|
2018-05-14 20:56:35 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
|
|
|
|
|
.hsfreqrange = hsfreqrange_h3_v3h_m3n,
|
|
|
|
|
.csi0clkfreqrange = 0x20,
|
2018-11-06 05:54:27 -05:00
|
|
|
.num_channels = 4,
|
2018-05-14 20:56:35 -04:00
|
|
|
.clear_ulps = true,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
|
|
|
|
|
.hsfreqrange = hsfreqrange_m3w_h3es1,
|
2018-11-06 05:54:27 -05:00
|
|
|
.num_channels = 4,
|
2018-05-14 20:56:35 -04:00
|
|
|
};
|
|
|
|
|
|
2019-03-12 19:50:18 -04:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_h3es2,
|
|
|
|
|
.hsfreqrange = hsfreqrange_h3_v3h_m3n,
|
|
|
|
|
.csi0clkfreqrange = 0x20,
|
|
|
|
|
.num_channels = 4,
|
|
|
|
|
.clear_ulps = true,
|
|
|
|
|
};
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
|
|
|
|
|
.hsfreqrange = hsfreqrange_m3w_h3es1,
|
2018-11-06 05:54:27 -05:00
|
|
|
.num_channels = 4,
|
2018-05-14 20:56:35 -04:00
|
|
|
};
|
|
|
|
|
|
2021-05-13 16:09:14 +02:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {
|
|
|
|
|
.hsfreqrange = hsfreqrange_m3w_h3es1,
|
|
|
|
|
.num_channels = 4,
|
|
|
|
|
};
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
|
|
|
|
|
.hsfreqrange = hsfreqrange_h3_v3h_m3n,
|
|
|
|
|
.csi0clkfreqrange = 0x20,
|
2018-11-06 05:54:27 -05:00
|
|
|
.num_channels = 4,
|
2018-05-14 20:56:35 -04:00
|
|
|
.clear_ulps = true,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_v3m_e3,
|
2020-06-11 21:32:32 +02:00
|
|
|
.phy_post_init = rcsi2_phy_post_init_v3m_e3,
|
2018-11-06 05:54:27 -05:00
|
|
|
.num_channels = 4,
|
2018-05-14 20:56:35 -04:00
|
|
|
};
|
|
|
|
|
|
2018-08-06 12:56:27 -04:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
|
|
|
|
|
.hsfreqrange = hsfreqrange_h3_v3h_m3n,
|
|
|
|
|
.csi0clkfreqrange = 0x20,
|
|
|
|
|
.clear_ulps = true,
|
|
|
|
|
};
|
|
|
|
|
|
2018-11-06 05:54:25 -05:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_v3m_e3,
|
2020-06-11 21:32:32 +02:00
|
|
|
.phy_post_init = rcsi2_phy_post_init_v3m_e3,
|
2018-11-06 05:54:27 -05:00
|
|
|
.num_channels = 2,
|
2018-11-06 05:54:25 -05:00
|
|
|
};
|
|
|
|
|
|
2021-06-12 10:46:29 +02:00
|
|
|
static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = {
|
|
|
|
|
.init_phtw = rcsi2_init_phtw_v3u,
|
|
|
|
|
.hsfreqrange = hsfreqrange_v3u,
|
|
|
|
|
.csi0clkfreqrange = 0x20,
|
|
|
|
|
.clear_ulps = true,
|
|
|
|
|
.use_isp = true,
|
|
|
|
|
};
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
static const struct of_device_id rcar_csi2_of_table[] = {
|
2019-03-01 10:45:34 -05:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a774a1-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a7796,
|
|
|
|
|
},
|
2019-10-15 07:57:58 -03:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a774b1-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77965,
|
|
|
|
|
},
|
2018-12-13 15:24:12 -05:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a774c0-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77990,
|
|
|
|
|
},
|
2020-07-16 19:18:33 +02:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a774e1-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a7795,
|
|
|
|
|
},
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a7795-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a7795,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a7796-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a7796,
|
|
|
|
|
},
|
2021-05-13 16:09:14 +02:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a77961-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77961,
|
|
|
|
|
},
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a77965-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77965,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a77970-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77970,
|
|
|
|
|
},
|
2018-08-06 12:56:27 -04:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a77980-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77980,
|
|
|
|
|
},
|
2018-11-06 05:54:25 -05:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a77990-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a77990,
|
|
|
|
|
},
|
2021-06-12 10:46:29 +02:00
|
|
|
{
|
|
|
|
|
.compatible = "renesas,r8a779a0-csi2",
|
|
|
|
|
.data = &rcar_csi2_info_r8a779a0,
|
|
|
|
|
},
|
2018-05-14 20:56:35 -04:00
|
|
|
{ /* sentinel */ },
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
|
|
|
|
|
|
2019-03-12 19:50:18 -04:00
|
|
|
static const struct soc_device_attribute r8a7795[] = {
|
2018-05-14 20:56:35 -04:00
|
|
|
{
|
|
|
|
|
.soc_id = "r8a7795", .revision = "ES1.*",
|
|
|
|
|
.data = &rcar_csi2_info_r8a7795es1,
|
|
|
|
|
},
|
2019-03-12 19:50:18 -04:00
|
|
|
{
|
|
|
|
|
.soc_id = "r8a7795", .revision = "ES2.*",
|
|
|
|
|
.data = &rcar_csi2_info_r8a7795es2,
|
|
|
|
|
},
|
2022-03-03 13:43:57 +01:00
|
|
|
{ /* sentinel */ }
|
2018-05-14 20:56:35 -04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int rcsi2_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
const struct soc_device_attribute *attr;
|
|
|
|
|
struct rcar_csi2 *priv;
|
2021-06-12 10:46:29 +02:00
|
|
|
unsigned int i, num_pads;
|
2018-05-14 20:56:35 -04:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
|
if (!priv)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
priv->info = of_device_get_match_data(&pdev->dev);
|
|
|
|
|
|
|
|
|
|
/*
|
2019-03-12 19:50:18 -04:00
|
|
|
* The different ES versions of r8a7795 (H3) behave differently but
|
|
|
|
|
* share the same compatible string.
|
2018-05-14 20:56:35 -04:00
|
|
|
*/
|
2019-03-12 19:50:18 -04:00
|
|
|
attr = soc_device_match(r8a7795);
|
2018-05-14 20:56:35 -04:00
|
|
|
if (attr)
|
|
|
|
|
priv->info = attr->data;
|
|
|
|
|
|
|
|
|
|
priv->dev = &pdev->dev;
|
|
|
|
|
|
|
|
|
|
mutex_init(&priv->lock);
|
|
|
|
|
priv->stream_count = 0;
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_probe_resources(priv, pdev);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(priv->dev, "Failed to get resources\n");
|
2021-09-15 03:50:12 +02:00
|
|
|
goto error_mutex;
|
2018-05-14 20:56:35 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
|
|
|
|
|
|
ret = rcsi2_parse_dt(priv);
|
|
|
|
|
if (ret)
|
2021-09-15 03:50:12 +02:00
|
|
|
goto error_mutex;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
priv->subdev.owner = THIS_MODULE;
|
|
|
|
|
priv->subdev.dev = &pdev->dev;
|
|
|
|
|
v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
|
|
|
|
|
v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
|
|
|
|
|
snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
|
|
|
|
|
KBUILD_MODNAME, dev_name(&pdev->dev));
|
|
|
|
|
priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
|
|
|
|
|
|
|
|
|
|
priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
|
|
|
|
|
priv->subdev.entity.ops = &rcar_csi2_entity_ops;
|
|
|
|
|
|
2021-06-12 10:46:29 +02:00
|
|
|
num_pads = priv->info->use_isp ? 2 : NR_OF_RCAR_CSI2_PAD;
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
|
2021-06-12 10:46:29 +02:00
|
|
|
for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)
|
2018-05-14 20:56:35 -04:00
|
|
|
priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
|
|
|
|
|
|
2021-06-12 10:46:29 +02:00
|
|
|
ret = media_entity_pads_init(&priv->subdev.entity, num_pads,
|
2018-05-14 20:56:35 -04:00
|
|
|
priv->pads);
|
|
|
|
|
if (ret)
|
2021-09-15 03:50:12 +02:00
|
|
|
goto error_async;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
media: rcar-{csi2,vin}: Move to full Virtual Channel routing per CSI-2 IP
When Gen3 support was first added to this R-Car VIN and CSI-2 driver the
routing was centred around the CHSEL register which multiplexes the
different parallel buses that sit between the CSI-2 receivers source
side and the VIN dma engines. This was a bad design as the multiplexing
do allow for only a few combinations and do not play nice with many
video streams in the system.
For example it's only possible for CSI-2 Virtual Channels 0 and 1 of any
given CSI-2 receiver to be used together with the scaler.
Later datasheets have expanded the documentation and it is now possible
to improve on this design by allowing any Virtual Channel to be routed
to any R-Car VIN instance, provided that there exists a parallel bus
between them. This increases the flexibility as all Virtual Channels can
now be used together with the scaler for example.
The redesign is not however perfect. While the new design allows for
many more routes, two constrains limit a small portion of routes that
was possible in the old design but are no more.
- It is no longer possible to route the same CSI-2 and VC to more then
one VIN at a time. This was theoretically possible before if the
specific SoC allowed for the same CSI-2 and VC to be routed to two
different VIN capture groups.
- It is no longer possible to simultaneously mix links from two CSI-2 IP
blocks to the same VIN capture group.
For example if VIN2 is capturing from CSI40 then VIN{0,1,3} must also
capture from CSI40. While VIN{4,5,6,7} is still free to capture from
any other CSI-2 IP in the system. Once all VIN{0,1,2,3} links to CSI40
are disabled that VIN capture group is free again to capture from any
other CSI-2 IP it is connected to.
At the core of the redesign is greater cooperator of the R-Car VIN and
CSI-2 drivers in configuring the routing. The VIN driver is after this
change only responsible to configure the full VIN capture groups
parallel buses to be to a particular CSI-2 IP. While the configuration
of which CSI-2 Virtual Channel is outputted on which of the R-Car CSI-2
IP output ports is handled by the CSI-2 driver.
Before this change the CSI-2 Virtual Channel to output port was static
in the CSI-2 driver and the different links only manipulated the VIN
capture groups CHSEL register. With this change both the CHSEl register
and the CSI-2 routing VCDT registers are modified for greater
flexibility.
This change touches both the R-Car VIN and R-Car CSI-2 drivers in the
same commit as both drivers cooperate closely and one change without the
other would more or less break video capture.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: fix two trivial checkpatch whitespace issues]
2022-01-24 13:48:58 +01:00
|
|
|
for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++)
|
|
|
|
|
priv->channel_vc[i] = -1;
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
|
|
|
|
ret = v4l2_async_register_subdev(&priv->subdev);
|
|
|
|
|
if (ret < 0)
|
2021-09-15 03:50:12 +02:00
|
|
|
goto error_async;
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
dev_info(priv->dev, "%d lanes found\n", priv->lanes);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
2021-09-15 03:50:12 +02:00
|
|
|
error_async:
|
2021-03-05 18:13:12 +01:00
|
|
|
v4l2_async_nf_unregister(&priv->notifier);
|
|
|
|
|
v4l2_async_nf_cleanup(&priv->notifier);
|
2021-09-15 03:50:12 +02:00
|
|
|
error_mutex:
|
|
|
|
|
mutex_destroy(&priv->lock);
|
2018-05-14 20:56:35 -04:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rcsi2_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct rcar_csi2 *priv = platform_get_drvdata(pdev);
|
|
|
|
|
|
2021-03-05 18:13:12 +01:00
|
|
|
v4l2_async_nf_unregister(&priv->notifier);
|
|
|
|
|
v4l2_async_nf_cleanup(&priv->notifier);
|
2018-05-14 20:56:35 -04:00
|
|
|
v4l2_async_unregister_subdev(&priv->subdev);
|
|
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
|
2021-09-15 03:50:12 +02:00
|
|
|
mutex_destroy(&priv->lock);
|
|
|
|
|
|
2018-05-14 20:56:35 -04:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct platform_driver rcar_csi2_pdrv = {
|
|
|
|
|
.remove = rcsi2_remove,
|
|
|
|
|
.probe = rcsi2_probe,
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "rcar-csi2",
|
2021-11-28 14:24:26 +01:00
|
|
|
.suppress_bind_attrs = true,
|
2018-05-14 20:56:35 -04:00
|
|
|
.of_match_table = rcar_csi2_of_table,
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
module_platform_driver(rcar_csi2_pdrv);
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
|
|
|
|
|
MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
