2019-06-03 07:44:50 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-03-05 11:49:33 +00:00
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_DEBUG_MONITORS_H
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#define __ASM_DEBUG_MONITORS_H
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2015-07-24 16:37:47 +01:00
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#include <linux/errno.h>
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#include <linux/types.h>
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2016-02-23 08:56:45 +01:00
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#include <asm/brk-imm.h>
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2015-07-24 16:37:43 +01:00
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#include <asm/esr.h>
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2015-07-24 16:37:41 +01:00
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#include <asm/insn.h>
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2015-07-24 16:37:47 +01:00
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#include <asm/ptrace.h>
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2015-07-24 16:37:41 +01:00
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2014-05-07 12:13:14 +01:00
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/* Low-level stepping controls. */
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#define DBG_MDSCR_SS (1 << 0)
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#define DBG_SPSR_SS (1 << 21)
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/* MDSCR_EL1 enabling bits */
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#define DBG_MDSCR_KDE (1 << 13)
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#define DBG_MDSCR_MDE (1 << 15)
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#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
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2012-03-05 11:49:33 +00:00
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#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
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/* AArch64 */
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#define DBG_ESR_EVT_HWBP 0x0
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#define DBG_ESR_EVT_HWSS 0x1
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#define DBG_ESR_EVT_HWWP 0x2
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#define DBG_ESR_EVT_BRK 0x6
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2014-01-28 16:50:18 +05:30
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/*
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* Break point instruction encoding
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*/
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2015-07-24 16:37:41 +01:00
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#define BREAK_INSTR_SIZE AARCH64_INSN_SIZE
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2014-01-28 16:50:18 +05:30
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2015-07-24 16:37:46 +01:00
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#define AARCH64_BREAK_KGDB_DYN_DBG \
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(AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5))
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2014-01-28 16:50:18 +05:30
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#define CACHE_FLUSH_IS_SAFE 1
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arm64: Kprobes with single stepping support
Add support for basic kernel probes(kprobes) and jump probes
(jprobes) for ARM64.
Kprobes utilizes software breakpoint and single step debug
exceptions supported on ARM v8.
A software breakpoint is placed at the probe address to trap the
kernel execution into the kprobe handler.
ARM v8 supports enabling single stepping before the break exception
return (ERET), with next PC in exception return address (ELR_EL1). The
kprobe handler prepares an executable memory slot for out-of-line
execution with a copy of the original instruction being probed, and
enables single stepping. The PC is set to the out-of-line slot address
before the ERET. With this scheme, the instruction is executed with the
exact same register context except for the PC (and DAIF) registers.
Debug mask (PSTATE.D) is enabled only when single stepping a recursive
kprobe, e.g.: during kprobes reenter so that probed instruction can be
single stepped within the kprobe handler -exception- context.
The recursion depth of kprobe is always 2, i.e. upon probe re-entry,
any further re-entry is prevented by not calling handlers and the case
counted as a missed kprobe).
Single stepping from the x-o-l slot has a drawback for PC-relative accesses
like branching and symbolic literals access as the offset from the new PC
(slot address) may not be ensured to fit in the immediate value of
the opcode. Such instructions need simulation, so reject
probing them.
Instructions generating exceptions or cpu mode change are rejected
for probing.
Exclusive load/store instructions are rejected too. Additionally, the
code is checked to see if it is inside an exclusive load/store sequence
(code from Pratyush).
System instructions are mostly enabled for stepping, except MSR/MRS
accesses to "DAIF" flags in PSTATE, which are not safe for
probing.
This also changes arch/arm64/include/asm/ptrace.h to use
include/asm-generic/ptrace.h.
Thanks to Steve Capper and Pratyush Anand for several suggested
Changes.
Signed-off-by: Sandeepa Prabhu <sandeepa.s.prabhu@gmail.com>
Signed-off-by: David A. Long <dave.long@linaro.org>
Signed-off-by: Pratyush Anand <panand@redhat.com>
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-07-08 12:35:48 -04:00
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/* kprobes BRK opcodes with ESR encoding */
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2019-02-26 15:06:42 +00:00
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#define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (KPROBES_BRK_IMM << 5))
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2020-11-03 14:49:01 +01:00
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#define BRK64_OPCODE_KPROBES_SS (AARCH64_BREAK_MON | (KPROBES_BRK_SS_IMM << 5))
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2016-11-02 14:40:46 +05:30
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/* uprobes BRK opcodes with ESR encoding */
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2019-02-26 15:06:42 +00:00
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#define BRK64_OPCODE_UPROBES (AARCH64_BREAK_MON | (UPROBES_BRK_IMM << 5))
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arm64: Kprobes with single stepping support
Add support for basic kernel probes(kprobes) and jump probes
(jprobes) for ARM64.
Kprobes utilizes software breakpoint and single step debug
exceptions supported on ARM v8.
A software breakpoint is placed at the probe address to trap the
kernel execution into the kprobe handler.
ARM v8 supports enabling single stepping before the break exception
return (ERET), with next PC in exception return address (ELR_EL1). The
kprobe handler prepares an executable memory slot for out-of-line
execution with a copy of the original instruction being probed, and
enables single stepping. The PC is set to the out-of-line slot address
before the ERET. With this scheme, the instruction is executed with the
exact same register context except for the PC (and DAIF) registers.
Debug mask (PSTATE.D) is enabled only when single stepping a recursive
kprobe, e.g.: during kprobes reenter so that probed instruction can be
single stepped within the kprobe handler -exception- context.
The recursion depth of kprobe is always 2, i.e. upon probe re-entry,
any further re-entry is prevented by not calling handlers and the case
counted as a missed kprobe).
Single stepping from the x-o-l slot has a drawback for PC-relative accesses
like branching and symbolic literals access as the offset from the new PC
(slot address) may not be ensured to fit in the immediate value of
the opcode. Such instructions need simulation, so reject
probing them.
Instructions generating exceptions or cpu mode change are rejected
for probing.
Exclusive load/store instructions are rejected too. Additionally, the
code is checked to see if it is inside an exclusive load/store sequence
(code from Pratyush).
System instructions are mostly enabled for stepping, except MSR/MRS
accesses to "DAIF" flags in PSTATE, which are not safe for
probing.
This also changes arch/arm64/include/asm/ptrace.h to use
include/asm-generic/ptrace.h.
Thanks to Steve Capper and Pratyush Anand for several suggested
Changes.
Signed-off-by: Sandeepa Prabhu <sandeepa.s.prabhu@gmail.com>
Signed-off-by: David A. Long <dave.long@linaro.org>
Signed-off-by: Pratyush Anand <panand@redhat.com>
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-07-08 12:35:48 -04:00
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2012-03-05 11:49:33 +00:00
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/* AArch32 */
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#define DBG_ESR_EVT_BKPT 0x4
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#define DBG_ESR_EVT_VECC 0x5
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#define AARCH32_BREAK_ARM 0x07f001f0
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#define AARCH32_BREAK_THUMB 0xde01
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#define AARCH32_BREAK_THUMB2_LO 0xf7f0
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#define AARCH32_BREAK_THUMB2_HI 0xa000
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#ifndef __ASSEMBLY__
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struct task_struct;
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#define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */
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2013-12-04 05:50:20 +00:00
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#define DBG_HOOK_HANDLED 0
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#define DBG_HOOK_ERROR 1
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struct step_hook {
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struct list_head node;
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arm64: Treat ESR_ELx as a 64-bit register
In the initial release of the ARM Architecture Reference Manual for
ARMv8-A, the ESR_ELx registers were defined as 32-bit registers. This
changed in 2018 with version D.a (ARM DDI 0487D.a) of the architecture,
when they became 64-bit registers, with bits [63:32] defined as RES0. In
version G.a, a new field was added to ESR_ELx, ISS2, which covers bits
[36:32]. This field is used when the Armv8.7 extension FEAT_LS64 is
implemented.
As a result of the evolution of the register width, Linux stores it as
both a 64-bit value and a 32-bit value, which hasn't affected correctness
so far as Linux only uses the lower 32 bits of the register.
Make the register type consistent and always treat it as 64-bit wide. The
register is redefined as an "unsigned long", which is an unsigned
double-word (64-bit quantity) for the LP64 machine (aapcs64 [1], Table 1,
page 14). The type was chosen because "unsigned int" is the most frequent
type for ESR_ELx and because FAR_ELx, which is used together with ESR_ELx
in exception handling, is also declared as "unsigned long". The 64-bit type
also makes adding support for architectural features that use fields above
bit 31 easier in the future.
The KVM hypervisor will receive a similar update in a subsequent patch.
[1] https://github.com/ARM-software/abi-aa/releases/download/2021Q3/aapcs64.pdf
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425114444.368693-4-alexandru.elisei@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-04-25 12:44:42 +01:00
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int (*fn)(struct pt_regs *regs, unsigned long esr);
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2013-12-04 05:50:20 +00:00
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};
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2019-02-26 12:52:47 +00:00
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void register_user_step_hook(struct step_hook *hook);
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void unregister_user_step_hook(struct step_hook *hook);
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void register_kernel_step_hook(struct step_hook *hook);
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void unregister_kernel_step_hook(struct step_hook *hook);
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2013-12-04 05:50:20 +00:00
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struct break_hook {
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struct list_head node;
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arm64: Treat ESR_ELx as a 64-bit register
In the initial release of the ARM Architecture Reference Manual for
ARMv8-A, the ESR_ELx registers were defined as 32-bit registers. This
changed in 2018 with version D.a (ARM DDI 0487D.a) of the architecture,
when they became 64-bit registers, with bits [63:32] defined as RES0. In
version G.a, a new field was added to ESR_ELx, ISS2, which covers bits
[36:32]. This field is used when the Armv8.7 extension FEAT_LS64 is
implemented.
As a result of the evolution of the register width, Linux stores it as
both a 64-bit value and a 32-bit value, which hasn't affected correctness
so far as Linux only uses the lower 32 bits of the register.
Make the register type consistent and always treat it as 64-bit wide. The
register is redefined as an "unsigned long", which is an unsigned
double-word (64-bit quantity) for the LP64 machine (aapcs64 [1], Table 1,
page 14). The type was chosen because "unsigned int" is the most frequent
type for ESR_ELx and because FAR_ELx, which is used together with ESR_ELx
in exception handling, is also declared as "unsigned long". The 64-bit type
also makes adding support for architectural features that use fields above
bit 31 easier in the future.
The KVM hypervisor will receive a similar update in a subsequent patch.
[1] https://github.com/ARM-software/abi-aa/releases/download/2021Q3/aapcs64.pdf
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425114444.368693-4-alexandru.elisei@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-04-25 12:44:42 +01:00
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int (*fn)(struct pt_regs *regs, unsigned long esr);
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2019-02-26 12:52:47 +00:00
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u16 imm;
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u16 mask; /* These bits are ignored when comparing with imm */
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2013-12-04 05:50:20 +00:00
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};
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2019-02-26 12:52:47 +00:00
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void register_user_break_hook(struct break_hook *hook);
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void unregister_user_break_hook(struct break_hook *hook);
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void register_kernel_break_hook(struct break_hook *hook);
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void unregister_kernel_break_hook(struct break_hook *hook);
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2013-12-04 05:50:20 +00:00
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2012-03-05 11:49:33 +00:00
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u8 debug_monitors_arch(void);
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2015-07-27 18:36:54 +01:00
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enum dbg_active_el {
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2014-05-07 12:13:14 +01:00
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DBG_ACTIVE_EL0 = 0,
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DBG_ACTIVE_EL1,
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};
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2015-07-27 18:36:54 +01:00
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void enable_debug_monitors(enum dbg_active_el el);
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void disable_debug_monitors(enum dbg_active_el el);
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2012-03-05 11:49:33 +00:00
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void user_rewind_single_step(struct task_struct *task);
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void user_fastforward_single_step(struct task_struct *task);
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arm64: ptrace: Override SPSR.SS when single-stepping is enabled
Luis reports that, when reverse debugging with GDB, single-step does not
function as expected on arm64:
| I've noticed, under very specific conditions, that a PTRACE_SINGLESTEP
| request by GDB won't execute the underlying instruction. As a consequence,
| the PC doesn't move, but we return a SIGTRAP just like we would for a
| regular successful PTRACE_SINGLESTEP request.
The underlying problem is that when the CPU register state is restored
as part of a reverse step, the SPSR.SS bit is cleared and so the hardware
single-step state can transition to the "active-pending" state, causing
an unexpected step exception to be taken immediately if a step operation
is attempted.
In hindsight, we probably shouldn't have exposed SPSR.SS in the pstate
accessible by the GPR regset, but it's a bit late for that now. Instead,
simply prevent userspace from configuring the bit to a value which is
inconsistent with the TIF_SINGLESTEP state for the task being traced.
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Keno Fischer <keno@juliacomputing.com>
Link: https://lore.kernel.org/r/1eed6d69-d53d-9657-1fc9-c089be07f98c@linaro.org
Reported-by: Luis Machado <luis.machado@linaro.org>
Tested-by: Luis Machado <luis.machado@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
2020-02-13 12:06:26 +00:00
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void user_regs_reset_single_step(struct user_pt_regs *regs,
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struct task_struct *task);
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2012-03-05 11:49:33 +00:00
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void kernel_enable_single_step(struct pt_regs *regs);
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void kernel_disable_single_step(void);
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int kernel_active_single_step(void);
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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int reinstall_suspended_bps(struct pt_regs *regs);
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#else
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static inline int reinstall_suspended_bps(struct pt_regs *regs)
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{
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return -ENODEV;
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}
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#endif
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2013-03-16 08:48:13 +00:00
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int aarch32_break_handler(struct pt_regs *regs);
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2020-05-13 16:06:37 -07:00
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void debug_traps_init(void);
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2012-03-05 11:49:33 +00:00
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#endif /* __ASSEMBLY */
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#endif /* __ASM_DEBUG_MONITORS_H */
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