2019-06-03 05:44:50 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-03-05 11:49:28 +00:00
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/*
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* Based on arch/arm/include/asm/thread_info.h
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*
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* Copyright (C) 2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_THREAD_INFO_H
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#define __ASM_THREAD_INFO_H
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#include <linux/compiler.h>
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#ifndef __ASSEMBLY__
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struct task_struct;
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2017-07-14 15:39:21 +00:00
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#include <asm/memory.h>
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2016-11-03 20:23:05 +00:00
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#include <asm/stack_pointer.h>
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2012-03-05 11:49:28 +00:00
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#include <asm/types.h>
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/*
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* low level task data that entry.S needs immediate access to.
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*/
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struct thread_info {
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unsigned long flags; /* low level flags */
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2016-07-01 15:53:00 +00:00
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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u64 ttbr0; /* saved TTBR0_EL1 */
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#endif
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2018-09-20 09:26:40 +00:00
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union {
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u64 preempt_count; /* 0 => preemptible, <0 => bug */
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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u32 need_resched;
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u32 count;
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#else
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u32 count;
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u32 need_resched;
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#endif
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} preempt;
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};
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2020-04-27 16:00:16 +00:00
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#ifdef CONFIG_SHADOW_CALL_STACK
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void *scs_base;
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2020-05-15 13:11:05 +00:00
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void *scs_sp;
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2020-04-27 16:00:16 +00:00
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#endif
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2021-09-14 12:10:29 +00:00
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u32 cpu;
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2012-03-05 11:49:28 +00:00
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};
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#define thread_saved_pc(tsk) \
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((unsigned long)(tsk->thread.cpu_context.pc))
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#define thread_saved_sp(tsk) \
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((unsigned long)(tsk->thread.cpu_context.sp))
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#define thread_saved_fp(tsk) \
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((unsigned long)(tsk->thread.cpu_context.fp))
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2017-08-20 10:20:48 +00:00
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void arch_setup_new_exec(void);
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#define arch_setup_new_exec arch_setup_new_exec
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arm64/sve: Core task context handling
This patch adds the core support for switching and managing the SVE
architectural state of user tasks.
Calls to the existing FPSIMD low-level save/restore functions are
factored out as new functions task_fpsimd_{save,load}(), since SVE
now dynamically may or may not need to be handled at these points
depending on the kernel configuration, hardware features discovered
at boot, and the runtime state of the task. To make these
decisions as fast as possible, const cpucaps are used where
feasible, via the system_supports_sve() helper.
The SVE registers are only tracked for threads that have explicitly
used SVE, indicated by the new thread flag TIF_SVE. Otherwise, the
FPSIMD view of the architectural state is stored in
thread.fpsimd_state as usual.
When in use, the SVE registers are not stored directly in
thread_struct due to their potentially large and variable size.
Because the task_struct slab allocator must be configured very
early during kernel boot, it is also tricky to configure it
correctly to match the maximum vector length provided by the
hardware, since this depends on examining secondary CPUs as well as
the primary. Instead, a pointer sve_state in thread_struct points
to a dynamically allocated buffer containing the SVE register data,
and code is added to allocate and free this buffer at appropriate
times.
TIF_SVE is set when taking an SVE access trap from userspace, if
suitable hardware support has been detected. This enables SVE for
the thread: a subsequent return to userspace will disable the trap
accordingly. If such a trap is taken without sufficient system-
wide hardware support, SIGILL is sent to the thread instead as if
an undefined instruction had been executed: this may happen if
userspace tries to use SVE in a system where not all CPUs support
it for example.
The kernel will clear TIF_SVE and disable SVE for the thread
whenever an explicit syscall is made by userspace. For backwards
compatibility reasons and conformance with the spirit of the base
AArch64 procedure call standard, the subset of the SVE register
state that aliases the FPSIMD registers is still preserved across a
syscall even if this happens. The remainder of the SVE register
state logically becomes zero at syscall entry, though the actual
zeroing work is currently deferred until the thread next tries to
use SVE, causing another trap to the kernel. This implementation
is suboptimal: in the future, the fastpath case may be optimised
to zero the registers in-place and leave SVE enabled for the task,
where beneficial.
TIF_SVE is also cleared in the following slowpath cases, which are
taken as reasonable hints that the task may no longer use SVE:
* exec
* fork and clone
Code is added to sync data between thread.fpsimd_state and
thread.sve_state whenever enabling/disabling SVE, in a manner
consistent with the SVE architectural programmer's model.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
[will: added #include to fix allnoconfig build]
[will: use enable_daif in do_sve_acc]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-10-31 15:51:05 +00:00
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void arch_release_task_struct(struct task_struct *tsk);
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2021-03-24 06:54:58 +00:00
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int arch_dup_task_struct(struct task_struct *dst,
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struct task_struct *src);
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arm64/sve: Core task context handling
This patch adds the core support for switching and managing the SVE
architectural state of user tasks.
Calls to the existing FPSIMD low-level save/restore functions are
factored out as new functions task_fpsimd_{save,load}(), since SVE
now dynamically may or may not need to be handled at these points
depending on the kernel configuration, hardware features discovered
at boot, and the runtime state of the task. To make these
decisions as fast as possible, const cpucaps are used where
feasible, via the system_supports_sve() helper.
The SVE registers are only tracked for threads that have explicitly
used SVE, indicated by the new thread flag TIF_SVE. Otherwise, the
FPSIMD view of the architectural state is stored in
thread.fpsimd_state as usual.
When in use, the SVE registers are not stored directly in
thread_struct due to their potentially large and variable size.
Because the task_struct slab allocator must be configured very
early during kernel boot, it is also tricky to configure it
correctly to match the maximum vector length provided by the
hardware, since this depends on examining secondary CPUs as well as
the primary. Instead, a pointer sve_state in thread_struct points
to a dynamically allocated buffer containing the SVE register data,
and code is added to allocate and free this buffer at appropriate
times.
TIF_SVE is set when taking an SVE access trap from userspace, if
suitable hardware support has been detected. This enables SVE for
the thread: a subsequent return to userspace will disable the trap
accordingly. If such a trap is taken without sufficient system-
wide hardware support, SIGILL is sent to the thread instead as if
an undefined instruction had been executed: this may happen if
userspace tries to use SVE in a system where not all CPUs support
it for example.
The kernel will clear TIF_SVE and disable SVE for the thread
whenever an explicit syscall is made by userspace. For backwards
compatibility reasons and conformance with the spirit of the base
AArch64 procedure call standard, the subset of the SVE register
state that aliases the FPSIMD registers is still preserved across a
syscall even if this happens. The remainder of the SVE register
state logically becomes zero at syscall entry, though the actual
zeroing work is currently deferred until the thread next tries to
use SVE, causing another trap to the kernel. This implementation
is suboptimal: in the future, the fastpath case may be optimised
to zero the registers in-place and leave SVE enabled for the task,
where beneficial.
TIF_SVE is also cleared in the following slowpath cases, which are
taken as reasonable hints that the task may no longer use SVE:
* exec
* fork and clone
Code is added to sync data between thread.fpsimd_state and
thread.sve_state whenever enabling/disabling SVE, in a manner
consistent with the SVE architectural programmer's model.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
[will: added #include to fix allnoconfig build]
[will: use enable_daif in do_sve_acc]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-10-31 15:51:05 +00:00
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2012-03-05 11:49:28 +00:00
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#endif
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2019-07-31 13:35:20 +00:00
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#define TIF_SIGPENDING 0 /* signal pending */
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#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
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2012-03-05 11:49:28 +00:00
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#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
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2014-05-08 09:20:23 +00:00
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#define TIF_FOREIGN_FPSTATE 3 /* CPU's FP state is not current's */
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2016-11-02 09:10:46 +00:00
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#define TIF_UPROBE 4 /* uprobe breakpoint or singlestep */
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2020-12-02 13:15:56 +00:00
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#define TIF_MTE_ASYNC_FAULT 5 /* MTE Asynchronous Tag Check Fault */
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2020-12-16 21:32:48 +00:00
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#define TIF_NOTIFY_SIGNAL 6 /* signal notifications exist */
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2019-07-31 13:35:20 +00:00
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#define TIF_SYSCALL_TRACE 8 /* syscall trace active */
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#define TIF_SYSCALL_AUDIT 9 /* syscall auditing */
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#define TIF_SYSCALL_TRACEPOINT 10 /* syscall tracepoint for ftrace */
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#define TIF_SECCOMP 11 /* syscall secure computing */
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#define TIF_SYSCALL_EMU 12 /* syscall emulation active */
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2012-03-05 11:49:28 +00:00
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#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
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#define TIF_FREEZE 19
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#define TIF_RESTORE_SIGMASK 20
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#define TIF_SINGLESTEP 21
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#define TIF_32BIT 22 /* 32bit process */
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arm64/sve: Core task context handling
This patch adds the core support for switching and managing the SVE
architectural state of user tasks.
Calls to the existing FPSIMD low-level save/restore functions are
factored out as new functions task_fpsimd_{save,load}(), since SVE
now dynamically may or may not need to be handled at these points
depending on the kernel configuration, hardware features discovered
at boot, and the runtime state of the task. To make these
decisions as fast as possible, const cpucaps are used where
feasible, via the system_supports_sve() helper.
The SVE registers are only tracked for threads that have explicitly
used SVE, indicated by the new thread flag TIF_SVE. Otherwise, the
FPSIMD view of the architectural state is stored in
thread.fpsimd_state as usual.
When in use, the SVE registers are not stored directly in
thread_struct due to their potentially large and variable size.
Because the task_struct slab allocator must be configured very
early during kernel boot, it is also tricky to configure it
correctly to match the maximum vector length provided by the
hardware, since this depends on examining secondary CPUs as well as
the primary. Instead, a pointer sve_state in thread_struct points
to a dynamically allocated buffer containing the SVE register data,
and code is added to allocate and free this buffer at appropriate
times.
TIF_SVE is set when taking an SVE access trap from userspace, if
suitable hardware support has been detected. This enables SVE for
the thread: a subsequent return to userspace will disable the trap
accordingly. If such a trap is taken without sufficient system-
wide hardware support, SIGILL is sent to the thread instead as if
an undefined instruction had been executed: this may happen if
userspace tries to use SVE in a system where not all CPUs support
it for example.
The kernel will clear TIF_SVE and disable SVE for the thread
whenever an explicit syscall is made by userspace. For backwards
compatibility reasons and conformance with the spirit of the base
AArch64 procedure call standard, the subset of the SVE register
state that aliases the FPSIMD registers is still preserved across a
syscall even if this happens. The remainder of the SVE register
state logically becomes zero at syscall entry, though the actual
zeroing work is currently deferred until the thread next tries to
use SVE, causing another trap to the kernel. This implementation
is suboptimal: in the future, the fastpath case may be optimised
to zero the registers in-place and leave SVE enabled for the task,
where beneficial.
TIF_SVE is also cleared in the following slowpath cases, which are
taken as reasonable hints that the task may no longer use SVE:
* exec
* fork and clone
Code is added to sync data between thread.fpsimd_state and
thread.sve_state whenever enabling/disabling SVE, in a manner
consistent with the SVE architectural programmer's model.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
[will: added #include to fix allnoconfig build]
[will: use enable_daif in do_sve_acc]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-10-31 15:51:05 +00:00
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#define TIF_SVE 23 /* Scalable Vector Extension in use */
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2021-10-19 17:22:14 +00:00
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#define TIF_SVE_VL_INHERIT 24 /* Inherit SVE vl_onexec across exec */
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2018-05-29 12:11:13 +00:00
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#define TIF_SSBD 25 /* Wants SSB mitigation */
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2019-07-23 17:58:39 +00:00
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#define TIF_TAGGED_ADDR 26 /* Allow tagged user addresses */
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2012-03-05 11:49:28 +00:00
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#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
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#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
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2014-05-08 09:20:23 +00:00
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#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE)
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2014-04-30 09:51:29 +00:00
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#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
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#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
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#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
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#define _TIF_SECCOMP (1 << TIF_SECCOMP)
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2019-05-23 09:06:18 +00:00
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#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
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2016-11-02 09:10:46 +00:00
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#define _TIF_UPROBE (1 << TIF_UPROBE)
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2020-07-02 20:16:20 +00:00
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#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
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2012-03-05 11:49:28 +00:00
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#define _TIF_32BIT (1 << TIF_32BIT)
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arm64/sve: Core task context handling
This patch adds the core support for switching and managing the SVE
architectural state of user tasks.
Calls to the existing FPSIMD low-level save/restore functions are
factored out as new functions task_fpsimd_{save,load}(), since SVE
now dynamically may or may not need to be handled at these points
depending on the kernel configuration, hardware features discovered
at boot, and the runtime state of the task. To make these
decisions as fast as possible, const cpucaps are used where
feasible, via the system_supports_sve() helper.
The SVE registers are only tracked for threads that have explicitly
used SVE, indicated by the new thread flag TIF_SVE. Otherwise, the
FPSIMD view of the architectural state is stored in
thread.fpsimd_state as usual.
When in use, the SVE registers are not stored directly in
thread_struct due to their potentially large and variable size.
Because the task_struct slab allocator must be configured very
early during kernel boot, it is also tricky to configure it
correctly to match the maximum vector length provided by the
hardware, since this depends on examining secondary CPUs as well as
the primary. Instead, a pointer sve_state in thread_struct points
to a dynamically allocated buffer containing the SVE register data,
and code is added to allocate and free this buffer at appropriate
times.
TIF_SVE is set when taking an SVE access trap from userspace, if
suitable hardware support has been detected. This enables SVE for
the thread: a subsequent return to userspace will disable the trap
accordingly. If such a trap is taken without sufficient system-
wide hardware support, SIGILL is sent to the thread instead as if
an undefined instruction had been executed: this may happen if
userspace tries to use SVE in a system where not all CPUs support
it for example.
The kernel will clear TIF_SVE and disable SVE for the thread
whenever an explicit syscall is made by userspace. For backwards
compatibility reasons and conformance with the spirit of the base
AArch64 procedure call standard, the subset of the SVE register
state that aliases the FPSIMD registers is still preserved across a
syscall even if this happens. The remainder of the SVE register
state logically becomes zero at syscall entry, though the actual
zeroing work is currently deferred until the thread next tries to
use SVE, causing another trap to the kernel. This implementation
is suboptimal: in the future, the fastpath case may be optimised
to zero the registers in-place and leave SVE enabled for the task,
where beneficial.
TIF_SVE is also cleared in the following slowpath cases, which are
taken as reasonable hints that the task may no longer use SVE:
* exec
* fork and clone
Code is added to sync data between thread.fpsimd_state and
thread.sve_state whenever enabling/disabling SVE, in a manner
consistent with the SVE architectural programmer's model.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
[will: added #include to fix allnoconfig build]
[will: use enable_daif in do_sve_acc]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-10-31 15:51:05 +00:00
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#define _TIF_SVE (1 << TIF_SVE)
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2019-09-16 10:51:17 +00:00
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#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT)
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2020-10-23 02:09:23 +00:00
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#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL)
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2012-03-05 11:49:28 +00:00
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#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
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2016-11-02 09:10:46 +00:00
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_TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \
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2020-12-16 20:33:35 +00:00
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_TIF_UPROBE | _TIF_MTE_ASYNC_FAULT | \
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2020-10-23 02:09:23 +00:00
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_TIF_NOTIFY_SIGNAL)
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2012-03-05 11:49:28 +00:00
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2014-04-30 09:51:29 +00:00
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#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
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2014-05-30 19:34:15 +00:00
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_TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \
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2020-01-28 12:50:32 +00:00
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_TIF_SYSCALL_EMU)
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2012-03-05 11:49:28 +00:00
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2020-04-27 16:00:16 +00:00
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#ifdef CONFIG_SHADOW_CALL_STACK
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#define INIT_SCS \
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.scs_base = init_shadow_call_stack, \
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2020-05-15 13:11:05 +00:00
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.scs_sp = init_shadow_call_stack,
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2020-04-27 16:00:16 +00:00
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#else
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#define INIT_SCS
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#endif
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2018-05-24 14:54:30 +00:00
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.flags = _TIF_FOREIGN_FPSTATE, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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2020-04-27 16:00:16 +00:00
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INIT_SCS \
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2018-05-24 14:54:30 +00:00
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}
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2012-03-05 11:49:28 +00:00
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#endif /* __ASM_THREAD_INFO_H */
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