251 lines
8.5 KiB
C
251 lines
8.5 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCE_HWSEQ_H__
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#define __DCE_HWSEQ_H__
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#include "hw_sequencer.h"
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#define HWSEQ_DCEF_REG_LIST_DCE8() \
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.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
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.DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
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.DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
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.DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
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.DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
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.DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
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#define HWSEQ_DCEF_REG_LIST() \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
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SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
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#define HWSEQ_BLND_REG_LIST() \
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SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
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SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
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SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
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SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
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SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
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SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
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SRII(BLND_CONTROL, BLND, 0), \
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SRII(BLND_CONTROL, BLND, 1), \
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SRII(BLND_CONTROL, BLND, 2), \
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SRII(BLND_CONTROL, BLND, 3), \
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SRII(BLND_CONTROL, BLND, 4), \
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SRII(BLND_CONTROL, BLND, 5)
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#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
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SRII(PIXEL_RATE_CNTL, blk, 0), \
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SRII(PIXEL_RATE_CNTL, blk, 1), \
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SRII(PIXEL_RATE_CNTL, blk, 2), \
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SRII(PIXEL_RATE_CNTL, blk, 3), \
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SRII(PIXEL_RATE_CNTL, blk, 4), \
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SRII(PIXEL_RATE_CNTL, blk, 5)
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#define HWSEQ_PHYPLL_REG_LIST(blk) \
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SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
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SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
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SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
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SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
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SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
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SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
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#define HWSEQ_DCE11_REG_LIST_BASE() \
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SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
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SR(DCFEV_CLOCK_CONTROL), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
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SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
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SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
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SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
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SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
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SRII(BLND_CONTROL, BLND, 0),\
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SRII(BLND_CONTROL, BLND, 1),\
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SR(BLNDV_CONTROL),\
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HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
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#define HWSEQ_DCE8_REG_LIST() \
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HWSEQ_DCEF_REG_LIST_DCE8(), \
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HWSEQ_BLND_REG_LIST(), \
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HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
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#define HWSEQ_DCE10_REG_LIST() \
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HWSEQ_DCEF_REG_LIST(), \
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HWSEQ_BLND_REG_LIST(), \
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HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
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#define HWSEQ_ST_REG_LIST() \
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HWSEQ_DCE11_REG_LIST_BASE(), \
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.DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
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.CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
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.BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
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.BLND_CONTROL[2] = mmBLNDV_CONTROL,
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#define HWSEQ_CZ_REG_LIST() \
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HWSEQ_DCE11_REG_LIST_BASE(), \
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SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
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SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
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SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
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SRII(BLND_CONTROL, BLND, 2), \
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.DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
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.CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
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.BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
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.BLND_CONTROL[3] = mmBLNDV_CONTROL
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#define HWSEQ_DCE112_REG_LIST() \
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HWSEQ_DCE10_REG_LIST(), \
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HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
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HWSEQ_PHYPLL_REG_LIST(CRTC)
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struct dce_hwseq_registers {
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uint32_t DCFE_CLOCK_CONTROL[6];
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uint32_t DCFEV_CLOCK_CONTROL;
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uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
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uint32_t BLND_V_UPDATE_LOCK[6];
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uint32_t BLND_CONTROL[6];
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uint32_t BLNDV_CONTROL;
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uint32_t CRTC_H_BLANK_START_END[6];
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uint32_t PIXEL_RATE_CNTL[6];
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uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
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};
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/* set field name */
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#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
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.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
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#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
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.field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
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#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
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HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
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SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
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#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
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HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
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HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
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HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
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HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
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HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
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#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
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HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
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HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
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#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
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HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
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HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
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#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
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.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
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HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
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HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
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HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
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#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
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HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
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HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
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HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
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#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
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HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
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SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
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HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
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#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
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HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
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HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
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#define HWSEQ_REG_FIED_LIST(type) \
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type DCFE_CLOCK_ENABLE; \
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type DCFEV_CLOCK_ENABLE; \
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type DC_MEM_GLOBAL_PWR_REQ_DIS; \
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type BLND_DCP_GRPH_V_UPDATE_LOCK; \
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type BLND_SCL_V_UPDATE_LOCK; \
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type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
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type BLND_BLND_V_UPDATE_LOCK; \
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type BLND_V_UPDATE_LOCK_MODE; \
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type BLND_FEEDTHROUGH_EN; \
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type BLND_ALPHA_MODE; \
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type BLND_MODE; \
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type BLND_MULTIPLIED_MODE; \
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type DP_DTO0_ENABLE; \
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type PIXEL_RATE_SOURCE; \
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type PHYPLL_PIXEL_RATE_SOURCE; \
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type PIXEL_RATE_PLL_SOURCE; \
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struct dce_hwseq_shift {
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HWSEQ_REG_FIED_LIST(uint8_t)
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};
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struct dce_hwseq_mask {
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HWSEQ_REG_FIED_LIST(uint32_t)
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};
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struct dce_hwseq_wa {
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bool blnd_crtc_trigger;
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};
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struct dce_hwseq {
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struct dc_context *ctx;
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const struct dce_hwseq_registers *regs;
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const struct dce_hwseq_shift *shifts;
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const struct dce_hwseq_mask *masks;
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struct dce_hwseq_wa wa;
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};
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enum blnd_mode {
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BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
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BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
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BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
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};
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void dce_enable_fe_clock(struct dce_hwseq *hwss,
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unsigned int inst, bool enable);
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void dce_pipe_control_lock(struct dce_hwseq *hws,
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unsigned int blnd_inst,
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enum pipe_lock_control control_mask,
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bool lock);
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void dce_set_blender_mode(struct dce_hwseq *hws,
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unsigned int blnd_inst, enum blnd_mode mode);
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void dce_clock_gating_power_up(struct dce_hwseq *hws,
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bool enable);
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void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
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struct clock_source *clk_src,
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unsigned int tg_inst);
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#endif /*__DCE_HWSEQ_H__*/
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