linux/include/dt-bindings/clock/gxbb-clkc.h

/*
 * GXBB clock tree IDs
 */

#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H

#define CLKID_CPUCLK		1
#define CLKID_FCLK_DIV2		4
#define CLKID_CLK81		12
#define CLKID_ETH		36
#define CLKID_SD_EMMC_A		94
#define CLKID_SD_EMMC_B		95
#define CLKID_SD_EMMC_C		96

#endif /* __GXBB_CLKC_H */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00			`/*`
			`* GXBB clock tree IDs`
			`*/`

			`#ifndef __GXBB_CLKC_H`
			`#define __GXBB_CLKC_H`

			`#define CLKID_CPUCLK 1`
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-08-02 21:40:11 +00:00			`#define CLKID_FCLK_DIV2 4`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00			`#define CLKID_CLK81 12`
			`#define CLKID_ETH 36`
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-08-02 21:40:11 +00:00			`#define CLKID_SD_EMMC_A 94`
			`#define CLKID_SD_EMMC_B 95`
			`#define CLKID_SD_EMMC_C 96`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00
			`#endif /* __GXBB_CLKC_H */`