linux/arch/arm/mm/pabort-v7.S

#include <linux/linkage.h>
#include <asm/assembler.h>

/*
 * Function: v6_pabort
 *
 * Params  : r0 = address of aborted instruction
 *
 * Returns : r0 = address of abort
 *	   : r1 = IFSR
 *
 * Purpose : obtain information about current prefetch abort.
 */

	.align	5
ENTRY(v7_pabort)
	mrc	p15, 0, r0, c6, c0, 2		@ get IFAR
	mrc	p15, 0, r1, c5, c0, 1		@ get IFSR
	mov	pc, lr
ENDPROC(v7_pabort)
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2009-09-25 12:39:47 +00:00			`#include <linux/linkage.h>`
			`#include <asm/assembler.h>`

			`/*`
			`* Function: v6_pabort`
			`*`
			`* Params : r0 = address of aborted instruction`
			`*`
			`* Returns : r0 = address of abort`
			`* : r1 = IFSR`
			`*`
			`* Purpose : obtain information about current prefetch abort.`
			`*/`

			`.align 5`
			`ENTRY(v7_pabort)`
			`mrc p15, 0, r0, c6, c0, 2 @ get IFAR`
			`mrc p15, 0, r1, c5, c0, 1 @ get IFSR`
			`mov pc, lr`
			`ENDPROC(v7_pabort)`