2019-06-20 00:13:43 +00:00
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/* SPDX-License-Identifier: MIT */
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2013-01-14 22:33:25 +00:00
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#ifndef __NVBIOS_VOLT_H__
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#define __NVBIOS_VOLT_H__
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2015-09-09 01:05:50 +00:00
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enum nvbios_volt_type {
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NVBIOS_VOLT_GPIO = 0,
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NVBIOS_VOLT_PWM,
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};
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2013-01-14 22:33:25 +00:00
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struct nvbios_volt {
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2015-09-09 01:05:50 +00:00
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enum nvbios_volt_type type;
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2013-01-14 22:33:25 +00:00
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u32 min;
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u32 max;
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u32 base;
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2015-09-09 01:05:50 +00:00
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/* GPIO mode */
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2016-07-12 19:36:08 +00:00
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bool ranged;
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u8 vidmask;
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s16 step;
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2015-09-09 01:05:50 +00:00
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/* PWM mode */
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u32 pwm_freq;
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u32 pwm_range;
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2013-01-14 22:33:25 +00:00
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};
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2016-11-18 01:18:45 +00:00
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u32 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
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u32 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
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2013-01-14 22:33:25 +00:00
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struct nvbios_volt *);
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struct nvbios_volt_entry {
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u32 voltage;
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u8 vid;
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};
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2016-11-18 01:18:45 +00:00
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u32 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len);
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u32 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len,
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2013-01-14 22:33:25 +00:00
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struct nvbios_volt_entry *);
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#endif
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