linux/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h

/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_SEC2_H__
#define __NVKM_SEC2_H__
#include <core/engine.h>

struct nvkm_sec2 {
	struct nvkm_engine engine;
	u32 addr;

	struct nvkm_falcon *falcon;
	struct nvkm_msgqueue *queue;
	struct work_struct work;
};

int gp102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **);
int tu102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **);
#endif
drm/nouveau: fix bogus GPL-2 license header The bulk SPDX addition made all these files into GPL-2.0 licensed files. However the remainder of the project is MIT-licensed, these files (primarily header files) were simply missing the boiler plate and got caught up in the global update. Fixes: b24413180f5 (License cleanup: add SPDX GPL-2.0 license identifier to files with no license) Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Emil Velikov <emil.l.velikov@gmail.com> Acked-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2019-06-20 00:13:43 +00:00			`/* SPDX-License-Identifier: MIT */`
drm/nouveau/core: add SEC2 engine SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2017-02-23 09:41:41 +00:00			`#ifndef __NVKM_SEC2_H__`
			`#define __NVKM_SEC2_H__`
			`#include <core/engine.h>`

			`struct nvkm_sec2 {`
			`struct nvkm_engine engine;`
drm/nouveau/sec2: utilise engine PRI address from TOP Turing has its SEC2 instance in an alternate location, and this avoids needing to duplicate the code here for it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2019-02-12 12:28:13 +00:00			`u32 addr;`

drm/nouveau/core: add SEC2 engine SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2017-02-23 09:41:41 +00:00			`struct nvkm_falcon *falcon;`
			`struct nvkm_msgqueue *queue;`
			`struct work_struct work;`
			`};`

			`int gp102_sec2_new(struct nvkm_device , int, struct nvkm_sec2 *);`
drm/nouveau/sec2/tu102-: instantiate SEC2 falcon Required for ACR. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2019-02-12 12:28:13 +00:00			`int tu102_sec2_new(struct nvkm_device , int, struct nvkm_sec2 *);`
drm/nouveau/core: add SEC2 engine SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2017-02-23 09:41:41 +00:00			`#endif`