2008-08-19 08:08:40 +00:00
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/*
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* OMAP2/3 powerdomain control
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*
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2010-01-27 03:12:59 +00:00
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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2010-12-22 03:01:20 +00:00
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* Copyright (C) 2007-2010 Nokia Corporation
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2008-08-19 08:08:40 +00:00
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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2010-12-22 03:01:20 +00:00
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*
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* XXX This should be moved to the mach-omap2/ directory at the earliest
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* opportunity.
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2008-08-19 08:08:40 +00:00
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*/
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2010-12-22 03:01:20 +00:00
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#ifndef ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN
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#define ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN
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2008-08-19 08:08:40 +00:00
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#include <linux/types.h>
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#include <linux/list.h>
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#include <asm/atomic.h>
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2009-10-20 16:40:47 +00:00
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#include <plat/cpu.h>
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2008-08-19 08:08:40 +00:00
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/* Powerdomain basic power states */
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#define PWRDM_POWER_OFF 0x0
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#define PWRDM_POWER_RET 0x1
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#define PWRDM_POWER_INACTIVE 0x2
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#define PWRDM_POWER_ON 0x3
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2009-12-08 23:33:12 +00:00
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#define PWRDM_MAX_PWRSTS 4
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2008-08-19 08:08:40 +00:00
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/* Powerdomain allowable state bitfields */
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2010-05-19 02:24:01 +00:00
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#define PWRSTS_ON (1 << PWRDM_POWER_ON)
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2010-09-27 20:02:56 +00:00
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#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
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2008-08-19 08:08:40 +00:00
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#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
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(1 << PWRDM_POWER_ON))
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#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
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(1 << PWRDM_POWER_RET))
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2010-01-27 03:12:52 +00:00
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#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
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(1 << PWRDM_POWER_ON))
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2008-08-19 08:08:40 +00:00
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#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
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[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 00:09:37 +00:00
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/* Powerdomain flags */
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#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
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2009-12-08 23:33:15 +00:00
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#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
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* in MEM bank 1 position. This is
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* true for OMAP3430
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*/
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2010-05-19 02:24:03 +00:00
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#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
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* support to transition from a
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* sleep state to a lower sleep
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* state without waking up the
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* powerdomain
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*/
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[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 00:09:37 +00:00
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2008-08-19 08:08:40 +00:00
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/*
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2010-01-27 03:12:52 +00:00
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* Number of memory banks that are power-controllable. On OMAP4430, the
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* maximum is 5.
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2008-08-19 08:08:40 +00:00
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*/
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2010-01-27 03:12:52 +00:00
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#define PWRDM_MAX_MEM_BANKS 5
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2008-08-19 08:08:40 +00:00
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2008-08-19 08:08:44 +00:00
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/*
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* Maximum number of clockdomains that can be associated with a powerdomain.
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2010-01-27 03:12:52 +00:00
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* CORE powerdomain on OMAP4 is the worst case
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2008-08-19 08:08:44 +00:00
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*/
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2010-01-27 03:12:52 +00:00
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#define PWRDM_MAX_CLKDMS 9
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2008-08-19 08:08:44 +00:00
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2008-08-19 08:08:40 +00:00
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/* XXX A completely arbitrary number. What is reasonable here? */
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#define PWRDM_TRANSITION_BAILOUT 100000
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2008-08-19 08:08:44 +00:00
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struct clockdomain;
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2008-08-19 08:08:40 +00:00
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struct powerdomain;
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2010-01-27 03:13:02 +00:00
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/**
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* struct powerdomain - OMAP powerdomain
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* @name: Powerdomain name
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* @omap_chip: represents the OMAP chip types containing this pwrdm
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* @prcm_offs: the address offset from CM_BASE/PRM_BASE
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* @pwrsts: Possible powerdomain power states
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* @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
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* @flags: Powerdomain flags
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* @banks: Number of software-controllable memory banks in this powerdomain
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* @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
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* @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
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* @pwrdm_clkdms: Clockdomains in this powerdomain
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* @node: list_head linking all powerdomains
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* @state:
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* @state_counter:
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* @timer:
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* @state_timer:
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*/
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2008-08-19 08:08:40 +00:00
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struct powerdomain {
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const char *name;
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const struct omap_chip_id omap_chip;
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2010-01-27 03:13:01 +00:00
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const s16 prcm_offs;
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2008-08-19 08:08:40 +00:00
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const u8 pwrsts;
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const u8 pwrsts_logic_ret;
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 00:09:37 +00:00
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const u8 flags;
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2008-08-19 08:08:40 +00:00
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const u8 banks;
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const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
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const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
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2008-08-19 08:08:44 +00:00
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struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
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2008-08-19 08:08:40 +00:00
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struct list_head node;
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2008-10-15 14:48:43 +00:00
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int state;
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2009-12-08 23:33:12 +00:00
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unsigned state_counter[PWRDM_MAX_PWRSTS];
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2010-02-24 19:05:50 +00:00
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unsigned ret_logic_off_counter;
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unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
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2008-10-15 15:13:48 +00:00
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#ifdef CONFIG_PM_DEBUG
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s64 timer;
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2009-12-08 23:33:12 +00:00
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s64 state_timer[PWRDM_MAX_PWRSTS];
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2008-10-15 15:13:48 +00:00
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#endif
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2008-08-19 08:08:40 +00:00
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};
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2010-12-22 03:01:18 +00:00
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/**
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* struct pwrdm_ops - Arch specfic function implementations
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* @pwrdm_set_next_pwrst: Set the target power state for a pd
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* @pwrdm_read_next_pwrst: Read the target power state set for a pd
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* @pwrdm_read_pwrst: Read the current power state of a pd
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* @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
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* @pwrdm_set_logic_retst: Set the logic state in RET for a pd
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* @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
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* @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
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* @pwrdm_read_logic_pwrst: Read the current logic state of a pd
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* @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
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* @pwrdm_read_logic_retst: Read the logic state in RET for a pd
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* @pwrdm_read_mem_pwrst: Read the current memory state of a pd
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* @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
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* @pwrdm_read_mem_retst: Read the memory state in RET for a pd
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* @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
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* @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
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* @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
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* @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
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* @pwrdm_wait_transition: Wait for a pd state transition to complete
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*/
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struct pwrdm_ops {
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int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
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int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
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int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
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int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
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int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
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int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
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};
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2008-08-19 08:08:40 +00:00
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2010-12-22 03:01:17 +00:00
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void pwrdm_fw_init(void);
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2010-12-22 03:01:18 +00:00
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void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
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2008-08-19 08:08:40 +00:00
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struct powerdomain *pwrdm_lookup(const char *name);
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2008-10-15 15:13:47 +00:00
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int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
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void *user);
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2009-10-01 07:01:55 +00:00
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int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
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void *user);
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2008-08-19 08:08:40 +00:00
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2008-08-19 08:08:44 +00:00
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int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
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int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
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int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
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int (*fn)(struct powerdomain *pwrdm,
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struct clockdomain *clkdm));
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2008-08-19 08:08:40 +00:00
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int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
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int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
|
2009-01-28 02:12:50 +00:00
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int pwrdm_read_pwrst(struct powerdomain *pwrdm);
|
2008-08-19 08:08:40 +00:00
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int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
|
2010-02-24 19:05:49 +00:00
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int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
|
2008-08-19 08:08:40 +00:00
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int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
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int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
2010-02-24 19:05:49 +00:00
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int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
|
2008-08-19 08:08:40 +00:00
|
|
|
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 00:09:37 +00:00
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int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
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int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
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bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
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2008-08-19 08:08:40 +00:00
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int pwrdm_wait_transition(struct powerdomain *pwrdm);
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2008-10-15 14:48:43 +00:00
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int pwrdm_state_switch(struct powerdomain *pwrdm);
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int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
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int pwrdm_pre_transition(void);
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int pwrdm_post_transition(void);
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2010-10-08 16:58:35 +00:00
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int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
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2008-10-15 14:48:43 +00:00
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2010-12-22 03:01:20 +00:00
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extern void omap2xxx_powerdomains_init(void);
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extern void omap3xxx_powerdomains_init(void);
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extern void omap44xx_powerdomains_init(void);
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2008-08-19 08:08:40 +00:00
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#endif
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