drivers/gpu/host1x/hw/host1x07_hardware.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Tegra host1x Register Offsets for Tegra194
 *
 * Copyright (c) 2018 NVIDIA Corporation.
 */

#ifndef __HOST1X_HOST1X07_HARDWARE_H
#define __HOST1X_HOST1X07_HARDWARE_H

#include <linux/types.h>
#include <linux/bitops.h>

#include "hw_host1x07_channel.h"
#include "hw_host1x07_uclass.h"
#include "hw_host1x07_vm.h"
#include "hw_host1x07_hypervisor.h"

#include "opcodes.h"

#endif
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-28 10:10:04 -07:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
gpu: host1x: Add Tegra194 support The host1x hardware found on Tegra194 is mostly backwards compatible with the version found on Tegra186, with the notable exceptions of the increased number of syncpoints and mlocks. In addition, some rarely used features such as syncpoint wait bases were dropped and some registers had to move around to accomodate the increased number of syncpoints. Signed-off-by: Thierry Reding <treding@nvidia.com> 2018-01-25 14:10:44 +02:00			`/*`
			`* Tegra host1x Register Offsets for Tegra194`
			`*`
			`* Copyright (c) 2018 NVIDIA Corporation.`
			`*/`

			`#ifndef __HOST1X_HOST1X07_HARDWARE_H`
			`#define __HOST1X_HOST1X07_HARDWARE_H`

			`#include <linux/types.h>`
			`#include <linux/bitops.h>`

gpu: host1x: Program the channel stream ID When processing command streams, make sure the host1x's stream ID is programmed for the channel so that addresses are properly translated through the SMMU. Signed-off-by: Thierry Reding <treding@nvidia.com> 2019-02-01 14:28:23 +01:00			`#include "hw_host1x07_channel.h"`
gpu: host1x: Add Tegra194 support The host1x hardware found on Tegra194 is mostly backwards compatible with the version found on Tegra186, with the notable exceptions of the increased number of syncpoints and mlocks. In addition, some rarely used features such as syncpoint wait bases were dropped and some registers had to move around to accomodate the increased number of syncpoints. Signed-off-by: Thierry Reding <treding@nvidia.com> 2018-01-25 14:10:44 +02:00			`#include "hw_host1x07_uclass.h"`
			`#include "hw_host1x07_vm.h"`
			`#include "hw_host1x07_hypervisor.h"`

gpu: host1x: Deduplicate hardware headers Host1x class information and opcodes are unchanged or backwards compatible across SoCs so let's not duplicate them for each one but have them in a shared header file. At the same time, add opcode functions for acquire/release_mlock. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2022-06-27 17:19:59 +03:00			`#include "opcodes.h"`
gpu: host1x: Add Tegra194 support The host1x hardware found on Tegra194 is mostly backwards compatible with the version found on Tegra186, with the notable exceptions of the increased number of syncpoints and mlocks. In addition, some rarely used features such as syncpoint wait bases were dropped and some registers had to move around to accomodate the increased number of syncpoints. Signed-off-by: Thierry Reding <treding@nvidia.com> 2018-01-25 14:10:44 +02:00
			`#endif`