rtw89: add Realtek 802.11ax driver
This driver named rtw89, which is the next generation of rtw88, supports
Realtek 8852AE 802.11ax 2x2 chip whose new features are OFDMA, DBCC,
Spatial reuse, TWT and BSS coloring; now some of them aren't implemented
though.
The chip architecture is entirely different from the chips supported by
rtw88 like RTL8822CE 802.11ac chip. First of all, register address ranges
are totally redefined, so it's impossible to reuse register definition. To
communicate with firmware, new H2C/C2H format is proposed. In order to have
better utilization, TX DMA flow is changed to two stages DMA. To provide
rich RX status information, additional RX PPDU packets are added.
Since there are so many differences mentioned above, we decide to propose
a new driver. It has many authors, they are listed in alphabetic order:
Chin-Yen Lee <timlee@realtek.com>
Ping-Ke Shih <pkshih@realtek.com>
Po Hao Huang <phhuang@realtek.com>
Tzu-En Huang <tehuang@realtek.com>
Vincent Fann <vincent_fann@realtek.com>
Yan-Hsuan Chuang <tony0620emma@gmail.com>
Zong-Zhe Yang <kevin_yang@realtek.com>
Tested-by: Aaron Ma <aaron.ma@canonical.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20211008035627.19463-1-pkshih@realtek.com
2021-10-11 14:47:27 +03:00
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2019-2020 Realtek Corporation
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*/
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#ifndef __RTW89_COEX_H__
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#define __RTW89_COEX_H__
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#include "core.h"
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enum btc_mode {
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BTC_MODE_NORMAL,
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BTC_MODE_WL,
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BTC_MODE_BT,
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BTC_MODE_WLOFF,
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BTC_MODE_MAX
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};
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enum btc_wl_rfk_type {
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BTC_WRFKT_IQK = 0,
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BTC_WRFKT_LCK = 1,
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BTC_WRFKT_DPK = 2,
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BTC_WRFKT_TXGAPK = 3,
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BTC_WRFKT_DACK = 4,
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BTC_WRFKT_RXDCK = 5,
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BTC_WRFKT_TSSI = 6,
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};
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#define NM_EXEC false
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#define FC_EXEC true
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#define RTW89_COEX_ACT1_WORK_PERIOD round_jiffies_relative(HZ * 4)
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#define RTW89_COEX_BT_DEVINFO_WORK_PERIOD round_jiffies_relative(HZ * 16)
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#define RTW89_COEX_RFK_CHK_WORK_PERIOD msecs_to_jiffies(300)
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#define BTC_RFK_PATH_MAP GENMASK(3, 0)
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#define BTC_RFK_PHY_MAP GENMASK(5, 4)
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#define BTC_RFK_BAND_MAP GENMASK(7, 6)
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enum btc_wl_rfk_state {
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BTC_WRFK_STOP = 0,
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BTC_WRFK_START = 1,
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BTC_WRFK_ONESHOT_START = 2,
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BTC_WRFK_ONESHOT_STOP = 3,
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};
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enum btc_pri {
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BTC_PRI_MASK_RX_RESP = 0,
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BTC_PRI_MASK_TX_RESP,
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BTC_PRI_MASK_BEACON,
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BTC_PRI_MASK_RX_CCK,
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BTC_PRI_MASK_TX_MNGQ,
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BTC_PRI_MASK_MAX,
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};
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enum btc_bt_trs {
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BTC_BT_SS_GROUP = 0x0,
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BTC_BT_TX_GROUP = 0x2,
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BTC_BT_RX_GROUP = 0x3,
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BTC_BT_MAX_GROUP,
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};
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enum btc_rssi_st {
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BTC_RSSI_ST_LOW = 0x0,
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BTC_RSSI_ST_HIGH,
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BTC_RSSI_ST_STAY_LOW,
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BTC_RSSI_ST_STAY_HIGH,
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BTC_RSSI_ST_MAX
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};
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#define BTC_RSSI_HIGH(_rssi_) \
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({typeof(_rssi_) __rssi = (_rssi_); \
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((__rssi == BTC_RSSI_ST_HIGH || \
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__rssi == BTC_RSSI_ST_STAY_HIGH) ? 1 : 0); })
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#define BTC_RSSI_LOW(_rssi_) \
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({typeof(_rssi_) __rssi = (_rssi_); \
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((__rssi == BTC_RSSI_ST_LOW || \
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__rssi == BTC_RSSI_ST_STAY_LOW) ? 1 : 0); })
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#define BTC_RSSI_CHANGE(_rssi_) \
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({typeof(_rssi_) __rssi = (_rssi_); \
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((__rssi == BTC_RSSI_ST_LOW || \
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__rssi == BTC_RSSI_ST_HIGH) ? 1 : 0); })
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enum btc_ant {
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BTC_ANT_SHARED = 0,
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BTC_ANT_DEDICATED,
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BTC_ANTTYPE_MAX
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};
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enum btc_bt_btg {
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BTC_BT_ALONE = 0,
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BTC_BT_BTG
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};
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enum btc_switch {
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BTC_SWITCH_INTERNAL = 0,
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BTC_SWITCH_EXTERNAL
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};
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enum btc_pkt_type {
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PACKET_DHCP,
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PACKET_ARP,
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PACKET_EAPOL,
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PACKET_EAPOL_END,
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PACKET_ICMP,
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PACKET_MAX
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};
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enum btc_bt_mailbox_id {
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BTC_BTINFO_REPLY = 0x23,
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BTC_BTINFO_AUTO = 0x27
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};
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enum btc_role_state {
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BTC_ROLE_START,
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BTC_ROLE_STOP,
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BTC_ROLE_CHG_TYPE,
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BTC_ROLE_MSTS_STA_CONN_START,
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BTC_ROLE_MSTS_STA_CONN_END,
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BTC_ROLE_MSTS_STA_DIS_CONN,
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BTC_ROLE_MSTS_AP_START,
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BTC_ROLE_MSTS_AP_STOP,
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BTC_ROLE_STATE_UNKNOWN
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};
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enum btc_rfctrl {
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BTC_RFCTRL_WL_OFF,
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BTC_RFCTRL_WL_ON,
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BTC_RFCTRL_FW_CTRL,
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BTC_RFCTRL_MAX
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};
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2021-12-09 16:32:26 +08:00
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enum btc_lps_state {
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BTC_LPS_OFF = 0,
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BTC_LPS_RF_OFF = 1,
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BTC_LPS_RF_ON = 2
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};
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rtw89: add Realtek 802.11ax driver
This driver named rtw89, which is the next generation of rtw88, supports
Realtek 8852AE 802.11ax 2x2 chip whose new features are OFDMA, DBCC,
Spatial reuse, TWT and BSS coloring; now some of them aren't implemented
though.
The chip architecture is entirely different from the chips supported by
rtw88 like RTL8822CE 802.11ac chip. First of all, register address ranges
are totally redefined, so it's impossible to reuse register definition. To
communicate with firmware, new H2C/C2H format is proposed. In order to have
better utilization, TX DMA flow is changed to two stages DMA. To provide
rich RX status information, additional RX PPDU packets are added.
Since there are so many differences mentioned above, we decide to propose
a new driver. It has many authors, they are listed in alphabetic order:
Chin-Yen Lee <timlee@realtek.com>
Ping-Ke Shih <pkshih@realtek.com>
Po Hao Huang <phhuang@realtek.com>
Tzu-En Huang <tehuang@realtek.com>
Vincent Fann <vincent_fann@realtek.com>
Yan-Hsuan Chuang <tony0620emma@gmail.com>
Zong-Zhe Yang <kevin_yang@realtek.com>
Tested-by: Aaron Ma <aaron.ma@canonical.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20211008035627.19463-1-pkshih@realtek.com
2021-10-11 14:47:27 +03:00
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void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev);
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void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev);
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void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode);
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void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band);
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void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx);
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void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band);
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void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev,
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enum btc_pkt_type pkt_type);
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void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work);
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void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work);
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void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work);
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void rtw89_btc_ntfy_icmp_packet_work(struct work_struct *work);
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void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
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struct rtw89_sta *rtwsta, enum btc_role_state state);
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void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state);
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void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map,
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enum btc_wl_rfk_type type,
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enum btc_wl_rfk_state state);
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void rtw89_btc_ntfy_wl_sta(struct rtw89_dev *rtwdev);
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void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
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u32 len, u8 class, u8 func);
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void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m);
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void rtw89_coex_act1_work(struct work_struct *work);
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void rtw89_coex_bt_devinfo_work(struct work_struct *work);
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void rtw89_coex_rfk_chk_work(struct work_struct *work);
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void rtw89_coex_power_on(struct rtw89_dev *rtwdev);
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static inline u8 rtw89_btc_phymap(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx,
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enum rtw89_rf_path_bit paths)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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u8 phy_map;
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phy_map = FIELD_PREP(BTC_RFK_PATH_MAP, paths) |
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FIELD_PREP(BTC_RFK_PHY_MAP, BIT(phy_idx)) |
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FIELD_PREP(BTC_RFK_BAND_MAP, hal->current_band_type);
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return phy_map;
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}
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static inline u8 rtw89_btc_path_phymap(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx,
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enum rtw89_rf_path path)
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{
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return rtw89_btc_phymap(rtwdev, phy_idx, BIT(path));
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}
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#endif
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