2011-10-10 16:29:24 +00:00
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/*
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* at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
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* applies to AT91SAM9G45, AT91SAM9M10,
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* AT91SAM9G46, AT91SAM9M11 SoC
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*
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* Copyright (C) 2011 Atmel,
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* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Atmel AT91SAM9G45 family SoC";
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compatible = "atmel,at91sam9g45";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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serial4 = &usart3;
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2012-02-11 14:41:40 +00:00
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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gpio4 = &pioE;
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2012-01-19 09:13:40 +00:00
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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2011-10-10 16:29:24 +00:00
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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};
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};
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memory@70000000 {
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reg = <0x70000000 0x10000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aic: interrupt-controller@fffff000 {
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2011-11-22 21:26:09 +00:00
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#interrupt-cells = <2>;
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2011-10-10 16:29:24 +00:00
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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interrupt-parent;
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reg = <0xfffff000 0x200>;
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};
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2012-02-27 10:19:34 +00:00
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pit: timer@fffffd30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffd30 0xf>;
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interrupts = <1 4>;
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};
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2012-01-19 09:13:40 +00:00
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tcb0: timer@fff7c000 {
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compatible = "atmel,at91rm9200-tcb";
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reg = <0xfff7c000 0x100>;
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interrupts = <18 4>;
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};
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tcb1: timer@fffd4000 {
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compatible = "atmel,at91rm9200-tcb";
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reg = <0xfffd4000 0x100>;
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interrupts = <18 4>;
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};
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2011-10-10 16:29:24 +00:00
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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2011-11-22 21:26:09 +00:00
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interrupts = <21 4>;
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2011-10-10 16:29:24 +00:00
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};
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2012-02-11 14:41:40 +00:00
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pioA: gpio@fffff200 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff200 0x100>;
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interrupts = <2 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioB: gpio@fffff400 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x100>;
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interrupts = <3 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioC: gpio@fffff600 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff600 0x100>;
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interrupts = <4 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioD: gpio@fffff800 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff800 0x100>;
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interrupts = <5 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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pioE: gpio@fffffa00 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffffa00 0x100>;
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interrupts = <5 4>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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2011-10-10 16:29:24 +00:00
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dbgu: serial@ffffee00 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xffffee00 0x200>;
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2011-11-22 21:26:09 +00:00
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interrupts = <1 4>;
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2011-10-10 16:29:24 +00:00
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status = "disabled";
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};
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usart0: serial@fff8c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff8c000 0x200>;
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2011-11-22 21:26:09 +00:00
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interrupts = <7 4>;
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2011-10-10 16:29:24 +00:00
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart1: serial@fff90000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff90000 0x200>;
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2011-11-22 21:26:09 +00:00
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interrupts = <8 4>;
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2011-10-10 16:29:24 +00:00
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart2: serial@fff94000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff94000 0x200>;
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2011-11-22 21:26:09 +00:00
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interrupts = <9 4>;
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2011-10-10 16:29:24 +00:00
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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usart3: serial@fff98000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff98000 0x200>;
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2011-11-22 21:26:09 +00:00
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interrupts = <10 4>;
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2011-10-10 16:29:24 +00:00
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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2011-12-05 17:03:05 +00:00
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macb0: ethernet@fffbc000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xfffbc000 0x100>;
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2011-11-22 21:26:09 +00:00
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interrupts = <25 4>;
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2011-12-05 17:03:05 +00:00
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status = "disabled";
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};
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2011-10-10 16:29:24 +00:00
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};
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2012-01-25 18:11:06 +00:00
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x10000000
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0xffffe200 0x200
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>;
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atmel,nand-addr-offset = <21>;
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atmel,nand-cmd-offset = <22>;
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gpios = <&pioC 8 0
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&pioC 14 0
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0
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>;
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status = "disabled";
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};
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2011-10-10 16:29:24 +00:00
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};
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};
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