2018-08-09 11:59:11 +03:00
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
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2015-10-16 14:01:37 +02:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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2016-10-27 15:12:59 +02:00
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#include <linux/pci.h>
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2015-10-16 14:01:37 +02:00
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/skbuff.h>
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#include <linux/if_vlan.h>
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#include <linux/if_bridge.h>
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#include <linux/workqueue.h>
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#include <linux/jiffies.h>
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#include <linux/bitops.h>
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2015-12-15 16:03:37 +01:00
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#include <linux/list.h>
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2016-06-20 23:03:59 +02:00
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#include <linux/notifier.h>
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2016-04-06 17:10:08 +02:00
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#include <linux/dcbnl.h>
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mlxsw: spectrum: Introduce support for router interfaces
Up until now we only supported bridged interfaces. Packets ingressing
through the switch ports were either classified to FIDs (in the case of
the VLAN-aware bridge) or vFIDs (in the case of VLAN-unaware bridges).
The packets were then forwarded according to the FDB. Routing was done
entirely in slowpath, by splitting the vFID range in two and using the
lower 0.5K vFIDs as dummy bridges that simply flooded all incoming
traffic to the CPU.
Instead, allow packets to be routed in the device by creating router
interfaces (RIFs) that will direct them to the router block.
Specifically, the RIFs introduced here are Sub-port RIFs used for VLAN
devices and port netdevs. Packets ingressing from the {Port / LAG ID, VID}
with which the RIF was programmed with will be assigned to a special
kind of FIDs called rFIDs and from there directed to the router.
Create a RIF whenever the first IPv4 address was programmed on a VLAN /
LAG / port netdev. Destroy it upon removal of the last IPv4 address.
Receive these notifications by registering for the 'inetaddr'
notification chain. A non-zero (10) priority is used for the
notification block, so that RIFs will be created before routes are
offloaded via FIB code.
Note that another trigger for RIF destruction are CHANGEUPPER
notifications causing the underlying FID's reference count to go down to
zero. This can happen, for example, when a VLAN netdev with an IP address
is put under bridge. While this configuration doesn't make sense it does
cause the device and the kernel to get out of sync when the netdev is
unbridged. We intend to address this in the future, hopefully in current
cycle.
Finally, Remove the lower 0.5K vFIDs, as they are deprecated by the RIFs,
which will trap packets according to their DIP.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-04 08:23:14 +02:00
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#include <linux/inetdevice.h>
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2017-10-08 11:57:55 +02:00
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#include <linux/netlink.h>
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2019-04-21 07:18:34 +00:00
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#include <linux/jhash.h>
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2019-10-31 11:42:14 +02:00
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#include <linux/log2.h>
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2021-03-16 17:02:57 +02:00
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#include <linux/refcount.h>
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#include <linux/rhashtable.h>
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2015-10-16 14:01:37 +02:00
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#include <net/switchdev.h>
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2016-07-21 12:03:17 +02:00
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#include <net/pkt_cls.h>
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2016-09-01 10:37:43 +02:00
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#include <net/netevent.h>
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2017-07-18 10:10:13 +02:00
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#include <net/addrconf.h>
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2015-10-16 14:01:37 +02:00
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#include "spectrum.h"
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2016-10-27 15:12:59 +02:00
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#include "pci.h"
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2015-10-16 14:01:37 +02:00
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#include "core.h"
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2019-03-03 09:12:08 +00:00
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#include "core_env.h"
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2015-10-16 14:01:37 +02:00
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#include "reg.h"
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#include "port.h"
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#include "trap.h"
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#include "txheader.h"
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2017-03-11 09:42:51 +01:00
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#include "spectrum_cnt.h"
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2017-03-28 17:24:12 +02:00
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#include "spectrum_dpipe.h"
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2017-09-19 10:00:09 +02:00
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#include "spectrum_acl_flex_actions.h"
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2018-02-13 11:27:48 +01:00
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#include "spectrum_span.h"
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2019-06-11 18:45:11 +03:00
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#include "spectrum_ptp.h"
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2020-03-30 22:38:26 +03:00
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#include "spectrum_trap.h"
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2015-10-16 14:01:37 +02:00
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2018-07-08 23:51:26 +03:00
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#define MLXSW_SP1_FWREV_MAJOR 13
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2020-09-15 11:40:51 +03:00
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#define MLXSW_SP1_FWREV_MINOR 2008
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2021-03-10 13:02:17 +02:00
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#define MLXSW_SP1_FWREV_SUBMINOR 2406
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2018-08-09 11:59:09 +03:00
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#define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
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2018-07-08 23:51:26 +03:00
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static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
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.major = MLXSW_SP1_FWREV_MAJOR,
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.minor = MLXSW_SP1_FWREV_MINOR,
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.subminor = MLXSW_SP1_FWREV_SUBMINOR,
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2018-08-09 11:59:09 +03:00
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.can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
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2018-07-08 23:51:26 +03:00
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};
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#define MLXSW_SP1_FW_FILENAME \
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"mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
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"." __stringify(MLXSW_SP1_FWREV_MINOR) \
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"." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
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2017-05-23 21:56:29 +02:00
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2019-10-30 11:34:51 +02:00
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#define MLXSW_SP2_FWREV_MAJOR 29
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2020-09-15 11:40:51 +03:00
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#define MLXSW_SP2_FWREV_MINOR 2008
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2021-03-10 13:02:17 +02:00
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#define MLXSW_SP2_FWREV_SUBMINOR 2406
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2019-10-30 11:34:51 +02:00
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static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
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.major = MLXSW_SP2_FWREV_MAJOR,
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.minor = MLXSW_SP2_FWREV_MINOR,
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.subminor = MLXSW_SP2_FWREV_SUBMINOR,
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};
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#define MLXSW_SP2_FW_FILENAME \
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"mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
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"." __stringify(MLXSW_SP2_FWREV_MINOR) \
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"." __stringify(MLXSW_SP2_FWREV_SUBMINOR) ".mfa2"
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2020-06-23 22:13:46 +03:00
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#define MLXSW_SP3_FWREV_MAJOR 30
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2020-09-15 11:40:51 +03:00
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#define MLXSW_SP3_FWREV_MINOR 2008
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2021-03-10 13:02:17 +02:00
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#define MLXSW_SP3_FWREV_SUBMINOR 2406
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2020-06-23 22:13:46 +03:00
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static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = {
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.major = MLXSW_SP3_FWREV_MAJOR,
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.minor = MLXSW_SP3_FWREV_MINOR,
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.subminor = MLXSW_SP3_FWREV_SUBMINOR,
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};
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#define MLXSW_SP3_FW_FILENAME \
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"mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \
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"." __stringify(MLXSW_SP3_FWREV_MINOR) \
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"." __stringify(MLXSW_SP3_FWREV_SUBMINOR) ".mfa2"
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2018-07-18 11:14:45 +03:00
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static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
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static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
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2019-08-07 13:42:31 +03:00
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static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
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2015-10-16 14:01:37 +02:00
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2018-12-13 11:54:50 +00:00
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static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
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0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
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};
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static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
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0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
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};
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2015-10-16 14:01:37 +02:00
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/* tx_hdr_version
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* Tx header version.
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* Must be set to 1.
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*/
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MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
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/* tx_hdr_ctl
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* Packet control type.
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* 0 - Ethernet control (e.g. EMADs, LACP)
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* 1 - Ethernet data
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*/
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MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
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/* tx_hdr_proto
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* Packet protocol type. Must be set to 1 (Ethernet).
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*/
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MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
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/* tx_hdr_rx_is_router
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* Packet is sent from the router. Valid for data packets only.
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*/
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MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
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/* tx_hdr_fid_valid
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* Indicates if the 'fid' field is valid and should be used for
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* forwarding lookup. Valid for data packets only.
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*/
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MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
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/* tx_hdr_swid
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* Switch partition ID. Must be set to 0.
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*/
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MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
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/* tx_hdr_control_tclass
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* Indicates if the packet should use the control TClass and not one
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* of the data TClasses.
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*/
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MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
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/* tx_hdr_etclass
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* Egress TClass to be used on the egress device on the egress port.
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*/
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MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
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/* tx_hdr_port_mid
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* Destination local port for unicast packets.
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* Destination multicast ID for multicast packets.
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*
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* Control packets are directed to a specific egress port, while data
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* packets are transmitted through the CPU port (0) into the switch partition,
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* where forwarding rules are applied.
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*/
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MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
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/* tx_hdr_fid
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* Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
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* set, otherwise calculated based on the packet's VID using VID to FID mapping.
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* Valid for data packets only.
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*/
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MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
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/* tx_hdr_type
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* 0 - Data packets
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* 6 - Control packets
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*/
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MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
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2017-03-11 09:42:53 +01:00
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int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
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unsigned int counter_index, u64 *packets,
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u64 *bytes)
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{
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char mgpc_pl[MLXSW_REG_MGPC_LEN];
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int err;
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mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
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2017-08-24 08:40:07 +02:00
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MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
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2017-03-11 09:42:53 +01:00
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err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
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if (err)
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return err;
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2017-08-24 08:40:08 +02:00
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if (packets)
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*packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
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if (bytes)
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*bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
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2017-03-11 09:42:53 +01:00
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return 0;
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}
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static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
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unsigned int counter_index)
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{
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char mgpc_pl[MLXSW_REG_MGPC_LEN];
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mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
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2017-08-24 08:40:07 +02:00
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MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
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2017-03-11 09:42:53 +01:00
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return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
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}
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int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
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unsigned int *p_counter_index)
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{
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int err;
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err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
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p_counter_index);
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if (err)
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return err;
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err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
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if (err)
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goto err_counter_clear;
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return 0;
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err_counter_clear:
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mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
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*p_counter_index);
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return err;
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}
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void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
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unsigned int counter_index)
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{
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mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
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counter_index);
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}
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2015-10-16 14:01:37 +02:00
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static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
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const struct mlxsw_tx_info *tx_info)
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{
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char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
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memset(txhdr, 0, MLXSW_TXHDR_LEN);
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mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
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mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
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mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
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mlxsw_tx_hdr_swid_set(txhdr, 0);
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mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
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mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
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mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
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}
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2018-04-29 10:56:09 +03:00
|
|
|
enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
|
2017-05-16 19:38:31 +02:00
|
|
|
{
|
|
|
|
|
switch (state) {
|
|
|
|
|
case BR_STATE_FORWARDING:
|
2018-04-29 10:56:09 +03:00
|
|
|
return MLXSW_REG_SPMS_STATE_FORWARDING;
|
2017-05-16 19:38:31 +02:00
|
|
|
case BR_STATE_LEARNING:
|
2018-04-29 10:56:09 +03:00
|
|
|
return MLXSW_REG_SPMS_STATE_LEARNING;
|
2020-08-23 17:36:59 -05:00
|
|
|
case BR_STATE_LISTENING:
|
|
|
|
|
case BR_STATE_DISABLED:
|
2017-05-16 19:38:31 +02:00
|
|
|
case BR_STATE_BLOCKING:
|
2018-04-29 10:56:09 +03:00
|
|
|
return MLXSW_REG_SPMS_STATE_DISCARDING;
|
2017-05-16 19:38:31 +02:00
|
|
|
default:
|
|
|
|
|
BUG();
|
|
|
|
|
}
|
2018-04-29 10:56:09 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
|
|
|
|
|
u8 state)
|
|
|
|
|
{
|
|
|
|
|
enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char *spms_pl;
|
|
|
|
|
int err;
|
2017-05-16 19:38:31 +02:00
|
|
|
|
|
|
|
|
spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
|
|
|
|
|
if (!spms_pl)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
|
|
|
|
|
mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
|
|
|
|
|
|
|
|
|
|
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
|
|
|
|
|
kfree(spms_pl);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
2016-10-28 21:35:46 +02:00
|
|
|
char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
|
2015-10-16 14:01:37 +02:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-29 23:46:13 +03:00
|
|
|
int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
bool is_up)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char paos_pl[MLXSW_REG_PAOS_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
|
|
|
|
|
MLXSW_PORT_ADMIN_STATUS_DOWN);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
unsigned char *addr)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char ppad_pl[MLXSW_REG_PPAD_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
|
|
|
|
|
mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
|
|
|
|
|
|
|
|
|
|
ether_addr_copy(addr, mlxsw_sp->base_mac);
|
|
|
|
|
addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
|
|
|
|
|
return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-13 18:46:07 +03:00
|
|
|
static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char pmtu_pl[MLXSW_REG_PMTU_LEN];
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
|
|
|
|
|
err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2020-09-13 18:46:07 +03:00
|
|
|
*p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char pmtu_pl[MLXSW_REG_PMTU_LEN];
|
|
|
|
|
|
|
|
|
|
mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
|
|
|
|
|
if (mtu > mlxsw_sp_port->max_mtu)
|
2015-10-16 14:01:37 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-09 09:51:39 +02:00
|
|
|
static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
2017-06-08 08:47:44 +02:00
|
|
|
char pspa_pl[MLXSW_REG_PSPA_LEN];
|
2016-06-09 09:51:39 +02:00
|
|
|
|
2017-06-08 08:47:44 +02:00
|
|
|
mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
|
2016-06-09 09:51:39 +02:00
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:39 +02:00
|
|
|
int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char svpe_pl[MLXSW_REG_SVPE_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-16 19:38:33 +02:00
|
|
|
int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
|
|
|
|
|
bool learn_enable)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char *spvmlr_pl;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
|
|
|
|
|
if (!spvmlr_pl)
|
|
|
|
|
return -ENOMEM;
|
2017-05-16 19:38:33 +02:00
|
|
|
mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
|
|
|
|
|
learn_enable);
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
|
|
|
|
|
kfree(spvmlr_pl);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2020-12-08 11:22:47 +02:00
|
|
|
int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type)
|
2020-11-29 14:54:02 +02:00
|
|
|
{
|
|
|
|
|
switch (ethtype) {
|
|
|
|
|
case ETH_P_8021Q:
|
|
|
|
|
*p_sver_type = 0;
|
|
|
|
|
break;
|
|
|
|
|
case ETH_P_8021AD:
|
|
|
|
|
*p_sver_type = 1;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2021-03-17 12:35:25 +02:00
|
|
|
int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 ethtype)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char spevet_pl[MLXSW_REG_SPEVET_LEN];
|
|
|
|
|
u8 sver_type;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-16 19:38:34 +02:00
|
|
|
static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
2020-11-29 14:54:02 +02:00
|
|
|
u16 vid, u16 ethtype)
|
2017-05-16 19:38:34 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char spvid_pl[MLXSW_REG_SPVID_LEN];
|
2020-11-29 14:54:02 +02:00
|
|
|
u8 sver_type;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid,
|
|
|
|
|
sver_type);
|
2017-05-16 19:38:34 +02:00
|
|
|
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
bool allow)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char spaft_pl[MLXSW_REG_SPAFT_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-29 14:54:02 +02:00
|
|
|
int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
|
|
|
|
|
u16 ethtype)
|
2017-05-16 19:38:34 +02:00
|
|
|
{
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!vid) {
|
|
|
|
|
err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
} else {
|
2020-11-29 14:54:02 +02:00
|
|
|
err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype);
|
2017-05-16 19:38:34 +02:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_port_allow_untagged_set;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port->pvid = vid;
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_port_allow_untagged_set:
|
2020-11-29 14:54:02 +02:00
|
|
|
__mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype);
|
2017-05-16 19:38:34 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static int
|
|
|
|
|
mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char sspr_pl[MLXSW_REG_SSPR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:11 +02:00
|
|
|
static int
|
|
|
|
|
mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u8 local_port,
|
|
|
|
|
struct mlxsw_sp_port_mapping *port_mapping)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
char pmlp_pl[MLXSW_REG_PMLP_LEN];
|
2019-10-31 11:42:14 +02:00
|
|
|
bool separate_rxtx;
|
|
|
|
|
u8 module;
|
|
|
|
|
u8 width;
|
2015-10-16 14:01:37 +02:00
|
|
|
int err;
|
2019-10-31 11:42:14 +02:00
|
|
|
int i;
|
2015-10-16 14:01:37 +02:00
|
|
|
|
2016-02-26 17:32:29 +01:00
|
|
|
mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
2019-10-31 11:42:14 +02:00
|
|
|
module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
|
|
|
|
|
width = mlxsw_reg_pmlp_width_get(pmlp_pl);
|
|
|
|
|
separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
|
|
|
|
|
|
|
|
|
|
if (width && !is_power_of_2(width)) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
|
|
|
|
|
local_port);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < width; i++) {
|
|
|
|
|
if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
|
|
|
|
|
local_port);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
if (separate_rxtx &&
|
|
|
|
|
mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
|
|
|
|
|
mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
|
|
|
|
|
local_port);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
|
|
|
|
|
local_port);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
port_mapping->module = module;
|
|
|
|
|
port_mapping->width = width;
|
2019-10-31 11:42:11 +02:00
|
|
|
port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
|
2015-10-16 14:01:37 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:13 +02:00
|
|
|
static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port)
|
2016-02-26 17:32:31 +01:00
|
|
|
{
|
2019-10-31 11:42:13 +02:00
|
|
|
struct mlxsw_sp_port_mapping *port_mapping = &mlxsw_sp_port->mapping;
|
2017-06-08 08:47:45 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
2016-02-26 17:32:31 +01:00
|
|
|
char pmlp_pl[MLXSW_REG_PMLP_LEN];
|
|
|
|
|
int i;
|
|
|
|
|
|
2017-06-08 08:47:45 +02:00
|
|
|
mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
|
2019-10-31 11:42:13 +02:00
|
|
|
mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
|
|
|
|
|
for (i = 0; i < port_mapping->width; i++) {
|
|
|
|
|
mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
|
|
|
|
|
mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
|
2016-02-26 17:32:31 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-08 08:47:45 +02:00
|
|
|
static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
|
2016-02-26 17:32:28 +01:00
|
|
|
{
|
2017-06-08 08:47:45 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
2016-02-26 17:32:28 +01:00
|
|
|
char pmlp_pl[MLXSW_REG_PMLP_LEN];
|
|
|
|
|
|
2017-06-08 08:47:45 +02:00
|
|
|
mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
|
2016-02-26 17:32:28 +01:00
|
|
|
mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static int mlxsw_sp_port_open(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
netif_start_queue(dev);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_stop(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
|
return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
|
|
|
|
|
struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
|
|
|
|
|
const struct mlxsw_tx_info tx_info = {
|
|
|
|
|
.local_port = mlxsw_sp_port->local_port,
|
|
|
|
|
.is_emad = false,
|
|
|
|
|
};
|
|
|
|
|
u64 len;
|
|
|
|
|
int err;
|
|
|
|
|
|
2020-01-15 13:53:45 +02:00
|
|
|
if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
|
|
|
|
|
this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
|
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:52 +03:00
|
|
|
memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
|
|
|
|
|
|
2016-04-08 19:11:22 +02:00
|
|
|
if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
|
2015-10-16 14:01:37 +02:00
|
|
|
return NETDEV_TX_BUSY;
|
|
|
|
|
|
|
|
|
|
if (eth_skb_pad(skb)) {
|
|
|
|
|
this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_txhdr_construct(skb, &tx_info);
|
2016-06-17 15:09:05 +02:00
|
|
|
/* TX header is consumed by HW on the way so we shouldn't count its
|
|
|
|
|
* bytes as being sent.
|
|
|
|
|
*/
|
|
|
|
|
len = skb->len - MLXSW_TXHDR_LEN;
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
/* Due to a race we might fail here because of a full queue. In that
|
|
|
|
|
* unlikely case we simply drop the packet.
|
|
|
|
|
*/
|
2016-04-08 19:11:22 +02:00
|
|
|
err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
if (!err) {
|
|
|
|
|
pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
|
|
|
|
|
u64_stats_update_begin(&pcpu_stats->syncp);
|
|
|
|
|
pcpu_stats->tx_packets++;
|
|
|
|
|
pcpu_stats->tx_bytes += len;
|
|
|
|
|
u64_stats_update_end(&pcpu_stats->syncp);
|
|
|
|
|
} else {
|
|
|
|
|
this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
|
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
|
}
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-03 12:12:22 +01:00
|
|
|
static void mlxsw_sp_set_rx_mode(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
struct sockaddr *addr = p;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!is_valid_ether_addr(addr->sa_data))
|
|
|
|
|
return -EADDRNOTAVAIL;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
2020-09-16 09:35:16 +03:00
|
|
|
struct mlxsw_sp_hdroom orig_hdroom;
|
|
|
|
|
struct mlxsw_sp_hdroom hdroom;
|
2015-10-16 14:01:37 +02:00
|
|
|
int err;
|
|
|
|
|
|
2020-09-16 09:35:16 +03:00
|
|
|
orig_hdroom = *mlxsw_sp_port->hdroom;
|
|
|
|
|
|
|
|
|
|
hdroom = orig_hdroom;
|
|
|
|
|
hdroom.mtu = mtu;
|
mlxsw: spectrum: Split headroom autoresize out of buffer configuration
Split mlxsw_sp_port_headroom_set() to three functions.
mlxsw_sp_hdroom_bufs_reset_sizes() changes the sizes of the individual PG
buffers, and mlxsw_sp_hdroom_configure_buffers() will actually apply the
configuration. A third function, mlxsw_sp_hdroom_bufs_fit(), verifies that
the requested buffer configuration matches total headroom size
requirements.
Add wrappers, mlxsw_sp_hdroom_configure() and __..., that will eventually
perform full headroom configuration, but for now, only have them verify the
configured headroom size, and invoke mlxsw_sp_hdroom_configure_buffers().
Have them take the `force` argument to prepare for a later patch, even
though it is currently unused.
Note that the loop in mlxsw_sp_hdroom_configure_buffers() only goes through
DCBX_MAX_BUFFERS. Since there is no logic to configure the control buffer,
it needs to keep the values queried from the FW. Eventually this function
should configure all the PGs.
Note that conversion of __mlxsw_sp_dcbnl_ieee_setets() is not trivial. That
function performs the headroom configuration in three steps: first it
resizes the buffers and adds any new ones. Then it redirects priorities to
the new buffers. And finally it sets the size of the now-unused buffers to
zero. This way no packet drops are introduced.
So after invoking mlxsw_sp_hdroom_bufs_reset_sizes(), tweak the
configuration to keep the old sizes of PG buffers for those buffers whose
size was set to zero.
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-16 09:35:20 +03:00
|
|
|
mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
|
|
|
|
|
if (err) {
|
|
|
|
|
netdev_err(dev, "Failed to configure port's headroom\n");
|
2015-10-16 14:01:37 +02:00
|
|
|
return err;
|
mlxsw: spectrum: Split headroom autoresize out of buffer configuration
Split mlxsw_sp_port_headroom_set() to three functions.
mlxsw_sp_hdroom_bufs_reset_sizes() changes the sizes of the individual PG
buffers, and mlxsw_sp_hdroom_configure_buffers() will actually apply the
configuration. A third function, mlxsw_sp_hdroom_bufs_fit(), verifies that
the requested buffer configuration matches total headroom size
requirements.
Add wrappers, mlxsw_sp_hdroom_configure() and __..., that will eventually
perform full headroom configuration, but for now, only have them verify the
configured headroom size, and invoke mlxsw_sp_hdroom_configure_buffers().
Have them take the `force` argument to prepare for a later patch, even
though it is currently unused.
Note that the loop in mlxsw_sp_hdroom_configure_buffers() only goes through
DCBX_MAX_BUFFERS. Since there is no logic to configure the control buffer,
it needs to keep the values queried from the FW. Eventually this function
should configure all the PGs.
Note that conversion of __mlxsw_sp_dcbnl_ieee_setets() is not trivial. That
function performs the headroom configuration in three steps: first it
resizes the buffers and adds any new ones. Then it redirects priorities to
the new buffers. And finally it sets the size of the now-unused buffers to
zero. This way no packet drops are introduced.
So after invoking mlxsw_sp_hdroom_bufs_reset_sizes(), tweak the
configuration to keep the old sizes of PG buffers for those buffers whose
size was set to zero.
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-16 09:35:20 +03:00
|
|
|
}
|
2020-09-16 09:35:16 +03:00
|
|
|
|
2016-04-06 17:10:03 +02:00
|
|
|
err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_port_mtu_set;
|
2015-10-16 14:01:37 +02:00
|
|
|
dev->mtu = mtu;
|
|
|
|
|
return 0;
|
2016-04-06 17:10:03 +02:00
|
|
|
|
|
|
|
|
err_port_mtu_set:
|
mlxsw: spectrum: Split headroom autoresize out of buffer configuration
Split mlxsw_sp_port_headroom_set() to three functions.
mlxsw_sp_hdroom_bufs_reset_sizes() changes the sizes of the individual PG
buffers, and mlxsw_sp_hdroom_configure_buffers() will actually apply the
configuration. A third function, mlxsw_sp_hdroom_bufs_fit(), verifies that
the requested buffer configuration matches total headroom size
requirements.
Add wrappers, mlxsw_sp_hdroom_configure() and __..., that will eventually
perform full headroom configuration, but for now, only have them verify the
configured headroom size, and invoke mlxsw_sp_hdroom_configure_buffers().
Have them take the `force` argument to prepare for a later patch, even
though it is currently unused.
Note that the loop in mlxsw_sp_hdroom_configure_buffers() only goes through
DCBX_MAX_BUFFERS. Since there is no logic to configure the control buffer,
it needs to keep the values queried from the FW. Eventually this function
should configure all the PGs.
Note that conversion of __mlxsw_sp_dcbnl_ieee_setets() is not trivial. That
function performs the headroom configuration in three steps: first it
resizes the buffers and adds any new ones. Then it redirects priorities to
the new buffers. And finally it sets the size of the now-unused buffers to
zero. This way no packet drops are introduced.
So after invoking mlxsw_sp_hdroom_bufs_reset_sizes(), tweak the
configuration to keep the old sizes of PG buffers for those buffers whose
size was set to zero.
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-16 09:35:20 +03:00
|
|
|
mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
|
2016-04-06 17:10:03 +02:00
|
|
|
return err;
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2016-09-20 08:14:08 +03:00
|
|
|
static int
|
2016-09-16 15:05:38 +02:00
|
|
|
mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
|
|
|
|
|
struct rtnl_link_stats64 *stats)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
struct mlxsw_sp_port_pcpu_stats *p;
|
|
|
|
|
u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
|
|
|
|
|
u32 tx_dropped = 0;
|
|
|
|
|
unsigned int start;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
|
p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
|
|
|
|
|
do {
|
|
|
|
|
start = u64_stats_fetch_begin_irq(&p->syncp);
|
|
|
|
|
rx_packets = p->rx_packets;
|
|
|
|
|
rx_bytes = p->rx_bytes;
|
|
|
|
|
tx_packets = p->tx_packets;
|
|
|
|
|
tx_bytes = p->tx_bytes;
|
|
|
|
|
} while (u64_stats_fetch_retry_irq(&p->syncp, start));
|
|
|
|
|
|
|
|
|
|
stats->rx_packets += rx_packets;
|
|
|
|
|
stats->rx_bytes += rx_bytes;
|
|
|
|
|
stats->tx_packets += tx_packets;
|
|
|
|
|
stats->tx_bytes += tx_bytes;
|
|
|
|
|
/* tx_dropped is u32, updated without syncp protection. */
|
|
|
|
|
tx_dropped += p->tx_dropped;
|
|
|
|
|
}
|
|
|
|
|
stats->tx_dropped = tx_dropped;
|
2016-09-16 15:05:38 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-22 23:09:54 +02:00
|
|
|
static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
|
2016-09-16 15:05:38 +02:00
|
|
|
{
|
|
|
|
|
switch (attr_id) {
|
|
|
|
|
case IFLA_OFFLOAD_XSTATS_CPU_HIT:
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-20 08:14:08 +03:00
|
|
|
static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
|
|
|
|
|
void *sp)
|
2016-09-16 15:05:38 +02:00
|
|
|
{
|
|
|
|
|
switch (attr_id) {
|
|
|
|
|
case IFLA_OFFLOAD_XSTATS_CPU_HIT:
|
|
|
|
|
return mlxsw_sp_port_get_sw_stats64(dev, sp);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-29 23:46:13 +03:00
|
|
|
int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
|
|
|
|
|
int prio, char *ppcnt_pl)
|
2016-09-16 15:05:38 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
|
|
|
|
|
return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
|
|
|
|
|
struct rtnl_link_stats64 *stats)
|
|
|
|
|
{
|
|
|
|
|
char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
|
|
|
|
|
0, ppcnt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
stats->tx_packets =
|
|
|
|
|
mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
|
|
|
|
|
stats->rx_packets =
|
|
|
|
|
mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
|
|
|
|
|
stats->tx_bytes =
|
|
|
|
|
mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
|
|
|
|
|
stats->rx_bytes =
|
|
|
|
|
mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
|
|
|
|
|
stats->multicast =
|
|
|
|
|
mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
|
|
|
|
|
|
|
|
|
|
stats->rx_crc_errors =
|
|
|
|
|
mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
|
|
|
|
|
stats->rx_frame_errors =
|
|
|
|
|
mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
|
|
|
|
|
|
|
|
|
|
stats->rx_length_errors = (
|
|
|
|
|
mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
|
|
|
|
|
mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
|
|
|
|
|
mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
|
|
|
|
|
|
|
|
|
|
stats->rx_errors = (stats->rx_crc_errors +
|
|
|
|
|
stats->rx_frame_errors + stats->rx_length_errors);
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-11-06 07:23:47 +01:00
|
|
|
static void
|
|
|
|
|
mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
|
|
|
|
|
struct mlxsw_sp_port_xstats *xstats)
|
|
|
|
|
{
|
|
|
|
|
char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
|
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
|
|
|
|
|
ppcnt_pl);
|
|
|
|
|
if (!err)
|
|
|
|
|
xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < TC_MAX_QUEUE; i++) {
|
|
|
|
|
err = mlxsw_sp_port_get_stats_raw(dev,
|
|
|
|
|
MLXSW_REG_PPCNT_TC_CONG_TC,
|
|
|
|
|
i, ppcnt_pl);
|
|
|
|
|
if (!err)
|
|
|
|
|
xstats->wred_drop[i] =
|
|
|
|
|
mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
|
|
|
|
|
i, ppcnt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
xstats->backlog[i] =
|
|
|
|
|
mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
|
|
|
|
|
xstats->tail_drop[i] =
|
|
|
|
|
mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
|
|
|
|
|
}
|
2018-02-28 10:44:59 +01:00
|
|
|
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
|
|
|
|
|
i, ppcnt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
|
|
|
|
|
xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
|
|
|
|
|
}
|
2017-11-06 07:23:47 +01:00
|
|
|
}
|
|
|
|
|
|
2016-09-16 15:05:38 +02:00
|
|
|
static void update_stats_cache(struct work_struct *work)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port =
|
|
|
|
|
container_of(work, struct mlxsw_sp_port,
|
2017-10-26 10:55:32 +02:00
|
|
|
periodic_hw_stats.update_dw.work);
|
2016-09-16 15:05:38 +02:00
|
|
|
|
|
|
|
|
if (!netif_carrier_ok(mlxsw_sp_port->dev))
|
2020-01-15 13:53:48 +02:00
|
|
|
/* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
|
|
|
|
|
* necessary when port goes down.
|
|
|
|
|
*/
|
2016-09-16 15:05:38 +02:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
|
2017-10-26 10:55:32 +02:00
|
|
|
&mlxsw_sp_port->periodic_hw_stats.stats);
|
2017-11-06 07:23:47 +01:00
|
|
|
mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
|
|
|
|
|
&mlxsw_sp_port->periodic_hw_stats.xstats);
|
2016-09-16 15:05:38 +02:00
|
|
|
|
|
|
|
|
out:
|
2017-10-26 10:55:32 +02:00
|
|
|
mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
|
2016-09-16 15:05:38 +02:00
|
|
|
MLXSW_HW_STATS_UPDATE_TIME);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the stats from a cache that is updated periodically,
|
|
|
|
|
* as this function might get called in an atomic context.
|
|
|
|
|
*/
|
2017-01-06 19:12:52 -08:00
|
|
|
static void
|
2016-09-16 15:05:38 +02:00
|
|
|
mlxsw_sp_port_get_stats64(struct net_device *dev,
|
|
|
|
|
struct rtnl_link_stats64 *stats)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
|
2017-10-26 10:55:32 +02:00
|
|
|
memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2017-04-18 16:55:35 +02:00
|
|
|
static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 vid_begin, u16 vid_end,
|
|
|
|
|
bool is_member, bool untagged)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char *spvm_pl;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
|
|
|
|
|
if (!spvm_pl)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
|
|
|
|
|
vid_end, is_member, untagged);
|
|
|
|
|
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
|
|
|
|
|
kfree(spvm_pl);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-18 16:55:35 +02:00
|
|
|
int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
|
|
|
|
|
u16 vid_end, bool is_member, bool untagged)
|
|
|
|
|
{
|
|
|
|
|
u16 vid, vid_e;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
for (vid = vid_begin; vid <= vid_end;
|
|
|
|
|
vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
|
|
|
|
|
vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
|
|
|
|
|
vid_end);
|
|
|
|
|
|
|
|
|
|
err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
|
|
|
|
|
is_member, untagged);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-20 19:42:29 +00:00
|
|
|
static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
bool flush_default)
|
2015-12-15 16:03:37 +01:00
|
|
|
{
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
|
2015-12-15 16:03:37 +01:00
|
|
|
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
|
2018-12-20 19:42:29 +00:00
|
|
|
&mlxsw_sp_port->vlans_list, list) {
|
|
|
|
|
if (!flush_default &&
|
|
|
|
|
mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
|
|
|
|
|
continue;
|
2018-12-19 06:08:43 +00:00
|
|
|
mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
|
2018-12-20 19:42:29 +00:00
|
|
|
}
|
2015-12-15 16:03:37 +01:00
|
|
|
}
|
|
|
|
|
|
2018-12-20 19:42:32 +00:00
|
|
|
static void
|
|
|
|
|
mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
|
|
|
|
|
{
|
|
|
|
|
if (mlxsw_sp_port_vlan->bridge_port)
|
|
|
|
|
mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
|
|
|
|
|
else if (mlxsw_sp_port_vlan->fid)
|
|
|
|
|
mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-19 06:08:43 +00:00
|
|
|
struct mlxsw_sp_port_vlan *
|
2017-05-26 08:37:26 +02:00
|
|
|
mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
|
2018-12-20 19:42:26 +00:00
|
|
|
bool untagged = vid == MLXSW_SP_DEFAULT_VID;
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
int err;
|
|
|
|
|
|
2018-12-19 06:08:43 +00:00
|
|
|
mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
|
|
|
|
|
if (mlxsw_sp_port_vlan)
|
|
|
|
|
return ERR_PTR(-EEXIST);
|
|
|
|
|
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
|
|
|
|
|
if (err)
|
|
|
|
|
return ERR_PTR(err);
|
2017-05-26 08:37:26 +02:00
|
|
|
|
|
|
|
|
mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
if (!mlxsw_sp_port_vlan) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto err_port_vlan_alloc;
|
|
|
|
|
}
|
2017-05-26 08:37:26 +02:00
|
|
|
|
|
|
|
|
mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
|
|
|
|
|
mlxsw_sp_port_vlan->vid = vid;
|
|
|
|
|
list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
|
|
|
|
|
|
|
|
|
|
return mlxsw_sp_port_vlan;
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
|
|
|
|
|
err_port_vlan_alloc:
|
|
|
|
|
mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
|
|
|
|
|
return ERR_PTR(err);
|
2017-05-26 08:37:26 +02:00
|
|
|
}
|
|
|
|
|
|
2018-12-19 06:08:43 +00:00
|
|
|
void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
|
2017-05-26 08:37:26 +02:00
|
|
|
{
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
|
|
|
|
|
u16 vid = mlxsw_sp_port_vlan->vid;
|
2017-05-26 08:37:28 +02:00
|
|
|
|
2018-12-20 19:42:32 +00:00
|
|
|
mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
|
2018-12-19 06:08:43 +00:00
|
|
|
list_del(&mlxsw_sp_port_vlan->list);
|
|
|
|
|
kfree(mlxsw_sp_port_vlan);
|
|
|
|
|
mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
|
2017-05-26 08:37:26 +02:00
|
|
|
}
|
|
|
|
|
|
2016-08-17 16:39:30 +02:00
|
|
|
static int mlxsw_sp_port_add_vid(struct net_device *dev,
|
|
|
|
|
__be16 __always_unused proto, u16 vid)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
/* VLAN 0 is added to HW filter when device goes up, but it is
|
|
|
|
|
* reserved in our case, so simply return.
|
|
|
|
|
*/
|
|
|
|
|
if (!vid)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2018-12-19 06:08:43 +00:00
|
|
|
return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2016-07-02 11:00:10 +02:00
|
|
|
static int mlxsw_sp_port_kill_vid(struct net_device *dev,
|
|
|
|
|
__be16 __always_unused proto, u16 vid)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
2017-05-26 08:37:26 +02:00
|
|
|
struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
/* VLAN 0 is removed from HW filter when device goes down, but
|
|
|
|
|
* it is reserved in our case, so simply return.
|
|
|
|
|
*/
|
|
|
|
|
if (!vid)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2017-05-26 08:37:26 +02:00
|
|
|
mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
if (!mlxsw_sp_port_vlan)
|
2015-10-16 14:01:37 +02:00
|
|
|
return 0;
|
2018-12-19 06:08:43 +00:00
|
|
|
mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
|
2017-05-26 08:37:26 +02:00
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-11 00:55:13 +03:00
|
|
|
static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
struct flow_block_offload *f)
|
|
|
|
|
{
|
|
|
|
|
switch (f->binder_type) {
|
|
|
|
|
case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS:
|
|
|
|
|
return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true);
|
|
|
|
|
case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS:
|
|
|
|
|
return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false);
|
2020-07-11 00:55:14 +03:00
|
|
|
case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP:
|
|
|
|
|
return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f);
|
2020-07-11 00:55:13 +03:00
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-07 10:15:24 +02:00
|
|
|
static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
|
2017-08-07 10:15:32 +02:00
|
|
|
void *type_data)
|
2017-08-07 10:15:24 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
|
2017-08-07 10:15:17 +02:00
|
|
|
switch (type) {
|
2017-10-19 15:50:37 +02:00
|
|
|
case TC_SETUP_BLOCK:
|
|
|
|
|
return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
|
2017-11-06 07:23:45 +01:00
|
|
|
case TC_SETUP_QDISC_RED:
|
|
|
|
|
return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
|
2018-01-14 12:33:16 +01:00
|
|
|
case TC_SETUP_QDISC_PRIO:
|
|
|
|
|
return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
|
2019-12-18 14:55:19 +00:00
|
|
|
case TC_SETUP_QDISC_ETS:
|
|
|
|
|
return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
|
2020-01-24 15:23:14 +02:00
|
|
|
case TC_SETUP_QDISC_TBF:
|
|
|
|
|
return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
|
2020-03-05 09:16:43 +02:00
|
|
|
case TC_SETUP_QDISC_FIFO:
|
|
|
|
|
return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
|
2017-08-07 10:15:17 +02:00
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
2016-07-21 12:03:17 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-12-06 09:41:12 +01:00
|
|
|
static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
|
2018-01-17 11:46:56 +01:00
|
|
|
if (!enable) {
|
2020-04-27 18:12:59 +03:00
|
|
|
if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) ||
|
2020-04-27 18:13:08 +03:00
|
|
|
mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) {
|
2018-01-17 11:46:56 +01:00
|
|
|
netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
2020-04-27 18:12:59 +03:00
|
|
|
mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block);
|
|
|
|
|
mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block);
|
2018-01-17 11:46:56 +01:00
|
|
|
} else {
|
2020-04-27 18:12:59 +03:00
|
|
|
mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block);
|
|
|
|
|
mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block);
|
2017-12-06 09:41:12 +01:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-05 09:48:06 +03:00
|
|
|
static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
char pplr_pl[MLXSW_REG_PPLR_LEN];
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (netif_running(dev))
|
|
|
|
|
mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
|
|
|
|
|
err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
|
|
|
|
|
pplr_pl);
|
|
|
|
|
|
|
|
|
|
if (netif_running(dev))
|
|
|
|
|
mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-12-06 09:41:12 +01:00
|
|
|
typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_handle_feature(struct net_device *dev,
|
|
|
|
|
netdev_features_t wanted_features,
|
|
|
|
|
netdev_features_t feature,
|
|
|
|
|
mlxsw_sp_feature_handler feature_handler)
|
|
|
|
|
{
|
|
|
|
|
netdev_features_t changes = wanted_features ^ dev->features;
|
|
|
|
|
bool enable = !!(wanted_features & feature);
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!(changes & feature))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err = feature_handler(dev, enable);
|
|
|
|
|
if (err) {
|
|
|
|
|
netdev_err(dev, "%s feature %pNF failed, err %d\n",
|
|
|
|
|
enable ? "Enable" : "Disable", &feature, err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
|
dev->features |= feature;
|
|
|
|
|
else
|
|
|
|
|
dev->features &= ~feature;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int mlxsw_sp_set_features(struct net_device *dev,
|
|
|
|
|
netdev_features_t features)
|
|
|
|
|
{
|
2019-05-05 09:48:06 +03:00
|
|
|
netdev_features_t oper_features = dev->features;
|
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
|
|
err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
|
2017-12-06 09:41:12 +01:00
|
|
|
mlxsw_sp_feature_hw_tc);
|
2019-05-05 09:48:06 +03:00
|
|
|
err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
|
|
|
|
|
mlxsw_sp_feature_loopback);
|
|
|
|
|
|
|
|
|
|
if (err) {
|
|
|
|
|
dev->features = oper_features;
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
2017-12-06 09:41:12 +01:00
|
|
|
}
|
|
|
|
|
|
2019-03-28 13:56:38 +01:00
|
|
|
static struct devlink_port *
|
|
|
|
|
mlxsw_sp_port_get_devlink_port(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
|
|
|
|
|
return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:59 +03:00
|
|
|
static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
struct ifreq *ifr)
|
|
|
|
|
{
|
|
|
|
|
struct hwtstamp_config config;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
|
|
|
|
|
&config);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
struct ifreq *ifr)
|
|
|
|
|
{
|
|
|
|
|
struct hwtstamp_config config;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
|
|
|
|
|
&config);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
struct hwtstamp_config config = {0};
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
|
case SIOCSHWTSTAMP:
|
|
|
|
|
return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
|
|
|
|
|
case SIOCGHWTSTAMP:
|
|
|
|
|
return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
|
|
|
|
|
.ndo_open = mlxsw_sp_port_open,
|
|
|
|
|
.ndo_stop = mlxsw_sp_port_stop,
|
|
|
|
|
.ndo_start_xmit = mlxsw_sp_port_xmit,
|
2016-07-21 12:03:17 +02:00
|
|
|
.ndo_setup_tc = mlxsw_sp_setup_tc,
|
2015-12-03 12:12:22 +01:00
|
|
|
.ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
|
2015-10-16 14:01:37 +02:00
|
|
|
.ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
|
|
|
|
|
.ndo_change_mtu = mlxsw_sp_port_change_mtu,
|
|
|
|
|
.ndo_get_stats64 = mlxsw_sp_port_get_stats64,
|
2016-09-16 15:05:38 +02:00
|
|
|
.ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
|
|
|
|
|
.ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
|
2015-10-16 14:01:37 +02:00
|
|
|
.ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
|
|
|
|
|
.ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
|
2017-12-06 09:41:12 +01:00
|
|
|
.ndo_set_features = mlxsw_sp_set_features,
|
2019-03-28 13:56:38 +01:00
|
|
|
.ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port,
|
2019-06-30 09:04:59 +03:00
|
|
|
.ndo_do_ioctl = mlxsw_sp_port_ioctl,
|
2015-10-16 14:01:37 +02:00
|
|
|
};
|
|
|
|
|
|
2016-02-26 17:32:31 +01:00
|
|
|
static int
|
2019-10-31 11:42:13 +02:00
|
|
|
mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
|
2016-02-26 17:32:31 +01:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
2020-02-26 09:39:19 +01:00
|
|
|
u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
|
2019-02-22 13:56:40 +00:00
|
|
|
const struct mlxsw_sp_port_type_speed_ops *ops;
|
2016-02-26 17:32:31 +01:00
|
|
|
char ptys_pl[MLXSW_REG_PTYS_LEN];
|
2020-10-24 16:37:31 +03:00
|
|
|
u32 eth_proto_cap_masked;
|
2019-02-22 13:56:40 +00:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
ops = mlxsw_sp->port_type_speed_ops;
|
|
|
|
|
|
2020-10-24 16:37:31 +03:00
|
|
|
/* Set advertised speeds to speeds supported by both the driver
|
|
|
|
|
* and the device.
|
|
|
|
|
*/
|
2020-02-26 09:39:19 +01:00
|
|
|
ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
0, false);
|
|
|
|
|
err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
|
2019-02-22 13:56:40 +00:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
2016-02-26 17:32:31 +01:00
|
|
|
|
2020-02-26 09:39:19 +01:00
|
|
|
ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
|
|
|
|
|
ð_proto_admin, ð_proto_oper);
|
2020-10-24 16:37:31 +03:00
|
|
|
eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap);
|
2019-02-22 13:56:40 +00:00
|
|
|
ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
|
2020-10-24 16:37:31 +03:00
|
|
|
eth_proto_cap_masked,
|
|
|
|
|
mlxsw_sp_port->link.autoneg);
|
2016-02-26 17:32:31 +01:00
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-20 09:52:50 +02:00
|
|
|
int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
|
|
|
|
|
{
|
|
|
|
|
const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char ptys_pl[MLXSW_REG_PTYS_LEN];
|
|
|
|
|
u32 eth_proto_oper;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
|
|
|
|
|
port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
|
|
|
|
|
mlxsw_sp_port->local_port, 0,
|
|
|
|
|
false);
|
|
|
|
|
err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
|
|
|
|
|
ð_proto_oper);
|
|
|
|
|
*speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-06 17:10:10 +02:00
|
|
|
int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
|
|
|
|
|
bool dwrr, u8 dwrr_weight)
|
2016-04-06 17:10:08 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char qeec_pl[MLXSW_REG_QEEC_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
|
|
|
|
|
next_index);
|
|
|
|
|
mlxsw_reg_qeec_de_set(qeec_pl, true);
|
|
|
|
|
mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
|
|
|
|
|
mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-06 17:10:11 +02:00
|
|
|
int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
enum mlxsw_reg_qeec_hr hr, u8 index,
|
2020-01-24 15:23:13 +02:00
|
|
|
u8 next_index, u32 maxrate, u8 burst_size)
|
2016-04-06 17:10:08 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char qeec_pl[MLXSW_REG_QEEC_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
|
|
|
|
|
next_index);
|
|
|
|
|
mlxsw_reg_qeec_mase_set(qeec_pl, true);
|
|
|
|
|
mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
|
2020-01-24 15:23:13 +02:00
|
|
|
mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
|
2016-04-06 17:10:08 +02:00
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-31 09:56:44 +00:00
|
|
|
static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
enum mlxsw_reg_qeec_hr hr, u8 index,
|
|
|
|
|
u8 next_index, u32 minrate)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char qeec_pl[MLXSW_REG_QEEC_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
|
|
|
|
|
next_index);
|
|
|
|
|
mlxsw_reg_qeec_mise_set(qeec_pl, true);
|
|
|
|
|
mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
|
|
|
|
|
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-06 17:10:10 +02:00
|
|
|
int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u8 switch_prio, u8 tclass)
|
2016-04-06 17:10:08 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char qtct_pl[MLXSW_REG_QTCT_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
|
|
|
|
|
tclass);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
|
|
/* Setup the elements hierarcy, so that each TC is linked to
|
|
|
|
|
* one subgroup, which are all member in the same group.
|
|
|
|
|
*/
|
|
|
|
|
err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
|
2016-04-06 17:10:08 +02:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_SUBGROUP, i,
|
2016-04-06 17:10:08 +02:00
|
|
|
0, false, 0);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_TC, i, i,
|
2016-04-06 17:10:08 +02:00
|
|
|
false, 0);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_TC,
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
i + 8, i,
|
2019-04-18 07:14:13 +00:00
|
|
|
true, 100);
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
2016-04-06 17:10:08 +02:00
|
|
|
}
|
|
|
|
|
|
2019-07-04 10:07:34 +03:00
|
|
|
/* Make sure the max shaper is disabled in all hierarchies that support
|
|
|
|
|
* it. Note that this disables ptps (PTP shaper), but that is intended
|
|
|
|
|
* for the initial configuration.
|
2016-04-06 17:10:08 +02:00
|
|
|
*/
|
|
|
|
|
err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_PORT, 0, 0,
|
2020-01-24 15:23:13 +02:00
|
|
|
MLXSW_REG_QEEC_MAS_DIS, 0);
|
2016-04-06 17:10:08 +02:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_SUBGROUP,
|
2016-04-06 17:10:08 +02:00
|
|
|
i, 0,
|
2020-01-24 15:23:13 +02:00
|
|
|
MLXSW_REG_QEEC_MAS_DIS, 0);
|
2016-04-06 17:10:08 +02:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_TC,
|
2016-04-06 17:10:08 +02:00
|
|
|
i, i,
|
2020-01-24 15:23:13 +02:00
|
|
|
MLXSW_REG_QEEC_MAS_DIS, 0);
|
2016-04-06 17:10:08 +02:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
2018-09-20 09:21:24 +03:00
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_TC,
|
2018-09-20 09:21:24 +03:00
|
|
|
i + 8, i,
|
2020-01-24 15:23:13 +02:00
|
|
|
MLXSW_REG_QEEC_MAS_DIS, 0);
|
2018-09-20 09:21:24 +03:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
2016-04-06 17:10:08 +02:00
|
|
|
}
|
|
|
|
|
|
2018-10-31 09:56:44 +00:00
|
|
|
/* Configure the min shaper for multicast TCs. */
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
|
2019-12-18 14:55:11 +00:00
|
|
|
MLXSW_REG_QEEC_HR_TC,
|
2018-10-31 09:56:44 +00:00
|
|
|
i + 8, i,
|
|
|
|
|
MLXSW_REG_QEEC_MIS_MIN);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-06 17:10:08 +02:00
|
|
|
/* Map all priorities to traffic class 0. */
|
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
|
|
|
err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
bool enable)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char qtctm_pl[MLXSW_REG_QTCTM_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-27 10:50:13 +03:00
|
|
|
static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
u8 module = mlxsw_sp_port->mapping.module;
|
|
|
|
|
u64 overheat_counter;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, module,
|
|
|
|
|
&overheat_counter);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port->module_overheat_initial_val = overheat_counter;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-29 14:54:04 +02:00
|
|
|
int
|
2020-11-29 14:54:01 +02:00
|
|
|
mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
bool is_8021ad_tagged,
|
|
|
|
|
bool is_8021q_tagged)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char spvc_pl[MLXSW_REG_SPVC_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
is_8021ad_tagged, is_8021q_tagged);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-08 08:47:44 +02:00
|
|
|
static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
|
2019-10-31 11:42:17 +02:00
|
|
|
u8 split_base_local_port,
|
2019-10-31 11:42:13 +02:00
|
|
|
struct mlxsw_sp_port_mapping *port_mapping)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
|
2019-10-31 11:42:17 +02:00
|
|
|
bool split = !!split_base_local_port;
|
2015-10-16 14:01:37 +02:00
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
2020-07-09 16:18:17 +03:00
|
|
|
u32 lanes = port_mapping->width;
|
2015-10-16 14:01:37 +02:00
|
|
|
struct net_device *dev;
|
2020-07-09 16:18:19 +03:00
|
|
|
bool splittable;
|
2015-10-16 14:01:37 +02:00
|
|
|
int err;
|
|
|
|
|
|
2020-07-09 16:18:19 +03:00
|
|
|
splittable = lanes > 1 && !split;
|
2019-03-24 11:14:31 +01:00
|
|
|
err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
|
2019-10-31 11:42:13 +02:00
|
|
|
port_mapping->module + 1, split,
|
2020-07-09 16:18:17 +03:00
|
|
|
port_mapping->lane / lanes,
|
2020-07-09 16:18:19 +03:00
|
|
|
splittable, lanes,
|
2019-04-03 14:24:18 +02:00
|
|
|
mlxsw_sp->base_mac,
|
|
|
|
|
sizeof(mlxsw_sp->base_mac));
|
2017-06-08 08:47:44 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
|
|
|
|
|
local_port);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
|
2017-06-08 08:47:44 +02:00
|
|
|
if (!dev) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto err_alloc_etherdev;
|
|
|
|
|
}
|
2016-10-27 15:13:00 +02:00
|
|
|
SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
|
2019-10-03 11:49:33 +02:00
|
|
|
dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
|
2015-10-16 14:01:37 +02:00
|
|
|
mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
mlxsw_sp_port->dev = dev;
|
|
|
|
|
mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
|
|
|
|
|
mlxsw_sp_port->local_port = local_port;
|
2018-12-20 19:42:26 +00:00
|
|
|
mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
|
2016-02-26 17:32:31 +01:00
|
|
|
mlxsw_sp_port->split = split;
|
2019-10-31 11:42:17 +02:00
|
|
|
mlxsw_sp_port->split_base_local_port = split_base_local_port;
|
2019-10-31 11:42:13 +02:00
|
|
|
mlxsw_sp_port->mapping = *port_mapping;
|
2016-09-12 13:26:23 +02:00
|
|
|
mlxsw_sp_port->link.autoneg = 1;
|
2017-05-26 08:37:26 +02:00
|
|
|
INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
mlxsw_sp_port->pcpu_stats =
|
|
|
|
|
netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
|
|
|
|
|
if (!mlxsw_sp_port->pcpu_stats) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto err_alloc_stats;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-26 10:55:32 +02:00
|
|
|
INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
|
2016-09-16 15:05:38 +02:00
|
|
|
&update_stats_cache);
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
|
|
|
|
|
dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
|
|
|
|
|
|
2019-10-31 11:42:13 +02:00
|
|
|
err = mlxsw_sp_port_module_map(mlxsw_sp_port);
|
2017-06-08 08:47:44 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_module_map;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-08 08:16:02 +02:00
|
|
|
err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_swid_set;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_dev_addr_init;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
netif_carrier_off(dev);
|
|
|
|
|
|
|
|
|
|
dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
|
2016-07-21 12:03:17 +02:00
|
|
|
NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
|
2019-05-05 09:48:06 +03:00
|
|
|
dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
|
2015-10-16 14:01:37 +02:00
|
|
|
|
ethernet: use net core MTU range checking in more drivers
Somehow, I missed a healthy number of ethernet drivers in the last pass.
Most of these drivers either were in need of an updated max_mtu to make
jumbo frames possible to enable again. In a few cases, also setting a
different min_mtu to match previous lower bounds. There are also a few
drivers that had no upper bounds checking, so they're getting a brand new
ETH_MAX_MTU that is identical to IP_MAX_MTU, but accessible by includes
all ethernet and ethernet-like drivers all have already.
acenic:
- min_mtu = 0, max_mtu = 9000
amazon/ena:
- min_mtu = 128, max_mtu = adapter->max_mtu
amd/xgbe:
- min_mtu = 0, max_mtu = 9000
sb1250:
- min_mtu = 0, max_mtu = 1518
cxgb3:
- min_mtu = 81, max_mtu = 65535
cxgb4:
- min_mtu = 81, max_mtu = 9600
cxgb4vf:
- min_mtu = 81, max_mtu = 65535
benet:
- min_mtu = 256, max_mtu = 9000
ibmveth:
- min_mtu = 68, max_mtu = 65535
ibmvnic:
- min_mtu = adapter->min_mtu, max_mtu = adapter->max_mtu
- remove now redundant ibmvnic_change_mtu
jme:
- min_mtu = 1280, max_mtu = 9202
mv643xx_eth:
- min_mtu = 64, max_mtu = 9500
mlxsw:
- min_mtu = 0, max_mtu = 65535
- Basically bypassing the core checks, and instead relying on dynamic
checks in the respective switch drivers' ndo_change_mtu functions
ns83820:
- min_mtu = 0
- remove redundant ns83820_change_mtu, only checked for mtu > 1500
netxen:
- min_mtu = 0, max_mtu = 8000 (P2), max_mtu = 9600 (P3)
qlge:
- min_mtu = 1500, max_mtu = 9000
- driver only supports setting mtu to 1500 or 9000, so the core check only
rules out < 1500 and > 9000, qlge_change_mtu still needs to check that
the value is 1500 or 9000
qualcomm/emac:
- min_mtu = 46, max_mtu = 9194
xilinx_axienet:
- min_mtu = 64, max_mtu = 9000
Fixes: 61e84623ace3 ("net: centralize net_device min/max MTU checking")
CC: netdev@vger.kernel.org
CC: Jes Sorensen <jes@trained-monkey.org>
CC: Netanel Belgazal <netanel@annapurnalabs.com>
CC: Tom Lendacky <thomas.lendacky@amd.com>
CC: Santosh Raspatur <santosh@chelsio.com>
CC: Hariprasad S <hariprasad@chelsio.com>
CC: Sathya Perla <sathya.perla@broadcom.com>
CC: Ajit Khaparde <ajit.khaparde@broadcom.com>
CC: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
CC: Somnath Kotur <somnath.kotur@broadcom.com>
CC: Thomas Falcon <tlfalcon@linux.vnet.ibm.com>
CC: John Allen <jallen@linux.vnet.ibm.com>
CC: Guo-Fu Tseng <cooldavid@cooldavid.org>
CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
CC: Jiri Pirko <jiri@mellanox.com>
CC: Ido Schimmel <idosch@mellanox.com>
CC: Manish Chopra <manish.chopra@qlogic.com>
CC: Sony Chacko <sony.chacko@qlogic.com>
CC: Rajesh Borundia <rajesh.borundia@qlogic.com>
CC: Timur Tabi <timur@codeaurora.org>
CC: Anirudha Sarangi <anirudh@xilinx.com>
CC: John Linn <John.Linn@xilinx.com>
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-20 13:55:16 -04:00
|
|
|
dev->min_mtu = 0;
|
|
|
|
|
dev->max_mtu = ETH_MAX_MTU;
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
/* Each packet needs to have a Tx header (metadata) on top all other
|
|
|
|
|
* headers.
|
|
|
|
|
*/
|
2016-10-04 09:46:04 +02:00
|
|
|
dev->needed_headroom = MLXSW_TXHDR_LEN;
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_system_port_mapping_set;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:13 +02:00
|
|
|
err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
|
2016-02-26 17:32:31 +01:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_speed_by_width_set;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-13 18:46:08 +03:00
|
|
|
err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
|
|
|
|
|
&mlxsw_sp_port->max_speed);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_max_speed_get;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-13 18:46:07 +03:00
|
|
|
err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_max_mtu_get;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_mtu_set;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_port_admin_status_set;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_buffers_init;
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-06 17:10:08 +02:00
|
|
|
err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_ets_init;
|
|
|
|
|
}
|
|
|
|
|
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_tc_mc_mode;
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-06 17:10:09 +02:00
|
|
|
/* ETS and buffers must be initialized before DCB. */
|
|
|
|
|
err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_dcb_init;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:39 +02:00
|
|
|
err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
|
2017-05-16 19:38:35 +02:00
|
|
|
if (err) {
|
2017-05-26 08:37:39 +02:00
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
|
2017-05-16 19:38:35 +02:00
|
|
|
mlxsw_sp_port->local_port);
|
2017-05-26 08:37:39 +02:00
|
|
|
goto err_port_fids_init;
|
2017-05-16 19:38:35 +02:00
|
|
|
}
|
|
|
|
|
|
2018-01-10 14:59:57 +01:00
|
|
|
err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_qdiscs_init;
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-26 14:43:38 +03:00
|
|
|
err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
|
|
|
|
|
false);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_vlan_clear;
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-17 08:53:14 +00:00
|
|
|
err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_nve_init;
|
|
|
|
|
}
|
|
|
|
|
|
2020-11-29 14:54:02 +02:00
|
|
|
err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
|
|
|
|
|
ETH_P_8021Q);
|
2018-12-20 19:42:27 +00:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_pvid_set;
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-20 19:42:26 +00:00
|
|
|
mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
|
|
|
|
|
MLXSW_SP_DEFAULT_VID);
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
if (IS_ERR(mlxsw_sp_port_vlan)) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
|
2016-08-17 16:39:30 +02:00
|
|
|
mlxsw_sp_port->local_port);
|
2017-11-06 11:11:28 +00:00
|
|
|
err = PTR_ERR(mlxsw_sp_port_vlan);
|
2018-12-19 06:08:43 +00:00
|
|
|
goto err_port_vlan_create;
|
2016-08-17 16:39:30 +02:00
|
|
|
}
|
2018-12-20 19:42:30 +00:00
|
|
|
mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
|
2016-08-17 16:39:30 +02:00
|
|
|
|
2020-11-29 14:54:01 +02:00
|
|
|
/* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat
|
|
|
|
|
* only packets with 802.1q header as tagged packets.
|
|
|
|
|
*/
|
|
|
|
|
err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n",
|
|
|
|
|
local_port);
|
|
|
|
|
goto err_port_vlan_classification_set;
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-04 10:07:39 +03:00
|
|
|
INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
|
|
|
|
|
mlxsw_sp->ptp_ops->shaper_work);
|
|
|
|
|
|
2016-08-17 16:39:31 +02:00
|
|
|
mlxsw_sp->ports[local_port] = mlxsw_sp_port;
|
2020-09-27 10:50:13 +03:00
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_port_overheat_init_val_set;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
err = register_netdev(dev);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
goto err_register_netdev;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-28 21:35:57 +02:00
|
|
|
mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
|
2019-03-24 11:14:31 +01:00
|
|
|
mlxsw_sp_port, dev);
|
2017-10-26 10:55:32 +02:00
|
|
|
mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
|
2015-10-16 14:01:37 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_register_netdev:
|
2020-09-27 10:50:13 +03:00
|
|
|
err_port_overheat_init_val_set:
|
2020-11-29 14:54:01 +02:00
|
|
|
mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
|
|
|
|
|
err_port_vlan_classification_set:
|
2016-08-17 16:39:31 +02:00
|
|
|
mlxsw_sp->ports[local_port] = NULL;
|
2018-12-19 06:08:43 +00:00
|
|
|
mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
|
|
|
|
|
err_port_vlan_create:
|
2018-12-20 19:42:27 +00:00
|
|
|
err_port_pvid_set:
|
2018-10-17 08:53:14 +00:00
|
|
|
mlxsw_sp_port_nve_fini(mlxsw_sp_port);
|
|
|
|
|
err_port_nve_init:
|
2019-09-26 14:43:38 +03:00
|
|
|
err_port_vlan_clear:
|
2018-01-10 14:59:57 +01:00
|
|
|
mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
|
|
|
|
|
err_port_qdiscs_init:
|
2017-05-26 08:37:39 +02:00
|
|
|
mlxsw_sp_port_fids_fini(mlxsw_sp_port);
|
|
|
|
|
err_port_fids_init:
|
2016-08-04 17:36:22 +03:00
|
|
|
mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
|
2016-04-06 17:10:09 +02:00
|
|
|
err_port_dcb_init:
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
|
|
|
|
|
err_port_tc_mc_mode:
|
2016-04-06 17:10:08 +02:00
|
|
|
err_port_ets_init:
|
2020-09-16 09:35:14 +03:00
|
|
|
mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
|
2015-10-16 14:01:37 +02:00
|
|
|
err_port_buffers_init:
|
|
|
|
|
err_port_admin_status_set:
|
|
|
|
|
err_port_mtu_set:
|
2020-09-13 18:46:07 +03:00
|
|
|
err_port_max_mtu_get:
|
2020-09-13 18:46:08 +03:00
|
|
|
err_max_speed_get:
|
2016-02-26 17:32:31 +01:00
|
|
|
err_port_speed_by_width_set:
|
2015-10-16 14:01:37 +02:00
|
|
|
err_port_system_port_mapping_set:
|
|
|
|
|
err_dev_addr_init:
|
2016-09-08 08:16:02 +02:00
|
|
|
mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
|
|
|
|
|
err_port_swid_set:
|
2017-06-08 08:47:45 +02:00
|
|
|
mlxsw_sp_port_module_unmap(mlxsw_sp_port);
|
2017-06-08 08:47:44 +02:00
|
|
|
err_port_module_map:
|
2015-10-16 14:01:37 +02:00
|
|
|
free_percpu(mlxsw_sp_port->pcpu_stats);
|
|
|
|
|
err_alloc_stats:
|
|
|
|
|
free_netdev(dev);
|
2017-06-08 08:47:44 +02:00
|
|
|
err_alloc_etherdev:
|
2016-10-28 21:35:55 +02:00
|
|
|
mlxsw_core_port_fini(mlxsw_sp->core, local_port);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-08 08:47:44 +02:00
|
|
|
static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
|
|
|
|
|
|
2017-10-26 10:55:32 +02:00
|
|
|
cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
|
2019-07-04 10:07:39 +03:00
|
|
|
cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
|
2019-06-30 09:04:59 +03:00
|
|
|
mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
|
2016-10-28 21:35:55 +02:00
|
|
|
mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
|
2020-11-29 14:54:01 +02:00
|
|
|
mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
|
2016-08-17 16:39:31 +02:00
|
|
|
mlxsw_sp->ports[local_port] = NULL;
|
2018-12-20 19:42:29 +00:00
|
|
|
mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
|
2018-10-17 08:53:14 +00:00
|
|
|
mlxsw_sp_port_nve_fini(mlxsw_sp_port);
|
2018-01-10 14:59:57 +01:00
|
|
|
mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
|
2017-05-26 08:37:39 +02:00
|
|
|
mlxsw_sp_port_fids_fini(mlxsw_sp_port);
|
2016-04-06 17:10:09 +02:00
|
|
|
mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
|
mlxsw: spectrum: Configure MC-aware mode on mlxsw ports
In order to give unicast traffic precedence over BUM traffic, configure
multicast-aware mode on all ports.
Under multicast-aware regime, when assigning traffic class to a packet,
the switch doesn't merely take the value prescribed by the QTCT
register. For BUM traffic, it instead assigns that value plus 8.
ETS elements for TCs 8..15 thus need to be configured as well. Extend
mlxsw_sp_port_ets_init() so that it maps each of them to the same
subgroup as their corresponding TC from the range 0..7, such that TCs X
and X+8 map to the same subgroup.
The existing code configures TCs with strict priority. So far this was
immaterial, because each TC had its own subgroup. Now that two TCs share
a subgroup it becomes important. TCs are prioritized in order of 7, 6,
..., 0, 15, 14, ..., 8: the higher TCs used for BUM traffic end up being
deprioritized. Since that's what's needed, keep that configuration as it
is, and configure the new TCs likewise.
Finally in mlxsw_sp_port_create(), invoke configuration of QTCTM to
enable MC-aware mode on each port.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-08-05 09:03:08 +03:00
|
|
|
mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
|
2020-09-16 09:35:14 +03:00
|
|
|
mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
|
2016-02-26 17:32:28 +01:00
|
|
|
mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
|
2017-06-08 08:47:45 +02:00
|
|
|
mlxsw_sp_port_module_unmap(mlxsw_sp_port);
|
2017-01-09 11:25:47 +01:00
|
|
|
free_percpu(mlxsw_sp_port->pcpu_stats);
|
2017-05-26 08:37:26 +02:00
|
|
|
WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
|
2015-10-16 14:01:37 +02:00
|
|
|
free_netdev(mlxsw_sp_port->dev);
|
2016-10-28 21:35:55 +02:00
|
|
|
mlxsw_core_port_fini(mlxsw_sp->core, local_port);
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-16 18:04:21 +03:00
|
|
|
static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
|
|
|
|
|
if (!mlxsw_sp_port)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
|
|
|
|
|
mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
|
|
|
|
|
mlxsw_sp_port,
|
|
|
|
|
mlxsw_sp->base_mac,
|
|
|
|
|
sizeof(mlxsw_sp->base_mac));
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
|
|
|
|
|
goto err_core_cpu_port_init;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_core_cpu_port_init:
|
|
|
|
|
kfree(mlxsw_sp_port);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port =
|
|
|
|
|
mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
|
|
|
|
|
|
|
|
|
|
mlxsw_core_cpu_port_fini(mlxsw_sp->core);
|
|
|
|
|
mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
|
|
|
|
|
kfree(mlxsw_sp_port);
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-28 21:35:49 +02:00
|
|
|
static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
|
|
|
|
|
{
|
|
|
|
|
return mlxsw_sp->ports[local_port] != NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
2017-03-24 08:02:48 +01:00
|
|
|
for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
|
2016-10-28 21:35:49 +02:00
|
|
|
if (mlxsw_sp_port_created(mlxsw_sp, i))
|
|
|
|
|
mlxsw_sp_port_remove(mlxsw_sp, i);
|
2019-09-16 18:04:21 +03:00
|
|
|
mlxsw_sp_cpu_port_remove(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
kfree(mlxsw_sp->ports);
|
2020-05-21 15:11:44 +03:00
|
|
|
mlxsw_sp->ports = NULL;
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
2017-03-24 08:02:48 +01:00
|
|
|
unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
|
2019-10-31 11:42:11 +02:00
|
|
|
struct mlxsw_sp_port_mapping *port_mapping;
|
2015-10-16 14:01:37 +02:00
|
|
|
size_t alloc_size;
|
|
|
|
|
int i;
|
|
|
|
|
int err;
|
|
|
|
|
|
2017-03-24 08:02:48 +01:00
|
|
|
alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
|
2015-10-16 14:01:37 +02:00
|
|
|
mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
|
|
|
|
|
if (!mlxsw_sp->ports)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2019-09-16 18:04:21 +03:00
|
|
|
err = mlxsw_sp_cpu_port_create(mlxsw_sp);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_cpu_port_create;
|
|
|
|
|
|
2017-03-24 08:02:48 +01:00
|
|
|
for (i = 1; i < max_ports; i++) {
|
2019-10-31 11:42:11 +02:00
|
|
|
port_mapping = mlxsw_sp->port_mapping[i];
|
|
|
|
|
if (!port_mapping)
|
2016-02-26 17:32:29 +01:00
|
|
|
continue;
|
2019-10-31 11:42:17 +02:00
|
|
|
err = mlxsw_sp_port_create(mlxsw_sp, i, 0, port_mapping);
|
2015-10-16 14:01:37 +02:00
|
|
|
if (err)
|
|
|
|
|
goto err_port_create;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_port_create:
|
|
|
|
|
for (i--; i >= 1; i--)
|
2016-10-28 21:35:49 +02:00
|
|
|
if (mlxsw_sp_port_created(mlxsw_sp, i))
|
|
|
|
|
mlxsw_sp_port_remove(mlxsw_sp, i);
|
2019-09-16 18:04:21 +03:00
|
|
|
mlxsw_sp_cpu_port_remove(mlxsw_sp);
|
|
|
|
|
err_cpu_port_create:
|
2015-10-16 14:01:37 +02:00
|
|
|
kfree(mlxsw_sp->ports);
|
2020-05-21 15:11:44 +03:00
|
|
|
mlxsw_sp->ports = NULL;
|
2015-10-16 14:01:37 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:11 +02:00
|
|
|
static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
|
|
|
|
|
struct mlxsw_sp_port_mapping port_mapping;
|
|
|
|
|
int i;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp->port_mapping = kcalloc(max_ports,
|
|
|
|
|
sizeof(struct mlxsw_sp_port_mapping *),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!mlxsw_sp->port_mapping)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
for (i = 1; i < max_ports; i++) {
|
2020-12-14 13:30:31 +02:00
|
|
|
if (mlxsw_core_port_is_xm(mlxsw_sp->core, i))
|
|
|
|
|
continue;
|
|
|
|
|
|
2019-10-31 11:42:11 +02:00
|
|
|
err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &port_mapping);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_port_module_info_get;
|
|
|
|
|
if (!port_mapping.width)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp->port_mapping[i] = kmemdup(&port_mapping,
|
|
|
|
|
sizeof(port_mapping),
|
|
|
|
|
GFP_KERNEL);
|
2019-11-06 14:52:31 +00:00
|
|
|
if (!mlxsw_sp->port_mapping[i]) {
|
|
|
|
|
err = -ENOMEM;
|
2019-10-31 11:42:11 +02:00
|
|
|
goto err_port_module_info_dup;
|
2019-11-06 14:52:31 +00:00
|
|
|
}
|
2019-10-31 11:42:11 +02:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_port_module_info_get:
|
|
|
|
|
err_port_module_info_dup:
|
|
|
|
|
for (i--; i >= 1; i--)
|
|
|
|
|
kfree(mlxsw_sp->port_mapping[i]);
|
|
|
|
|
kfree(mlxsw_sp->port_mapping);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
|
|
|
|
|
kfree(mlxsw_sp->port_mapping[i]);
|
|
|
|
|
kfree(mlxsw_sp->port_mapping);
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:08 +02:00
|
|
|
static u8 mlxsw_sp_cluster_base_port_get(u8 local_port, unsigned int max_width)
|
2016-02-26 17:32:31 +01:00
|
|
|
{
|
2019-10-31 11:42:08 +02:00
|
|
|
u8 offset = (local_port - 1) % max_width;
|
2016-02-26 17:32:31 +01:00
|
|
|
|
|
|
|
|
return local_port - offset;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:12 +02:00
|
|
|
static int
|
|
|
|
|
mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
|
|
|
|
|
struct mlxsw_sp_port_mapping *port_mapping,
|
|
|
|
|
unsigned int count, u8 offset)
|
2016-06-09 09:51:39 +02:00
|
|
|
{
|
2019-10-31 11:42:13 +02:00
|
|
|
struct mlxsw_sp_port_mapping split_port_mapping;
|
2016-06-09 09:51:39 +02:00
|
|
|
int err, i;
|
|
|
|
|
|
2019-10-31 11:42:13 +02:00
|
|
|
split_port_mapping = *port_mapping;
|
|
|
|
|
split_port_mapping.width /= count;
|
2016-06-09 09:51:39 +02:00
|
|
|
for (i = 0; i < count; i++) {
|
2019-05-02 14:13:09 +03:00
|
|
|
err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
|
2019-10-31 11:42:17 +02:00
|
|
|
base_port, &split_port_mapping);
|
2016-06-09 09:51:39 +02:00
|
|
|
if (err)
|
|
|
|
|
goto err_port_create;
|
2019-10-31 11:42:13 +02:00
|
|
|
split_port_mapping.lane += split_port_mapping.width;
|
2016-06-09 09:51:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_port_create:
|
|
|
|
|
for (i--; i >= 0; i--)
|
2019-05-02 14:13:09 +03:00
|
|
|
if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
|
|
|
|
|
mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
|
2016-06-09 09:51:39 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
|
2019-10-31 11:42:20 +02:00
|
|
|
u8 base_port,
|
|
|
|
|
unsigned int count, u8 offset)
|
2016-06-09 09:51:39 +02:00
|
|
|
{
|
2019-10-31 11:42:11 +02:00
|
|
|
struct mlxsw_sp_port_mapping *port_mapping;
|
2016-06-09 09:51:39 +02:00
|
|
|
int i;
|
|
|
|
|
|
2019-10-31 11:42:20 +02:00
|
|
|
/* Go over original unsplit ports in the gap and recreate them. */
|
|
|
|
|
for (i = 0; i < count * offset; i++) {
|
|
|
|
|
port_mapping = mlxsw_sp->port_mapping[base_port + i];
|
2019-10-31 11:42:11 +02:00
|
|
|
if (!port_mapping)
|
2017-11-21 09:42:21 +01:00
|
|
|
continue;
|
2019-10-31 11:42:20 +02:00
|
|
|
mlxsw_sp_port_create(mlxsw_sp, base_port + i, 0, port_mapping);
|
2016-06-09 09:51:39 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:15 +02:00
|
|
|
static int mlxsw_sp_local_ports_offset(struct mlxsw_core *mlxsw_core,
|
|
|
|
|
unsigned int count,
|
|
|
|
|
unsigned int max_width)
|
|
|
|
|
{
|
|
|
|
|
enum mlxsw_res_id local_ports_in_x_res_id;
|
|
|
|
|
int split_width = max_width / count;
|
|
|
|
|
|
|
|
|
|
if (split_width == 1)
|
|
|
|
|
local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_1X;
|
|
|
|
|
else if (split_width == 2)
|
|
|
|
|
local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_2X;
|
2019-10-31 11:42:16 +02:00
|
|
|
else if (split_width == 4)
|
|
|
|
|
local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_4X;
|
2019-10-31 11:42:15 +02:00
|
|
|
else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (!mlxsw_core_res_valid(mlxsw_core, local_ports_in_x_res_id))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
return mlxsw_core_res_get(mlxsw_core, local_ports_in_x_res_id);
|
|
|
|
|
}
|
|
|
|
|
|
2020-05-21 15:11:44 +03:00
|
|
|
static struct mlxsw_sp_port *
|
|
|
|
|
mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u8 local_port)
|
|
|
|
|
{
|
|
|
|
|
if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
|
|
|
|
|
return mlxsw_sp->ports[local_port];
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-08 19:11:23 +02:00
|
|
|
static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
|
2018-06-05 08:14:11 -07:00
|
|
|
unsigned int count,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2016-02-26 17:32:31 +01:00
|
|
|
{
|
2016-04-08 19:11:23 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
2019-10-31 11:42:12 +02:00
|
|
|
struct mlxsw_sp_port_mapping port_mapping;
|
2016-02-26 17:32:31 +01:00
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
2019-10-31 11:42:08 +02:00
|
|
|
int max_width;
|
2019-10-31 11:42:12 +02:00
|
|
|
u8 base_port;
|
2019-10-31 11:42:15 +02:00
|
|
|
int offset;
|
2016-02-26 17:32:31 +01:00
|
|
|
int i;
|
|
|
|
|
int err;
|
|
|
|
|
|
2020-05-21 15:11:44 +03:00
|
|
|
mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
|
2016-02-26 17:32:31 +01:00
|
|
|
if (!mlxsw_sp_port) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
|
|
|
|
|
local_port);
|
2018-06-05 08:14:11 -07:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
|
2016-02-26 17:32:31 +01:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:08 +02:00
|
|
|
max_width = mlxsw_core_module_max_width(mlxsw_core,
|
|
|
|
|
mlxsw_sp_port->mapping.module);
|
|
|
|
|
if (max_width < 0) {
|
|
|
|
|
netdev_err(mlxsw_sp_port->dev, "Cannot get max width of port module\n");
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Cannot get max width of port module");
|
|
|
|
|
return max_width;
|
|
|
|
|
}
|
2016-06-09 09:51:40 +02:00
|
|
|
|
2020-07-09 16:18:21 +03:00
|
|
|
/* Split port with non-max cannot be split. */
|
|
|
|
|
if (mlxsw_sp_port->mapping.width != max_width) {
|
2019-10-31 11:42:10 +02:00
|
|
|
netdev_err(mlxsw_sp_port->dev, "Port cannot be split\n");
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Port cannot be split");
|
2016-02-26 17:32:31 +01:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:15 +02:00
|
|
|
offset = mlxsw_sp_local_ports_offset(mlxsw_core, count, max_width);
|
|
|
|
|
if (offset < 0) {
|
|
|
|
|
netdev_err(mlxsw_sp_port->dev, "Cannot obtain local port offset\n");
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Cannot obtain local port offset");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:19 +02:00
|
|
|
/* Only in case max split is being done, the local port and
|
|
|
|
|
* base port may differ.
|
|
|
|
|
*/
|
|
|
|
|
base_port = count == max_width ?
|
|
|
|
|
mlxsw_sp_cluster_base_port_get(local_port, max_width) :
|
|
|
|
|
local_port;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < count * offset; i++) {
|
|
|
|
|
/* Expect base port to exist and also the one in the middle in
|
|
|
|
|
* case of maximal split count.
|
|
|
|
|
*/
|
|
|
|
|
if (i == 0 || (count == max_width && i == count / 2))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) {
|
2016-02-26 17:32:31 +01:00
|
|
|
netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
|
2018-06-05 08:14:11 -07:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
|
2016-02-26 17:32:31 +01:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:12 +02:00
|
|
|
port_mapping = mlxsw_sp_port->mapping;
|
|
|
|
|
|
2016-02-26 17:32:31 +01:00
|
|
|
for (i = 0; i < count; i++)
|
2019-05-02 14:13:09 +03:00
|
|
|
if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
|
|
|
|
|
mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
|
2016-02-26 17:32:31 +01:00
|
|
|
|
2019-10-31 11:42:12 +02:00
|
|
|
err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, &port_mapping,
|
|
|
|
|
count, offset);
|
2016-06-09 09:51:39 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
|
|
|
|
|
goto err_port_split_create;
|
2016-02-26 17:32:31 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
2016-06-09 09:51:39 +02:00
|
|
|
err_port_split_create:
|
2019-10-31 11:42:20 +02:00
|
|
|
mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count, offset);
|
2016-02-26 17:32:31 +01:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2018-06-05 08:14:11 -07:00
|
|
|
static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2016-02-26 17:32:31 +01:00
|
|
|
{
|
2016-04-08 19:11:23 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
2016-02-26 17:32:31 +01:00
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
|
|
|
|
unsigned int count;
|
2019-10-31 11:42:08 +02:00
|
|
|
int max_width;
|
|
|
|
|
u8 base_port;
|
2019-10-31 11:42:15 +02:00
|
|
|
int offset;
|
2016-02-26 17:32:31 +01:00
|
|
|
int i;
|
|
|
|
|
|
2020-05-21 15:11:44 +03:00
|
|
|
mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
|
2016-02-26 17:32:31 +01:00
|
|
|
if (!mlxsw_sp_port) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
|
|
|
|
|
local_port);
|
2018-06-05 08:14:11 -07:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
|
2016-02-26 17:32:31 +01:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!mlxsw_sp_port->split) {
|
2018-06-05 08:14:11 -07:00
|
|
|
netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Port was not split");
|
2016-02-26 17:32:31 +01:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:08 +02:00
|
|
|
max_width = mlxsw_core_module_max_width(mlxsw_core,
|
|
|
|
|
mlxsw_sp_port->mapping.module);
|
|
|
|
|
if (max_width < 0) {
|
|
|
|
|
netdev_err(mlxsw_sp_port->dev, "Cannot get max width of port module\n");
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Cannot get max width of port module");
|
|
|
|
|
return max_width;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
count = max_width / mlxsw_sp_port->mapping.width;
|
2016-02-26 17:32:31 +01:00
|
|
|
|
2019-10-31 11:42:15 +02:00
|
|
|
offset = mlxsw_sp_local_ports_offset(mlxsw_core, count, max_width);
|
|
|
|
|
if (WARN_ON(offset < 0)) {
|
|
|
|
|
netdev_err(mlxsw_sp_port->dev, "Cannot obtain local port offset\n");
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Cannot obtain local port offset");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
2019-05-02 14:13:09 +03:00
|
|
|
|
2019-10-31 11:42:17 +02:00
|
|
|
base_port = mlxsw_sp_port->split_base_local_port;
|
2016-02-26 17:32:31 +01:00
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
2019-05-02 14:13:09 +03:00
|
|
|
if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
|
|
|
|
|
mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
|
2016-02-26 17:32:31 +01:00
|
|
|
|
2019-10-31 11:42:20 +02:00
|
|
|
mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count, offset);
|
2016-02-26 17:32:31 +01:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-15 13:53:48 +02:00
|
|
|
static void
|
|
|
|
|
mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < TC_MAX_QUEUE; i++)
|
|
|
|
|
mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
|
|
|
|
|
char *pude_pl, void *priv)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = priv;
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
|
|
|
|
enum mlxsw_reg_pude_oper_status status;
|
|
|
|
|
u8 local_port;
|
|
|
|
|
|
|
|
|
|
local_port = mlxsw_reg_pude_local_port_get(pude_pl);
|
|
|
|
|
mlxsw_sp_port = mlxsw_sp->ports[local_port];
|
2016-07-02 11:00:14 +02:00
|
|
|
if (!mlxsw_sp_port)
|
2015-10-16 14:01:37 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
status = mlxsw_reg_pude_oper_status_get(pude_pl);
|
|
|
|
|
if (status == MLXSW_PORT_OPER_STATUS_UP) {
|
|
|
|
|
netdev_info(mlxsw_sp_port->dev, "link up\n");
|
|
|
|
|
netif_carrier_on(mlxsw_sp_port->dev);
|
2019-07-04 10:07:39 +03:00
|
|
|
mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
|
2015-10-16 14:01:37 +02:00
|
|
|
} else {
|
|
|
|
|
netdev_info(mlxsw_sp_port->dev, "link down\n");
|
|
|
|
|
netif_carrier_off(mlxsw_sp_port->dev);
|
2020-01-15 13:53:48 +02:00
|
|
|
mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:56 +03:00
|
|
|
static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
char *mtpptr_pl, bool ingress)
|
|
|
|
|
{
|
|
|
|
|
u8 local_port;
|
|
|
|
|
u8 num_rec;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
|
|
|
|
|
num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
|
|
|
|
|
for (i = 0; i < num_rec; i++) {
|
|
|
|
|
u8 domain_number;
|
|
|
|
|
u8 message_type;
|
|
|
|
|
u16 sequence_id;
|
|
|
|
|
u64 timestamp;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
|
|
|
|
|
&domain_number, &sequence_id,
|
|
|
|
|
×tamp);
|
|
|
|
|
mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
|
|
|
|
|
message_type, domain_number,
|
|
|
|
|
sequence_id, timestamp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
|
|
|
|
|
char *mtpptr_pl, void *priv)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = priv;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
|
|
|
|
|
char *mtpptr_pl, void *priv)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = priv;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
|
|
|
|
|
}
|
|
|
|
|
|
mlxsw: spectrum: PTP: Hook into packet receive path
When configured, the Spectrum hardware can recognize PTP packets and
trap them to the CPU using dedicated traps, PTP0 and PTP1.
One reason to get PTP packets under dedicated traps is to have a
separate policer suitable for the amount of PTP traffic expected when
switch is operated as a boundary clock. For this, add two new trap
groups, MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0 and _PTP1, and associate the
two PTP traps with these two groups.
In the driver, specifically for Spectrum-1, event PTP packets will need
to be paired up with their timestamps. Those arrive through a different
set of traps, added later in the patch set. To support this future use,
introduce a new PTP op, ptp_receive.
It is possible to configure which PTP messages should be trapped under
which PTP trap. On Spectrum systems, we will use PTP0 for event
packets (which need timestamping), and PTP1 for control packets (which
do not). Thus configure PTP0 trap with a custom callback that defers to
the ptp_receive op.
Additionally, L2 PTP packets are actually trapped through the LLDP trap,
not through any of the PTP traps. So treat the LLDP trap the same way as
the PTP0 trap. Unlike PTP traps, which are currently still disabled,
LLDP trap is active. Correspondingly, have all the implementations of
the ptp_receive op return true, which the handler treats as a signal to
forward the packet immediately.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:51 +03:00
|
|
|
void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
|
|
|
|
|
u8 local_port, void *priv)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = priv;
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
|
|
|
|
|
struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
|
|
|
|
|
|
|
|
|
|
if (unlikely(!mlxsw_sp_port)) {
|
|
|
|
|
dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
|
|
|
|
|
local_port);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
skb->dev = mlxsw_sp_port->dev;
|
|
|
|
|
|
|
|
|
|
pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
|
|
|
|
|
u64_stats_update_begin(&pcpu_stats->syncp);
|
|
|
|
|
pcpu_stats->rx_packets++;
|
|
|
|
|
pcpu_stats->rx_bytes += skb->len;
|
|
|
|
|
u64_stats_update_end(&pcpu_stats->syncp);
|
|
|
|
|
|
|
|
|
|
skb->protocol = eth_type_trans(skb, skb->dev);
|
|
|
|
|
netif_receive_skb(skb);
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-25 18:42:40 +02:00
|
|
|
static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
|
|
|
|
|
void *priv)
|
|
|
|
|
{
|
|
|
|
|
skb->offload_fwd_mark = 1;
|
2016-11-25 10:33:32 +01:00
|
|
|
return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
|
2016-08-25 18:42:40 +02:00
|
|
|
}
|
|
|
|
|
|
2018-12-04 08:15:10 +00:00
|
|
|
static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
|
2017-10-03 09:58:10 +02:00
|
|
|
u8 local_port, void *priv)
|
|
|
|
|
{
|
2018-12-04 08:15:10 +00:00
|
|
|
skb->offload_l3_fwd_mark = 1;
|
2017-10-03 09:58:10 +02:00
|
|
|
skb->offload_fwd_mark = 1;
|
|
|
|
|
return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
|
|
|
|
|
}
|
|
|
|
|
|
2020-05-29 21:36:48 +03:00
|
|
|
void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
|
|
|
|
|
u8 local_port)
|
|
|
|
|
{
|
|
|
|
|
mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
|
|
|
|
|
}
|
|
|
|
|
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
|
2016-11-25 10:33:39 +01:00
|
|
|
MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
_is_ctrl, SP_##_trap_group, DISCARD)
|
2016-11-25 10:33:32 +01:00
|
|
|
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
|
2016-11-25 10:33:32 +01:00
|
|
|
MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
_is_ctrl, SP_##_trap_group, DISCARD)
|
|
|
|
|
|
2018-12-04 08:15:10 +00:00
|
|
|
#define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
|
|
|
|
|
MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
|
2017-10-03 09:58:10 +02:00
|
|
|
_is_ctrl, SP_##_trap_group, DISCARD)
|
|
|
|
|
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
#define MLXSW_SP_EVENTL(_func, _trap_id) \
|
|
|
|
|
MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
|
2016-08-25 18:42:38 +02:00
|
|
|
|
2016-11-25 10:33:35 +01:00
|
|
|
static const struct mlxsw_listener mlxsw_sp_listener[] = {
|
|
|
|
|
/* Events */
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
|
2016-11-25 10:33:29 +01:00
|
|
|
/* L2 traps */
|
2020-05-26 02:05:47 +03:00
|
|
|
MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),
|
2016-08-25 18:42:38 +02:00
|
|
|
/* L3 traps */
|
2017-07-18 10:10:11 +02:00
|
|
|
MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
|
|
|
|
|
false),
|
2020-05-26 02:05:54 +03:00
|
|
|
MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
|
2017-07-18 10:10:11 +02:00
|
|
|
MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
|
|
|
|
|
false),
|
2020-01-05 18:20:50 +02:00
|
|
|
MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
|
|
|
|
|
ROUTER_EXP, false),
|
2020-01-05 18:20:52 +02:00
|
|
|
MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
|
|
|
|
|
ROUTER_EXP, false),
|
2020-01-05 18:20:54 +02:00
|
|
|
MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
|
|
|
|
|
ROUTER_EXP, false),
|
2020-01-05 18:20:56 +02:00
|
|
|
MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
|
|
|
|
|
ROUTER_EXP, false),
|
2017-09-19 10:00:20 +02:00
|
|
|
/* Multicast Router Traps */
|
|
|
|
|
MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
|
2018-12-04 08:15:10 +00:00
|
|
|
MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
|
2018-10-11 07:48:11 +00:00
|
|
|
/* NVE traps */
|
2020-05-25 00:51:04 +03:00
|
|
|
MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false),
|
2015-10-16 14:01:37 +02:00
|
|
|
};
|
|
|
|
|
|
2019-06-30 09:04:50 +03:00
|
|
|
static const struct mlxsw_listener mlxsw_sp1_listener[] = {
|
2019-06-30 09:04:56 +03:00
|
|
|
/* Events */
|
|
|
|
|
MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
|
|
|
|
|
MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
|
2019-06-30 09:04:50 +03:00
|
|
|
};
|
|
|
|
|
|
2016-11-25 10:33:47 +01:00
|
|
|
static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
2020-03-30 22:38:26 +03:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
2016-11-25 10:33:47 +01:00
|
|
|
char qpcr_pl[MLXSW_REG_QPCR_LEN];
|
|
|
|
|
enum mlxsw_reg_qpcr_ir_units ir_units;
|
|
|
|
|
int max_cpu_policers;
|
|
|
|
|
bool is_bytes;
|
|
|
|
|
u8 burst_size;
|
|
|
|
|
u32 rate;
|
|
|
|
|
int i, err;
|
|
|
|
|
|
|
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
|
|
|
|
|
|
|
|
|
|
ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
|
|
|
|
|
for (i = 0; i < max_cpu_policers; i++) {
|
|
|
|
|
is_bytes = false;
|
|
|
|
|
switch (i) {
|
|
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
|
2017-09-19 10:00:20 +02:00
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
|
2020-05-26 02:05:47 +03:00
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
|
2019-02-18 07:19:44 +00:00
|
|
|
rate = 1024;
|
|
|
|
|
burst_size = 7;
|
2016-11-25 10:33:47 +01:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-30 22:38:26 +03:00
|
|
|
__set_bit(i, mlxsw_sp->trap->policers_usage);
|
2016-11-25 10:33:47 +01:00
|
|
|
mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
|
|
|
|
|
burst_size);
|
|
|
|
|
err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-25 10:33:42 +01:00
|
|
|
static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
char htgt_pl[MLXSW_REG_HTGT_LEN];
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
enum mlxsw_reg_htgt_trap_group i;
|
2016-11-25 10:33:47 +01:00
|
|
|
int max_cpu_policers;
|
2016-11-25 10:33:42 +01:00
|
|
|
int max_trap_groups;
|
|
|
|
|
u8 priority, tc;
|
2016-11-25 10:33:47 +01:00
|
|
|
u16 policer_id;
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
int err;
|
2016-11-25 10:33:42 +01:00
|
|
|
|
|
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
|
2016-11-25 10:33:47 +01:00
|
|
|
max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
|
2016-11-25 10:33:42 +01:00
|
|
|
|
|
|
|
|
for (i = 0; i < max_trap_groups; i++) {
|
2016-11-25 10:33:47 +01:00
|
|
|
policer_id = i;
|
2016-11-25 10:33:42 +01:00
|
|
|
switch (i) {
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
|
2017-09-19 10:00:20 +02:00
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
|
2020-05-26 02:05:47 +03:00
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
priority = 1;
|
|
|
|
|
tc = 1;
|
|
|
|
|
break;
|
|
|
|
|
case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
|
2016-11-25 10:33:42 +01:00
|
|
|
priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
|
|
|
|
|
tc = MLXSW_REG_HTGT_DEFAULT_TC;
|
2016-11-25 10:33:47 +01:00
|
|
|
policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
|
2016-11-25 10:33:42 +01:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
continue;
|
|
|
|
|
}
|
mlxsw: Create a different trap group list for each device
Trap groups can be used to control traps priority, both in terms of
which trap "wins" if a packet matches two traps (priority) and in terms
of packets from which trap group will be scheduled to the cpu first (tc).
They can also be used to set rate limiters (policers) on them (will be
added in the next patches).
Currently, we support two trap groups. In Spectrum we want a better
resolution, so every protocol / flow will have a different trap group,
so we can control its parameters separately. Once the policers will be
implemented, it will also allow us limit the rate of each protocol by
itself.
This patch change the trap group list to include:
* the emad trap group, which is shared for all the devices.
* Switchx2's trap groups, which are a copy of the current trap groups.
* Spectrum's new trap groups, in order to match the above guidelines.
(Switchib is using only the emad trap group, so it require no changes).
This patch also includes new configuration for Spectrum's trap groups,
with primary priority order within them.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-25 10:33:44 +01:00
|
|
|
|
2016-11-25 10:33:47 +01:00
|
|
|
if (max_cpu_policers <= policer_id &&
|
|
|
|
|
policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
|
2016-11-25 10:33:42 +01:00
|
|
|
err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:49 +03:00
|
|
|
static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
const struct mlxsw_listener listeners[],
|
|
|
|
|
size_t listeners_count)
|
2016-11-25 10:33:42 +01:00
|
|
|
{
|
2015-10-16 14:01:37 +02:00
|
|
|
int i;
|
|
|
|
|
int err;
|
|
|
|
|
|
2019-06-30 09:04:49 +03:00
|
|
|
for (i = 0; i < listeners_count; i++) {
|
2016-11-25 10:33:32 +01:00
|
|
|
err = mlxsw_core_trap_register(mlxsw_sp->core,
|
2019-06-30 09:04:49 +03:00
|
|
|
&listeners[i],
|
2016-11-25 10:33:32 +01:00
|
|
|
mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
if (err)
|
2016-11-25 10:33:35 +01:00
|
|
|
goto err_listener_register;
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
|
2016-11-25 10:33:35 +01:00
|
|
|
err_listener_register:
|
2015-10-16 14:01:37 +02:00
|
|
|
for (i--; i >= 0; i--) {
|
2016-11-25 10:33:32 +01:00
|
|
|
mlxsw_core_trap_unregister(mlxsw_sp->core,
|
2019-06-30 09:04:49 +03:00
|
|
|
&listeners[i],
|
2016-11-25 10:33:32 +01:00
|
|
|
mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:49 +03:00
|
|
|
static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
const struct mlxsw_listener listeners[],
|
|
|
|
|
size_t listeners_count)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
2019-06-30 09:04:49 +03:00
|
|
|
for (i = 0; i < listeners_count; i++) {
|
2016-11-25 10:33:32 +01:00
|
|
|
mlxsw_core_trap_unregister(mlxsw_sp->core,
|
2019-06-30 09:04:49 +03:00
|
|
|
&listeners[i],
|
2016-11-25 10:33:32 +01:00
|
|
|
mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:49 +03:00
|
|
|
static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
2020-03-30 22:38:26 +03:00
|
|
|
struct mlxsw_sp_trap *trap;
|
|
|
|
|
u64 max_policers;
|
2019-06-30 09:04:49 +03:00
|
|
|
int err;
|
|
|
|
|
|
2020-03-30 22:38:26 +03:00
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
|
|
|
|
|
return -EIO;
|
|
|
|
|
max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
|
|
|
|
|
trap = kzalloc(struct_size(trap, policers_usage,
|
|
|
|
|
BITS_TO_LONGS(max_policers)), GFP_KERNEL);
|
|
|
|
|
if (!trap)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
trap->max_policers = max_policers;
|
|
|
|
|
mlxsw_sp->trap = trap;
|
|
|
|
|
|
2019-06-30 09:04:49 +03:00
|
|
|
err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
|
|
|
|
|
if (err)
|
2020-03-30 22:38:26 +03:00
|
|
|
goto err_cpu_policers_set;
|
2019-06-30 09:04:49 +03:00
|
|
|
|
|
|
|
|
err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
|
|
|
|
|
if (err)
|
2020-03-30 22:38:26 +03:00
|
|
|
goto err_trap_groups_set;
|
2019-06-30 09:04:49 +03:00
|
|
|
|
2019-06-30 09:04:50 +03:00
|
|
|
err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
|
|
|
|
|
ARRAY_SIZE(mlxsw_sp_listener));
|
|
|
|
|
if (err)
|
2020-03-30 22:38:26 +03:00
|
|
|
goto err_traps_register;
|
2019-06-30 09:04:50 +03:00
|
|
|
|
|
|
|
|
err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
|
|
|
|
|
mlxsw_sp->listeners_count);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_extra_traps_init;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_extra_traps_init:
|
|
|
|
|
mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
|
|
|
|
|
ARRAY_SIZE(mlxsw_sp_listener));
|
2020-03-30 22:38:26 +03:00
|
|
|
err_traps_register:
|
|
|
|
|
err_trap_groups_set:
|
|
|
|
|
err_cpu_policers_set:
|
|
|
|
|
kfree(trap);
|
2019-06-30 09:04:50 +03:00
|
|
|
return err;
|
2019-06-30 09:04:49 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
2019-06-30 09:04:50 +03:00
|
|
|
mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
|
|
|
|
|
mlxsw_sp->listeners_count);
|
2019-06-30 09:04:49 +03:00
|
|
|
mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
|
|
|
|
|
ARRAY_SIZE(mlxsw_sp_listener));
|
2020-03-30 22:38:26 +03:00
|
|
|
kfree(mlxsw_sp->trap);
|
2019-06-30 09:04:49 +03:00
|
|
|
}
|
|
|
|
|
|
2019-06-11 10:19:40 +03:00
|
|
|
#define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
|
|
|
|
|
|
2015-12-03 12:12:28 +01:00
|
|
|
static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
char slcr_pl[MLXSW_REG_SLCR_LEN];
|
2018-10-11 07:47:57 +00:00
|
|
|
u32 seed;
|
2016-09-20 11:16:50 +02:00
|
|
|
int err;
|
2015-12-03 12:12:28 +01:00
|
|
|
|
2019-06-11 10:19:40 +03:00
|
|
|
seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
|
|
|
|
|
MLXSW_SP_LAG_SEED_INIT);
|
2015-12-03 12:12:28 +01:00
|
|
|
mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_DMAC |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_VLANID |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_SIP |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_DIP |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_SPORT |
|
|
|
|
|
MLXSW_REG_SLCR_LAG_HASH_DPORT |
|
2018-10-11 07:47:57 +00:00
|
|
|
MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
|
2016-09-20 11:16:50 +02:00
|
|
|
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2016-10-21 16:07:23 +02:00
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
|
|
|
|
|
!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
|
2016-09-20 11:16:50 +02:00
|
|
|
return -EIO;
|
|
|
|
|
|
2016-10-21 16:07:23 +02:00
|
|
|
mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
|
2016-09-20 11:16:50 +02:00
|
|
|
sizeof(struct mlxsw_sp_upper),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!mlxsw_sp->lags)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
|
|
|
|
|
{
|
|
|
|
|
kfree(mlxsw_sp->lags);
|
2015-12-03 12:12:28 +01:00
|
|
|
}
|
|
|
|
|
|
2016-11-25 10:33:40 +01:00
|
|
|
static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
|
|
|
|
char htgt_pl[MLXSW_REG_HTGT_LEN];
|
2020-09-15 11:40:58 +03:00
|
|
|
int err;
|
2016-11-25 10:33:40 +01:00
|
|
|
|
2016-11-25 10:33:42 +01:00
|
|
|
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
|
|
|
|
|
MLXSW_REG_HTGT_INVALID_POLICER,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_TC);
|
2020-09-15 11:40:58 +03:00
|
|
|
err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MFDE,
|
|
|
|
|
MLXSW_REG_HTGT_INVALID_POLICER,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_TC);
|
2020-09-27 10:50:11 +03:00
|
|
|
err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MTWE,
|
|
|
|
|
MLXSW_REG_HTGT_INVALID_POLICER,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_TC);
|
2020-09-27 10:50:14 +03:00
|
|
|
err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_PMPE,
|
|
|
|
|
MLXSW_REG_HTGT_INVALID_POLICER,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_PRIORITY,
|
|
|
|
|
MLXSW_REG_HTGT_DEFAULT_TC);
|
2016-11-25 10:33:40 +01:00
|
|
|
return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-11 18:45:11 +03:00
|
|
|
static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
|
|
|
|
|
.clock_init = mlxsw_sp1_ptp_clock_init,
|
|
|
|
|
.clock_fini = mlxsw_sp1_ptp_clock_fini,
|
2019-06-30 09:04:54 +03:00
|
|
|
.init = mlxsw_sp1_ptp_init,
|
|
|
|
|
.fini = mlxsw_sp1_ptp_fini,
|
mlxsw: spectrum: PTP: Hook into packet receive path
When configured, the Spectrum hardware can recognize PTP packets and
trap them to the CPU using dedicated traps, PTP0 and PTP1.
One reason to get PTP packets under dedicated traps is to have a
separate policer suitable for the amount of PTP traffic expected when
switch is operated as a boundary clock. For this, add two new trap
groups, MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0 and _PTP1, and associate the
two PTP traps with these two groups.
In the driver, specifically for Spectrum-1, event PTP packets will need
to be paired up with their timestamps. Those arrive through a different
set of traps, added later in the patch set. To support this future use,
introduce a new PTP op, ptp_receive.
It is possible to configure which PTP messages should be trapped under
which PTP trap. On Spectrum systems, we will use PTP0 for event
packets (which need timestamping), and PTP1 for control packets (which
do not). Thus configure PTP0 trap with a custom callback that defers to
the ptp_receive op.
Additionally, L2 PTP packets are actually trapped through the LLDP trap,
not through any of the PTP traps. So treat the LLDP trap the same way as
the PTP0 trap. Unlike PTP traps, which are currently still disabled,
LLDP trap is active. Correspondingly, have all the implementations of
the ptp_receive op return true, which the handler treats as a signal to
forward the packet immediately.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:51 +03:00
|
|
|
.receive = mlxsw_sp1_ptp_receive,
|
mlxsw: pci: PTP: Hook into packet transmit path
On Spectrum-1, timestamps are delivered separately from the packets, and
need to paired up. Therefore, at some point after mlxsw_sp_port_xmit()
is invoked, it is necessary to involve the chip-specific driver code to
allow it to do the necessary bookkeeping and matching.
On Spectrum-2, timestamps are delivered in CQE. For that reason,
position the point of driver involvement into mlxsw_pci_cqe_sdq_handle()
to make it hopefully easier to extend for Spectrum-2 in the future.
To tell the driver what port the packet was sent on, keep tx_info
in SKB control buffer.
Introduce a new driver core interface mlxsw_core_ptp_transmitted(), a
driver callback ptp_transmitted, and a PTP op transmitted. The callee is
responsible for taking care of releasing the SKB passed to the new
interfaces, and correspondingly have the new stub callbacks just call
dev_kfree_skb_any().
Follow-up patches will introduce the actual content into
mlxsw_sp1_ptp_transmitted() in particular.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:53 +03:00
|
|
|
.transmitted = mlxsw_sp1_ptp_transmitted,
|
2019-06-30 09:04:59 +03:00
|
|
|
.hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
|
|
|
|
|
.hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
|
2019-07-04 10:07:39 +03:00
|
|
|
.shaper_work = mlxsw_sp1_ptp_shaper_work,
|
2019-06-30 09:05:00 +03:00
|
|
|
.get_ts_info = mlxsw_sp1_ptp_get_ts_info,
|
mlxsw: spectrum_ptp: Add counters for GC events
On Spectrum-1, timestamped PTP packets and the corresponding timestamps need to
be kept in caches until both are available, at which point they are matched up
and packets forwarded as appropriate. However, not all packets will ever see
their timestamp, and not all timestamps will ever see their packet. It is
necessary to dispose of such abandoned entries, so a garbage collector was
introduced in commit 5d23e4159772 ("mlxsw: spectrum: PTP: Garbage-collect
unmatched entries").
If these GC events happen often, it is a sign of a problem. However because this
whole mechanism is taking place behind the scenes, there is no direct way to
determine whether garbage collection took place.
Therefore to fix this, on Spectrum-1 only, expose four artificial ethtool
counters for the GC events: GCd timestamps and packets, in TX and RX directions.
Cc: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28 18:54:37 +03:00
|
|
|
.get_stats_count = mlxsw_sp1_get_stats_count,
|
|
|
|
|
.get_stats_strings = mlxsw_sp1_get_stats_strings,
|
|
|
|
|
.get_stats = mlxsw_sp1_get_stats,
|
2019-06-11 18:45:11 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
|
|
|
|
|
.clock_init = mlxsw_sp2_ptp_clock_init,
|
|
|
|
|
.clock_fini = mlxsw_sp2_ptp_clock_fini,
|
2019-06-30 09:04:54 +03:00
|
|
|
.init = mlxsw_sp2_ptp_init,
|
|
|
|
|
.fini = mlxsw_sp2_ptp_fini,
|
mlxsw: spectrum: PTP: Hook into packet receive path
When configured, the Spectrum hardware can recognize PTP packets and
trap them to the CPU using dedicated traps, PTP0 and PTP1.
One reason to get PTP packets under dedicated traps is to have a
separate policer suitable for the amount of PTP traffic expected when
switch is operated as a boundary clock. For this, add two new trap
groups, MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0 and _PTP1, and associate the
two PTP traps with these two groups.
In the driver, specifically for Spectrum-1, event PTP packets will need
to be paired up with their timestamps. Those arrive through a different
set of traps, added later in the patch set. To support this future use,
introduce a new PTP op, ptp_receive.
It is possible to configure which PTP messages should be trapped under
which PTP trap. On Spectrum systems, we will use PTP0 for event
packets (which need timestamping), and PTP1 for control packets (which
do not). Thus configure PTP0 trap with a custom callback that defers to
the ptp_receive op.
Additionally, L2 PTP packets are actually trapped through the LLDP trap,
not through any of the PTP traps. So treat the LLDP trap the same way as
the PTP0 trap. Unlike PTP traps, which are currently still disabled,
LLDP trap is active. Correspondingly, have all the implementations of
the ptp_receive op return true, which the handler treats as a signal to
forward the packet immediately.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:51 +03:00
|
|
|
.receive = mlxsw_sp2_ptp_receive,
|
mlxsw: pci: PTP: Hook into packet transmit path
On Spectrum-1, timestamps are delivered separately from the packets, and
need to paired up. Therefore, at some point after mlxsw_sp_port_xmit()
is invoked, it is necessary to involve the chip-specific driver code to
allow it to do the necessary bookkeeping and matching.
On Spectrum-2, timestamps are delivered in CQE. For that reason,
position the point of driver involvement into mlxsw_pci_cqe_sdq_handle()
to make it hopefully easier to extend for Spectrum-2 in the future.
To tell the driver what port the packet was sent on, keep tx_info
in SKB control buffer.
Introduce a new driver core interface mlxsw_core_ptp_transmitted(), a
driver callback ptp_transmitted, and a PTP op transmitted. The callee is
responsible for taking care of releasing the SKB passed to the new
interfaces, and correspondingly have the new stub callbacks just call
dev_kfree_skb_any().
Follow-up patches will introduce the actual content into
mlxsw_sp1_ptp_transmitted() in particular.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:53 +03:00
|
|
|
.transmitted = mlxsw_sp2_ptp_transmitted,
|
2019-06-30 09:04:59 +03:00
|
|
|
.hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
|
|
|
|
|
.hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
|
2019-07-04 10:07:39 +03:00
|
|
|
.shaper_work = mlxsw_sp2_ptp_shaper_work,
|
2019-06-30 09:05:00 +03:00
|
|
|
.get_ts_info = mlxsw_sp2_ptp_get_ts_info,
|
mlxsw: spectrum_ptp: Add counters for GC events
On Spectrum-1, timestamped PTP packets and the corresponding timestamps need to
be kept in caches until both are available, at which point they are matched up
and packets forwarded as appropriate. However, not all packets will ever see
their timestamp, and not all timestamps will ever see their packet. It is
necessary to dispose of such abandoned entries, so a garbage collector was
introduced in commit 5d23e4159772 ("mlxsw: spectrum: PTP: Garbage-collect
unmatched entries").
If these GC events happen often, it is a sign of a problem. However because this
whole mechanism is taking place behind the scenes, there is no direct way to
determine whether garbage collection took place.
Therefore to fix this, on Spectrum-1 only, expose four artificial ethtool
counters for the GC events: GCd timestamps and packets, in TX and RX directions.
Cc: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-28 18:54:37 +03:00
|
|
|
.get_stats_count = mlxsw_sp2_get_stats_count,
|
|
|
|
|
.get_stats_strings = mlxsw_sp2_get_stats_strings,
|
|
|
|
|
.get_stats = mlxsw_sp2_get_stats,
|
2019-06-11 18:45:11 +03:00
|
|
|
};
|
|
|
|
|
|
2021-03-16 17:02:57 +02:00
|
|
|
struct mlxsw_sp_sample_trigger_node {
|
|
|
|
|
struct mlxsw_sp_sample_trigger trigger;
|
|
|
|
|
struct mlxsw_sp_sample_params params;
|
|
|
|
|
struct rhash_head ht_node;
|
|
|
|
|
struct rcu_head rcu;
|
|
|
|
|
refcount_t refcount;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = {
|
|
|
|
|
.key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger),
|
|
|
|
|
.head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node),
|
|
|
|
|
.key_len = sizeof(struct mlxsw_sp_sample_trigger),
|
|
|
|
|
.automatic_shrinking = true,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key,
|
|
|
|
|
const struct mlxsw_sp_sample_trigger *trigger)
|
|
|
|
|
{
|
|
|
|
|
memset(key, 0, sizeof(*key));
|
|
|
|
|
key->type = trigger->type;
|
|
|
|
|
key->local_port = trigger->local_port;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* RCU read lock must be held */
|
|
|
|
|
struct mlxsw_sp_sample_params *
|
|
|
|
|
mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
const struct mlxsw_sp_sample_trigger *trigger)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_sample_trigger_node *trigger_node;
|
|
|
|
|
struct mlxsw_sp_sample_trigger key;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_sample_trigger_key_init(&key, trigger);
|
|
|
|
|
trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key,
|
|
|
|
|
mlxsw_sp_sample_trigger_ht_params);
|
|
|
|
|
if (!trigger_node)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
return &trigger_node->params;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
const struct mlxsw_sp_sample_trigger *trigger,
|
|
|
|
|
const struct mlxsw_sp_sample_params *params)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_sample_trigger_node *trigger_node;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL);
|
|
|
|
|
if (!trigger_node)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
trigger_node->trigger = *trigger;
|
|
|
|
|
trigger_node->params = *params;
|
|
|
|
|
refcount_set(&trigger_node->refcount, 1);
|
|
|
|
|
|
|
|
|
|
err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht,
|
|
|
|
|
&trigger_node->ht_node,
|
|
|
|
|
mlxsw_sp_sample_trigger_ht_params);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_rhashtable_insert;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_rhashtable_insert:
|
|
|
|
|
kfree(trigger_node);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
struct mlxsw_sp_sample_trigger_node *trigger_node)
|
|
|
|
|
{
|
|
|
|
|
rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht,
|
|
|
|
|
&trigger_node->ht_node,
|
|
|
|
|
mlxsw_sp_sample_trigger_ht_params);
|
|
|
|
|
kfree_rcu(trigger_node, rcu);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
const struct mlxsw_sp_sample_trigger *trigger,
|
|
|
|
|
const struct mlxsw_sp_sample_params *params,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_sample_trigger_node *trigger_node;
|
|
|
|
|
struct mlxsw_sp_sample_trigger key;
|
|
|
|
|
|
|
|
|
|
ASSERT_RTNL();
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_sample_trigger_key_init(&key, trigger);
|
|
|
|
|
|
|
|
|
|
trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
|
|
|
|
|
&key,
|
|
|
|
|
mlxsw_sp_sample_trigger_ht_params);
|
|
|
|
|
if (!trigger_node)
|
|
|
|
|
return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key,
|
|
|
|
|
params);
|
|
|
|
|
|
2021-03-29 13:09:47 +03:00
|
|
|
if (trigger_node->trigger.local_port) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2021-03-16 17:02:57 +02:00
|
|
|
if (trigger_node->params.psample_group != params->psample_group ||
|
|
|
|
|
trigger_node->params.truncate != params->truncate ||
|
|
|
|
|
trigger_node->params.rate != params->rate ||
|
|
|
|
|
trigger_node->params.trunc_size != params->trunc_size) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
refcount_inc(&trigger_node->refcount);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
const struct mlxsw_sp_sample_trigger *trigger)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_sample_trigger_node *trigger_node;
|
|
|
|
|
struct mlxsw_sp_sample_trigger key;
|
|
|
|
|
|
|
|
|
|
ASSERT_RTNL();
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_sample_trigger_key_init(&key, trigger);
|
|
|
|
|
|
|
|
|
|
trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
|
|
|
|
|
&key,
|
|
|
|
|
mlxsw_sp_sample_trigger_ht_params);
|
|
|
|
|
if (!trigger_node)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (!refcount_dec_and_test(&trigger_node->refcount))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node);
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-16 16:26:35 +02:00
|
|
|
static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
|
|
|
|
|
unsigned long event, void *ptr);
|
|
|
|
|
|
2016-04-08 19:11:23 +02:00
|
|
|
static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
|
2019-10-03 11:49:34 +02:00
|
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
2016-04-08 19:11:23 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
2015-10-16 14:01:37 +02:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp->core = mlxsw_core;
|
|
|
|
|
mlxsw_sp->bus_info = mlxsw_bus_info;
|
|
|
|
|
|
2019-11-12 08:48:30 +02:00
|
|
|
mlxsw_core_emad_string_tlv_enable(mlxsw_core);
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_sp_base_mac_get(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-22 23:11:44 +02:00
|
|
|
err = mlxsw_sp_kvdl_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:39 +02:00
|
|
|
err = mlxsw_sp_fids_init(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
if (err) {
|
2017-05-26 08:37:39 +02:00
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
|
2017-10-22 23:11:44 +02:00
|
|
|
goto err_fids_init;
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2020-07-15 11:27:25 +03:00
|
|
|
err = mlxsw_sp_policers_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
|
|
|
|
|
goto err_policers_init;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:39 +02:00
|
|
|
err = mlxsw_sp_traps_init(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
if (err) {
|
2017-05-26 08:37:39 +02:00
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
|
|
|
|
|
goto err_traps_init;
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2019-08-21 10:19:35 +03:00
|
|
|
err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
|
|
|
|
|
goto err_devlink_traps_init;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_sp_buffers_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
|
|
|
|
|
goto err_buffers_init;
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-03 12:12:28 +01:00
|
|
|
err = mlxsw_sp_lag_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
|
|
|
|
|
goto err_lag_init;
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-29 10:56:11 +03:00
|
|
|
/* Initialize SPAN before router and switchdev, so that those components
|
|
|
|
|
* can call mlxsw_sp_span_respin().
|
|
|
|
|
*/
|
|
|
|
|
err = mlxsw_sp_span_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
|
|
|
|
|
goto err_span_init;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
err = mlxsw_sp_switchdev_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
|
|
|
|
|
goto err_switchdev_init;
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-19 10:00:08 +02:00
|
|
|
err = mlxsw_sp_counter_pool_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
|
|
|
|
|
goto err_counter_pool_init;
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-19 10:00:09 +02:00
|
|
|
err = mlxsw_sp_afa_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
|
|
|
|
|
goto err_afa_init;
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-17 08:53:14 +00:00
|
|
|
err = mlxsw_sp_nve_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
|
|
|
|
|
goto err_nve_init;
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-10 07:11:37 +00:00
|
|
|
err = mlxsw_sp_acl_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
|
|
|
|
|
goto err_acl_init;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-03 11:49:34 +02:00
|
|
|
err = mlxsw_sp_router_init(mlxsw_sp, extack);
|
2016-07-02 11:00:15 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
|
|
|
|
|
goto err_router_init;
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-11 18:45:11 +03:00
|
|
|
if (mlxsw_sp->bus_info->read_frc_capable) {
|
|
|
|
|
/* NULL is a valid return value from clock_init */
|
|
|
|
|
mlxsw_sp->clock =
|
|
|
|
|
mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
|
|
|
|
|
mlxsw_sp->bus_info->dev);
|
|
|
|
|
if (IS_ERR(mlxsw_sp->clock)) {
|
|
|
|
|
err = PTR_ERR(mlxsw_sp->clock);
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
|
|
|
|
|
goto err_ptp_clock_init;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-30 09:04:54 +03:00
|
|
|
if (mlxsw_sp->clock) {
|
|
|
|
|
/* NULL is a valid return value from ptp_ops->init */
|
|
|
|
|
mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
|
|
|
|
|
if (IS_ERR(mlxsw_sp->ptp_state)) {
|
|
|
|
|
err = PTR_ERR(mlxsw_sp->ptp_state);
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
|
|
|
|
|
goto err_ptp_init;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-27 14:53:46 +01:00
|
|
|
/* Initialize netdevice notifier after router and SPAN is initialized,
|
|
|
|
|
* so that the event handler can use router structures and call SPAN
|
|
|
|
|
* respin.
|
2017-10-16 16:26:35 +02:00
|
|
|
*/
|
|
|
|
|
mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
|
2019-10-03 11:49:32 +02:00
|
|
|
err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
|
2019-09-30 10:15:11 +02:00
|
|
|
&mlxsw_sp->netdevice_nb);
|
2017-10-16 16:26:35 +02:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
|
|
|
|
|
goto err_netdev_notifier;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-28 17:24:12 +02:00
|
|
|
err = mlxsw_sp_dpipe_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
|
|
|
|
|
goto err_dpipe_init;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-31 11:42:11 +02:00
|
|
|
err = mlxsw_sp_port_module_info_init(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
|
|
|
|
|
goto err_port_module_info_init;
|
|
|
|
|
}
|
|
|
|
|
|
2021-03-16 17:02:57 +02:00
|
|
|
err = rhashtable_init(&mlxsw_sp->sample_trigger_ht,
|
|
|
|
|
&mlxsw_sp_sample_trigger_ht_params);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n");
|
|
|
|
|
goto err_sample_trigger_init;
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-02 11:00:14 +02:00
|
|
|
err = mlxsw_sp_ports_create(mlxsw_sp);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
|
|
|
|
|
goto err_ports_create;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
return 0;
|
|
|
|
|
|
2016-07-02 11:00:14 +02:00
|
|
|
err_ports_create:
|
2021-03-16 17:02:57 +02:00
|
|
|
rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
|
|
|
|
|
err_sample_trigger_init:
|
2019-10-31 11:42:11 +02:00
|
|
|
mlxsw_sp_port_module_info_fini(mlxsw_sp);
|
|
|
|
|
err_port_module_info_init:
|
2017-03-28 17:24:12 +02:00
|
|
|
mlxsw_sp_dpipe_fini(mlxsw_sp);
|
|
|
|
|
err_dpipe_init:
|
2019-10-03 11:49:32 +02:00
|
|
|
unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
|
2019-09-30 10:15:11 +02:00
|
|
|
&mlxsw_sp->netdevice_nb);
|
2017-10-16 16:26:35 +02:00
|
|
|
err_netdev_notifier:
|
2019-06-30 09:04:54 +03:00
|
|
|
if (mlxsw_sp->clock)
|
|
|
|
|
mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
|
|
|
|
|
err_ptp_init:
|
2019-06-11 18:45:11 +03:00
|
|
|
if (mlxsw_sp->clock)
|
|
|
|
|
mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
|
|
|
|
|
err_ptp_clock_init:
|
2016-07-02 11:00:15 +02:00
|
|
|
mlxsw_sp_router_fini(mlxsw_sp);
|
|
|
|
|
err_router_init:
|
2018-12-10 07:11:37 +00:00
|
|
|
mlxsw_sp_acl_fini(mlxsw_sp);
|
|
|
|
|
err_acl_init:
|
2018-10-17 08:53:14 +00:00
|
|
|
mlxsw_sp_nve_fini(mlxsw_sp);
|
|
|
|
|
err_nve_init:
|
2017-09-19 10:00:09 +02:00
|
|
|
mlxsw_sp_afa_fini(mlxsw_sp);
|
|
|
|
|
err_afa_init:
|
2017-09-19 10:00:08 +02:00
|
|
|
mlxsw_sp_counter_pool_fini(mlxsw_sp);
|
|
|
|
|
err_counter_pool_init:
|
2016-07-02 11:00:14 +02:00
|
|
|
mlxsw_sp_switchdev_fini(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
err_switchdev_init:
|
2018-04-29 10:56:11 +03:00
|
|
|
mlxsw_sp_span_fini(mlxsw_sp);
|
|
|
|
|
err_span_init:
|
2016-09-20 11:16:50 +02:00
|
|
|
mlxsw_sp_lag_fini(mlxsw_sp);
|
2015-12-03 12:12:28 +01:00
|
|
|
err_lag_init:
|
2016-04-14 18:19:24 +02:00
|
|
|
mlxsw_sp_buffers_fini(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
err_buffers_init:
|
2019-08-21 10:19:35 +03:00
|
|
|
mlxsw_sp_devlink_traps_fini(mlxsw_sp);
|
|
|
|
|
err_devlink_traps_init:
|
2015-10-16 14:01:37 +02:00
|
|
|
mlxsw_sp_traps_fini(mlxsw_sp);
|
2017-05-26 08:37:39 +02:00
|
|
|
err_traps_init:
|
2020-07-15 11:27:25 +03:00
|
|
|
mlxsw_sp_policers_fini(mlxsw_sp);
|
|
|
|
|
err_policers_init:
|
2017-05-26 08:37:39 +02:00
|
|
|
mlxsw_sp_fids_fini(mlxsw_sp);
|
2017-10-22 23:11:44 +02:00
|
|
|
err_fids_init:
|
|
|
|
|
mlxsw_sp_kvdl_fini(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
|
2019-10-03 11:49:34 +02:00
|
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2018-07-18 11:14:45 +03:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
|
|
2021-03-17 12:35:26 +02:00
|
|
|
mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops;
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
|
|
|
|
|
mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
|
|
|
|
|
mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
|
|
|
|
|
mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
|
2020-06-21 11:34:33 +03:00
|
|
|
mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
|
2018-10-17 08:53:14 +00:00
|
|
|
mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
|
2018-12-13 11:54:50 +00:00
|
|
|
mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
|
2019-02-20 19:32:12 +00:00
|
|
|
mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
|
2020-09-16 09:35:27 +03:00
|
|
|
mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
|
2019-02-22 13:56:40 +00:00
|
|
|
mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
|
2019-06-11 18:45:11 +03:00
|
|
|
mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
|
2020-01-20 09:52:52 +02:00
|
|
|
mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
|
2020-07-15 11:27:25 +03:00
|
|
|
mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
|
2020-08-03 19:11:37 +03:00
|
|
|
mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
|
2021-03-11 14:24:14 +02:00
|
|
|
mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops;
|
2021-03-22 17:58:53 +02:00
|
|
|
mlxsw_sp->router_ops = &mlxsw_sp1_router_ops;
|
2019-06-30 09:04:50 +03:00
|
|
|
mlxsw_sp->listeners = mlxsw_sp1_listener;
|
|
|
|
|
mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
|
2020-01-24 15:23:12 +02:00
|
|
|
mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
|
2018-07-18 11:14:45 +03:00
|
|
|
|
2019-10-03 11:49:34 +02:00
|
|
|
return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
|
2018-07-18 11:14:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
|
2019-10-03 11:49:34 +02:00
|
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2018-07-18 11:14:45 +03:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
|
|
2021-03-17 12:35:26 +02:00
|
|
|
mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
|
|
|
|
|
mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
|
|
|
|
|
mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
|
|
|
|
|
mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
|
2020-06-21 11:34:33 +03:00
|
|
|
mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
|
2018-10-17 08:53:14 +00:00
|
|
|
mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
|
2018-12-13 11:54:50 +00:00
|
|
|
mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
|
2019-02-20 19:32:12 +00:00
|
|
|
mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
|
2020-09-16 09:35:27 +03:00
|
|
|
mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
|
2019-02-22 13:56:45 +00:00
|
|
|
mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
|
2019-06-11 18:45:11 +03:00
|
|
|
mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
|
2020-01-20 09:52:52 +02:00
|
|
|
mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
|
2020-07-15 11:27:25 +03:00
|
|
|
mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
|
2020-08-03 19:11:37 +03:00
|
|
|
mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
|
2021-03-11 14:24:14 +02:00
|
|
|
mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
|
2021-03-22 17:58:53 +02:00
|
|
|
mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
|
2020-01-24 15:23:12 +02:00
|
|
|
mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
|
2018-07-18 11:14:45 +03:00
|
|
|
|
2019-10-03 11:49:34 +02:00
|
|
|
return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
|
2018-07-18 11:14:45 +03:00
|
|
|
}
|
|
|
|
|
|
2020-01-15 13:53:44 +02:00
|
|
|
static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
|
|
|
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
|
|
2021-03-17 12:35:26 +02:00
|
|
|
mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
|
2020-01-15 13:53:44 +02:00
|
|
|
mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
|
|
|
|
|
mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
|
|
|
|
|
mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
|
|
|
|
|
mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
|
2020-06-21 11:34:33 +03:00
|
|
|
mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
|
2020-01-15 13:53:44 +02:00
|
|
|
mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
|
|
|
|
|
mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
|
|
|
|
|
mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
|
|
|
|
|
mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
|
2020-09-16 09:35:27 +03:00
|
|
|
mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
|
2020-01-15 13:53:44 +02:00
|
|
|
mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
|
|
|
|
|
mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
|
2020-02-26 09:39:20 +01:00
|
|
|
mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
|
2020-07-15 11:27:25 +03:00
|
|
|
mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
|
2020-08-03 19:11:37 +03:00
|
|
|
mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
|
2021-03-11 14:24:14 +02:00
|
|
|
mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
|
2021-03-22 17:58:53 +02:00
|
|
|
mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
|
2020-01-24 15:23:12 +02:00
|
|
|
mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
|
2020-01-15 13:53:44 +02:00
|
|
|
|
|
|
|
|
return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-08 19:11:23 +02:00
|
|
|
static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
2016-04-08 19:11:23 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
2015-10-16 14:01:37 +02:00
|
|
|
|
2016-07-02 11:00:14 +02:00
|
|
|
mlxsw_sp_ports_remove(mlxsw_sp);
|
2021-03-16 17:02:57 +02:00
|
|
|
rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
|
2019-10-31 11:42:11 +02:00
|
|
|
mlxsw_sp_port_module_info_fini(mlxsw_sp);
|
2017-03-28 17:24:12 +02:00
|
|
|
mlxsw_sp_dpipe_fini(mlxsw_sp);
|
2019-10-03 11:49:32 +02:00
|
|
|
unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
|
2019-09-30 10:15:11 +02:00
|
|
|
&mlxsw_sp->netdevice_nb);
|
2019-06-30 09:04:54 +03:00
|
|
|
if (mlxsw_sp->clock) {
|
|
|
|
|
mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
|
2019-06-11 18:45:11 +03:00
|
|
|
mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
|
2019-06-30 09:04:54 +03:00
|
|
|
}
|
2016-07-02 11:00:15 +02:00
|
|
|
mlxsw_sp_router_fini(mlxsw_sp);
|
2018-12-10 07:11:37 +00:00
|
|
|
mlxsw_sp_acl_fini(mlxsw_sp);
|
2018-10-17 08:53:14 +00:00
|
|
|
mlxsw_sp_nve_fini(mlxsw_sp);
|
2017-09-19 10:00:09 +02:00
|
|
|
mlxsw_sp_afa_fini(mlxsw_sp);
|
2017-09-19 10:00:08 +02:00
|
|
|
mlxsw_sp_counter_pool_fini(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
mlxsw_sp_switchdev_fini(mlxsw_sp);
|
2018-04-29 10:56:11 +03:00
|
|
|
mlxsw_sp_span_fini(mlxsw_sp);
|
2016-09-20 11:16:50 +02:00
|
|
|
mlxsw_sp_lag_fini(mlxsw_sp);
|
2016-05-06 22:20:59 +02:00
|
|
|
mlxsw_sp_buffers_fini(mlxsw_sp);
|
2019-08-21 10:19:35 +03:00
|
|
|
mlxsw_sp_devlink_traps_fini(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
mlxsw_sp_traps_fini(mlxsw_sp);
|
2020-07-15 11:27:25 +03:00
|
|
|
mlxsw_sp_policers_fini(mlxsw_sp);
|
2017-05-26 08:37:39 +02:00
|
|
|
mlxsw_sp_fids_fini(mlxsw_sp);
|
2017-10-22 23:11:44 +02:00
|
|
|
mlxsw_sp_kvdl_fini(mlxsw_sp);
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2018-11-25 09:43:59 +00:00
|
|
|
/* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
|
|
|
|
|
* 802.1Q FIDs
|
|
|
|
|
*/
|
|
|
|
|
#define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \
|
|
|
|
|
VLAN_VID_MASK - 1)
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
|
2015-10-16 14:01:37 +02:00
|
|
|
.used_max_mid = 1,
|
2016-01-10 21:06:26 +01:00
|
|
|
.max_mid = MLXSW_SP_MID_MAX,
|
2015-10-16 14:01:37 +02:00
|
|
|
.used_flood_tables = 1,
|
|
|
|
|
.used_flood_mode = 1,
|
|
|
|
|
.flood_mode = 3,
|
2017-02-09 14:54:46 +01:00
|
|
|
.max_fid_flood_tables = 3,
|
2018-11-25 09:43:59 +00:00
|
|
|
.fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
|
2015-10-16 14:01:37 +02:00
|
|
|
.used_max_ib_mc = 1,
|
|
|
|
|
.max_ib_mc = 0,
|
|
|
|
|
.used_max_pkey = 1,
|
|
|
|
|
.max_pkey = 0,
|
2018-04-01 17:34:56 +03:00
|
|
|
.used_kvd_sizes = 1,
|
2017-10-22 23:11:49 +02:00
|
|
|
.kvd_hash_single_parts = 59,
|
|
|
|
|
.kvd_hash_double_parts = 41,
|
2016-07-05 11:27:46 +02:00
|
|
|
.kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
|
2015-10-16 14:01:37 +02:00
|
|
|
.swid_config = {
|
|
|
|
|
{
|
|
|
|
|
.used_type = 1,
|
|
|
|
|
.type = MLXSW_PORT_SWID_TYPE_ETH,
|
|
|
|
|
}
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
|
|
|
|
|
.used_max_mid = 1,
|
|
|
|
|
.max_mid = MLXSW_SP_MID_MAX,
|
|
|
|
|
.used_flood_tables = 1,
|
|
|
|
|
.used_flood_mode = 1,
|
|
|
|
|
.flood_mode = 3,
|
|
|
|
|
.max_fid_flood_tables = 3,
|
2018-11-25 09:43:59 +00:00
|
|
|
.fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
|
2018-07-18 11:14:45 +03:00
|
|
|
.used_max_ib_mc = 1,
|
|
|
|
|
.max_ib_mc = 0,
|
|
|
|
|
.used_max_pkey = 1,
|
|
|
|
|
.max_pkey = 0,
|
2020-12-14 13:30:40 +02:00
|
|
|
.used_kvh_xlt_cache_mode = 1,
|
|
|
|
|
.kvh_xlt_cache_mode = 1,
|
2018-07-18 11:14:45 +03:00
|
|
|
.swid_config = {
|
|
|
|
|
{
|
|
|
|
|
.used_type = 1,
|
|
|
|
|
.type = MLXSW_PORT_SWID_TYPE_ETH,
|
|
|
|
|
}
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2018-01-15 08:59:07 +01:00
|
|
|
static void
|
2018-02-28 13:12:09 +01:00
|
|
|
mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
|
|
|
|
|
struct devlink_resource_size_params *kvd_size_params,
|
|
|
|
|
struct devlink_resource_size_params *linear_size_params,
|
|
|
|
|
struct devlink_resource_size_params *hash_double_size_params,
|
|
|
|
|
struct devlink_resource_size_params *hash_single_size_params)
|
2018-01-15 08:59:07 +01:00
|
|
|
{
|
|
|
|
|
u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
|
|
|
|
|
KVD_SINGLE_MIN_SIZE);
|
|
|
|
|
u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
|
|
|
|
|
KVD_DOUBLE_MIN_SIZE);
|
|
|
|
|
u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
|
|
|
|
|
u32 linear_size_min = 0;
|
|
|
|
|
|
2018-02-28 13:12:09 +01:00
|
|
|
devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
|
|
|
|
|
MLXSW_SP_KVD_GRANULARITY,
|
|
|
|
|
DEVLINK_RESOURCE_UNIT_ENTRY);
|
|
|
|
|
devlink_resource_size_params_init(linear_size_params, linear_size_min,
|
|
|
|
|
kvd_size - single_size_min -
|
|
|
|
|
double_size_min,
|
|
|
|
|
MLXSW_SP_KVD_GRANULARITY,
|
|
|
|
|
DEVLINK_RESOURCE_UNIT_ENTRY);
|
|
|
|
|
devlink_resource_size_params_init(hash_double_size_params,
|
|
|
|
|
double_size_min,
|
|
|
|
|
kvd_size - single_size_min -
|
|
|
|
|
linear_size_min,
|
|
|
|
|
MLXSW_SP_KVD_GRANULARITY,
|
|
|
|
|
DEVLINK_RESOURCE_UNIT_ENTRY);
|
|
|
|
|
devlink_resource_size_params_init(hash_single_size_params,
|
|
|
|
|
single_size_min,
|
|
|
|
|
kvd_size - double_size_min -
|
|
|
|
|
linear_size_min,
|
|
|
|
|
MLXSW_SP_KVD_GRANULARITY,
|
|
|
|
|
DEVLINK_RESOURCE_UNIT_ENTRY);
|
2018-01-15 08:59:07 +01:00
|
|
|
}
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
|
2018-01-15 08:59:07 +01:00
|
|
|
{
|
|
|
|
|
struct devlink *devlink = priv_to_devlink(mlxsw_core);
|
2018-02-28 13:12:09 +01:00
|
|
|
struct devlink_resource_size_params hash_single_size_params;
|
|
|
|
|
struct devlink_resource_size_params hash_double_size_params;
|
|
|
|
|
struct devlink_resource_size_params linear_size_params;
|
|
|
|
|
struct devlink_resource_size_params kvd_size_params;
|
2018-01-15 08:59:07 +01:00
|
|
|
u32 kvd_size, single_size, double_size, linear_size;
|
|
|
|
|
const struct mlxsw_config_profile *profile;
|
|
|
|
|
int err;
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
profile = &mlxsw_sp1_config_profile;
|
2018-01-15 08:59:07 +01:00
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
2018-02-28 13:12:09 +01:00
|
|
|
mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
|
|
|
|
|
&linear_size_params,
|
|
|
|
|
&hash_double_size_params,
|
|
|
|
|
&hash_single_size_params);
|
|
|
|
|
|
2018-01-15 08:59:07 +01:00
|
|
|
kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
|
|
|
|
|
err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
|
2018-03-20 19:31:14 -07:00
|
|
|
kvd_size, MLXSW_SP_RESOURCE_KVD,
|
2018-01-15 08:59:07 +01:00
|
|
|
DEVLINK_RESOURCE_ID_PARENT_TOP,
|
2018-04-05 22:13:21 +02:00
|
|
|
&kvd_size_params);
|
2018-01-15 08:59:07 +01:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
linear_size = profile->kvd_linear_size;
|
|
|
|
|
err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
|
2018-03-20 19:31:14 -07:00
|
|
|
linear_size,
|
2018-01-15 08:59:07 +01:00
|
|
|
MLXSW_SP_RESOURCE_KVD_LINEAR,
|
|
|
|
|
MLXSW_SP_RESOURCE_KVD,
|
2018-04-05 22:13:21 +02:00
|
|
|
&linear_size_params);
|
2018-01-15 08:59:07 +01:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2018-07-08 23:51:16 +03:00
|
|
|
err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
|
2018-02-20 08:44:22 +01:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2018-01-15 08:59:07 +01:00
|
|
|
double_size = kvd_size - linear_size;
|
|
|
|
|
double_size *= profile->kvd_hash_double_parts;
|
|
|
|
|
double_size /= profile->kvd_hash_double_parts +
|
|
|
|
|
profile->kvd_hash_single_parts;
|
2018-04-01 17:34:54 +03:00
|
|
|
double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
|
2018-01-15 08:59:07 +01:00
|
|
|
err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
|
2018-03-20 19:31:14 -07:00
|
|
|
double_size,
|
2018-01-15 08:59:07 +01:00
|
|
|
MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
|
|
|
|
|
MLXSW_SP_RESOURCE_KVD,
|
2018-04-05 22:13:21 +02:00
|
|
|
&hash_double_size_params);
|
2018-01-15 08:59:07 +01:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
single_size = kvd_size - double_size - linear_size;
|
|
|
|
|
err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
|
2018-03-20 19:31:14 -07:00
|
|
|
single_size,
|
2018-01-15 08:59:07 +01:00
|
|
|
MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
|
|
|
|
|
MLXSW_SP_RESOURCE_KVD,
|
2018-04-05 22:13:21 +02:00
|
|
|
&hash_single_size_params);
|
2018-01-15 08:59:07 +01:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-23 10:57:41 +03:00
|
|
|
static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
|
|
|
|
struct devlink *devlink = priv_to_devlink(mlxsw_core);
|
|
|
|
|
struct devlink_resource_size_params kvd_size_params;
|
|
|
|
|
u32 kvd_size;
|
|
|
|
|
|
|
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
|
|
|
|
|
devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
|
|
|
|
|
MLXSW_SP_KVD_GRANULARITY,
|
|
|
|
|
DEVLINK_RESOURCE_UNIT_ENTRY);
|
|
|
|
|
|
|
|
|
|
return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
|
|
|
|
|
kvd_size, MLXSW_SP_RESOURCE_KVD,
|
|
|
|
|
DEVLINK_RESOURCE_ID_PARENT_TOP,
|
|
|
|
|
&kvd_size_params);
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-17 09:55:14 +03:00
|
|
|
static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
|
|
|
|
struct devlink *devlink = priv_to_devlink(mlxsw_core);
|
|
|
|
|
struct devlink_resource_size_params span_size_params;
|
|
|
|
|
u32 max_span;
|
|
|
|
|
|
|
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
|
|
|
|
|
devlink_resource_size_params_init(&span_size_params, max_span, max_span,
|
|
|
|
|
1, DEVLINK_RESOURCE_UNIT_ENTRY);
|
|
|
|
|
|
|
|
|
|
return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
|
|
|
|
|
max_span, MLXSW_SP_RESOURCE_SPAN,
|
|
|
|
|
DEVLINK_RESOURCE_ID_PARENT_TOP,
|
|
|
|
|
&span_size_params);
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
2019-10-17 09:55:14 +03:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_resources_span_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_resources_span_register;
|
|
|
|
|
|
2020-03-18 15:48:53 +02:00
|
|
|
err = mlxsw_sp_counter_resources_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_resources_counter_register;
|
|
|
|
|
|
2020-07-15 11:27:26 +03:00
|
|
|
err = mlxsw_sp_policer_resources_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_resources_counter_register;
|
|
|
|
|
|
2019-10-17 09:55:14 +03:00
|
|
|
return 0;
|
|
|
|
|
|
2020-03-18 15:48:53 +02:00
|
|
|
err_resources_counter_register:
|
2019-10-17 09:55:14 +03:00
|
|
|
err_resources_span_register:
|
|
|
|
|
devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL);
|
|
|
|
|
return err;
|
2018-07-18 11:14:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
2019-10-17 09:55:14 +03:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_resources_span_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_resources_span_register;
|
|
|
|
|
|
2020-03-18 15:48:53 +02:00
|
|
|
err = mlxsw_sp_counter_resources_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_resources_counter_register;
|
|
|
|
|
|
2020-07-15 11:27:26 +03:00
|
|
|
err = mlxsw_sp_policer_resources_register(mlxsw_core);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_resources_counter_register;
|
|
|
|
|
|
2019-10-17 09:55:14 +03:00
|
|
|
return 0;
|
|
|
|
|
|
2020-03-18 15:48:53 +02:00
|
|
|
err_resources_counter_register:
|
2019-10-17 09:55:14 +03:00
|
|
|
err_resources_span_register:
|
|
|
|
|
devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL);
|
|
|
|
|
return err;
|
2018-07-18 11:14:45 +03:00
|
|
|
}
|
|
|
|
|
|
2018-01-15 08:59:10 +01:00
|
|
|
static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
|
|
|
|
|
const struct mlxsw_config_profile *profile,
|
|
|
|
|
u64 *p_single_size, u64 *p_double_size,
|
|
|
|
|
u64 *p_linear_size)
|
|
|
|
|
{
|
|
|
|
|
struct devlink *devlink = priv_to_devlink(mlxsw_core);
|
|
|
|
|
u32 double_size;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
|
2018-04-01 17:34:56 +03:00
|
|
|
!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
|
2018-01-15 08:59:10 +01:00
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
/* The hash part is what left of the kvd without the
|
|
|
|
|
* linear part. It is split to the single size and
|
|
|
|
|
* double size by the parts ratio from the profile.
|
|
|
|
|
* Both sizes must be a multiplications of the
|
|
|
|
|
* granularity from the profile. In case the user
|
|
|
|
|
* provided the sizes they are obtained via devlink.
|
|
|
|
|
*/
|
|
|
|
|
err = devlink_resource_size_get(devlink,
|
|
|
|
|
MLXSW_SP_RESOURCE_KVD_LINEAR,
|
|
|
|
|
p_linear_size);
|
|
|
|
|
if (err)
|
|
|
|
|
*p_linear_size = profile->kvd_linear_size;
|
|
|
|
|
|
|
|
|
|
err = devlink_resource_size_get(devlink,
|
|
|
|
|
MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
|
|
|
|
|
p_double_size);
|
|
|
|
|
if (err) {
|
|
|
|
|
double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
|
|
|
|
|
*p_linear_size;
|
|
|
|
|
double_size *= profile->kvd_hash_double_parts;
|
|
|
|
|
double_size /= profile->kvd_hash_double_parts +
|
|
|
|
|
profile->kvd_hash_single_parts;
|
|
|
|
|
*p_double_size = rounddown(double_size,
|
2018-04-01 17:34:54 +03:00
|
|
|
MLXSW_SP_KVD_GRANULARITY);
|
2018-01-15 08:59:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = devlink_resource_size_get(devlink,
|
|
|
|
|
MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
|
|
|
|
|
p_single_size);
|
|
|
|
|
if (err)
|
|
|
|
|
*p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
|
|
|
|
|
*p_double_size - *p_linear_size;
|
|
|
|
|
|
|
|
|
|
/* Check results are legal. */
|
|
|
|
|
if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
|
|
|
|
|
*p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
|
|
|
|
|
MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-07 11:22:55 +00:00
|
|
|
static int
|
|
|
|
|
mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
|
|
|
|
|
struct devlink_param_gset_ctx *ctx)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
|
|
|
|
|
|
ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
|
|
|
|
|
struct devlink_param_gset_ctx *ctx)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
|
|
|
|
|
|
return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct devlink_param mlxsw_sp2_devlink_params[] = {
|
|
|
|
|
DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
|
|
|
|
|
"acl_region_rehash_interval",
|
|
|
|
|
DEVLINK_PARAM_TYPE_U32,
|
|
|
|
|
BIT(DEVLINK_PARAM_CMODE_RUNTIME),
|
|
|
|
|
mlxsw_sp_params_acl_region_rehash_intrvl_get,
|
|
|
|
|
mlxsw_sp_params_acl_region_rehash_intrvl_set,
|
|
|
|
|
NULL),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
|
|
|
|
struct devlink *devlink = priv_to_devlink(mlxsw_core);
|
|
|
|
|
union devlink_param_value value;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
|
|
|
|
|
ARRAY_SIZE(mlxsw_sp2_devlink_params));
|
|
|
|
|
if (err)
|
2020-09-15 11:40:54 +03:00
|
|
|
return err;
|
2019-02-07 11:22:55 +00:00
|
|
|
|
|
|
|
|
value.vu32 = 0;
|
|
|
|
|
devlink_param_driverinit_value_set(devlink,
|
|
|
|
|
MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
|
|
|
|
|
value);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
|
|
|
|
|
{
|
|
|
|
|
devlink_params_unregister(priv_to_devlink(mlxsw_core),
|
|
|
|
|
mlxsw_sp2_devlink_params,
|
|
|
|
|
ARRAY_SIZE(mlxsw_sp2_devlink_params));
|
|
|
|
|
}
|
|
|
|
|
|
mlxsw: pci: PTP: Hook into packet transmit path
On Spectrum-1, timestamps are delivered separately from the packets, and
need to paired up. Therefore, at some point after mlxsw_sp_port_xmit()
is invoked, it is necessary to involve the chip-specific driver code to
allow it to do the necessary bookkeeping and matching.
On Spectrum-2, timestamps are delivered in CQE. For that reason,
position the point of driver involvement into mlxsw_pci_cqe_sdq_handle()
to make it hopefully easier to extend for Spectrum-2 in the future.
To tell the driver what port the packet was sent on, keep tx_info
in SKB control buffer.
Introduce a new driver core interface mlxsw_core_ptp_transmitted(), a
driver callback ptp_transmitted, and a PTP op transmitted. The callee is
responsible for taking care of releasing the SKB passed to the new
interfaces, and correspondingly have the new stub callbacks just call
dev_kfree_skb_any().
Follow-up patches will introduce the actual content into
mlxsw_sp1_ptp_transmitted() in particular.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:53 +03:00
|
|
|
static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
|
|
|
|
|
struct sk_buff *skb, u8 local_port)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
|
|
|
|
|
|
|
|
|
|
skb_pull(skb, MLXSW_TXHDR_LEN);
|
|
|
|
|
mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static struct mlxsw_driver mlxsw_sp1_driver = {
|
|
|
|
|
.kind = mlxsw_sp1_driver_name,
|
2016-04-14 18:19:30 +02:00
|
|
|
.priv_size = sizeof(struct mlxsw_sp),
|
2020-09-15 11:40:52 +03:00
|
|
|
.fw_req_rev = &mlxsw_sp1_fw_rev,
|
|
|
|
|
.fw_filename = MLXSW_SP1_FW_FILENAME,
|
2018-07-18 11:14:45 +03:00
|
|
|
.init = mlxsw_sp1_init,
|
2016-04-14 18:19:30 +02:00
|
|
|
.fini = mlxsw_sp_fini,
|
2016-11-25 10:33:40 +01:00
|
|
|
.basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
|
2016-04-14 18:19:30 +02:00
|
|
|
.port_split = mlxsw_sp_port_split,
|
|
|
|
|
.port_unsplit = mlxsw_sp_port_unsplit,
|
|
|
|
|
.sb_pool_get = mlxsw_sp_sb_pool_get,
|
|
|
|
|
.sb_pool_set = mlxsw_sp_sb_pool_set,
|
|
|
|
|
.sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
|
|
|
|
|
.sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
|
|
|
|
|
.sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
|
|
|
|
|
.sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
|
|
|
|
|
.sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
|
|
|
|
|
.sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
|
|
|
|
|
.sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
|
|
|
|
|
.sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
|
2019-08-21 10:19:35 +03:00
|
|
|
.trap_init = mlxsw_sp_trap_init,
|
|
|
|
|
.trap_fini = mlxsw_sp_trap_fini,
|
|
|
|
|
.trap_action_set = mlxsw_sp_trap_action_set,
|
|
|
|
|
.trap_group_init = mlxsw_sp_trap_group_init,
|
2020-03-30 22:38:31 +03:00
|
|
|
.trap_group_set = mlxsw_sp_trap_group_set,
|
2020-03-30 22:38:28 +03:00
|
|
|
.trap_policer_init = mlxsw_sp_trap_policer_init,
|
|
|
|
|
.trap_policer_fini = mlxsw_sp_trap_policer_fini,
|
|
|
|
|
.trap_policer_set = mlxsw_sp_trap_policer_set,
|
|
|
|
|
.trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
|
2016-04-14 18:19:30 +02:00
|
|
|
.txhdr_construct = mlxsw_sp_txhdr_construct,
|
2018-07-18 11:14:45 +03:00
|
|
|
.resources_register = mlxsw_sp1_resources_register,
|
2018-01-15 08:59:10 +01:00
|
|
|
.kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
|
mlxsw: pci: PTP: Hook into packet transmit path
On Spectrum-1, timestamps are delivered separately from the packets, and
need to paired up. Therefore, at some point after mlxsw_sp_port_xmit()
is invoked, it is necessary to involve the chip-specific driver code to
allow it to do the necessary bookkeeping and matching.
On Spectrum-2, timestamps are delivered in CQE. For that reason,
position the point of driver involvement into mlxsw_pci_cqe_sdq_handle()
to make it hopefully easier to extend for Spectrum-2 in the future.
To tell the driver what port the packet was sent on, keep tx_info
in SKB control buffer.
Introduce a new driver core interface mlxsw_core_ptp_transmitted(), a
driver callback ptp_transmitted, and a PTP op transmitted. The callee is
responsible for taking care of releasing the SKB passed to the new
interfaces, and correspondingly have the new stub callbacks just call
dev_kfree_skb_any().
Follow-up patches will introduce the actual content into
mlxsw_sp1_ptp_transmitted() in particular.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:53 +03:00
|
|
|
.ptp_transmitted = mlxsw_sp_ptp_transmitted,
|
2016-04-14 18:19:30 +02:00
|
|
|
.txhdr_len = MLXSW_TXHDR_LEN,
|
2018-07-18 11:14:45 +03:00
|
|
|
.profile = &mlxsw_sp1_config_profile,
|
|
|
|
|
.res_query_enabled = true,
|
2020-09-15 11:40:58 +03:00
|
|
|
.fw_fatal_enabled = true,
|
2020-09-27 10:50:11 +03:00
|
|
|
.temp_warn_enabled = true,
|
2018-07-18 11:14:45 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct mlxsw_driver mlxsw_sp2_driver = {
|
|
|
|
|
.kind = mlxsw_sp2_driver_name,
|
|
|
|
|
.priv_size = sizeof(struct mlxsw_sp),
|
2020-09-15 11:40:52 +03:00
|
|
|
.fw_req_rev = &mlxsw_sp2_fw_rev,
|
|
|
|
|
.fw_filename = MLXSW_SP2_FW_FILENAME,
|
2018-07-18 11:14:45 +03:00
|
|
|
.init = mlxsw_sp2_init,
|
|
|
|
|
.fini = mlxsw_sp_fini,
|
|
|
|
|
.basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
|
|
|
|
|
.port_split = mlxsw_sp_port_split,
|
|
|
|
|
.port_unsplit = mlxsw_sp_port_unsplit,
|
|
|
|
|
.sb_pool_get = mlxsw_sp_sb_pool_get,
|
|
|
|
|
.sb_pool_set = mlxsw_sp_sb_pool_set,
|
|
|
|
|
.sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
|
|
|
|
|
.sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
|
|
|
|
|
.sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
|
|
|
|
|
.sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
|
|
|
|
|
.sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
|
|
|
|
|
.sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
|
|
|
|
|
.sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
|
|
|
|
|
.sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
|
2019-08-21 10:19:35 +03:00
|
|
|
.trap_init = mlxsw_sp_trap_init,
|
|
|
|
|
.trap_fini = mlxsw_sp_trap_fini,
|
|
|
|
|
.trap_action_set = mlxsw_sp_trap_action_set,
|
|
|
|
|
.trap_group_init = mlxsw_sp_trap_group_init,
|
2020-03-30 22:38:31 +03:00
|
|
|
.trap_group_set = mlxsw_sp_trap_group_set,
|
2020-03-30 22:38:28 +03:00
|
|
|
.trap_policer_init = mlxsw_sp_trap_policer_init,
|
|
|
|
|
.trap_policer_fini = mlxsw_sp_trap_policer_fini,
|
|
|
|
|
.trap_policer_set = mlxsw_sp_trap_policer_set,
|
|
|
|
|
.trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
|
2018-07-18 11:14:45 +03:00
|
|
|
.txhdr_construct = mlxsw_sp_txhdr_construct,
|
|
|
|
|
.resources_register = mlxsw_sp2_resources_register,
|
2019-02-07 11:22:55 +00:00
|
|
|
.params_register = mlxsw_sp2_params_register,
|
|
|
|
|
.params_unregister = mlxsw_sp2_params_unregister,
|
mlxsw: pci: PTP: Hook into packet transmit path
On Spectrum-1, timestamps are delivered separately from the packets, and
need to paired up. Therefore, at some point after mlxsw_sp_port_xmit()
is invoked, it is necessary to involve the chip-specific driver code to
allow it to do the necessary bookkeeping and matching.
On Spectrum-2, timestamps are delivered in CQE. For that reason,
position the point of driver involvement into mlxsw_pci_cqe_sdq_handle()
to make it hopefully easier to extend for Spectrum-2 in the future.
To tell the driver what port the packet was sent on, keep tx_info
in SKB control buffer.
Introduce a new driver core interface mlxsw_core_ptp_transmitted(), a
driver callback ptp_transmitted, and a PTP op transmitted. The callee is
responsible for taking care of releasing the SKB passed to the new
interfaces, and correspondingly have the new stub callbacks just call
dev_kfree_skb_any().
Follow-up patches will introduce the actual content into
mlxsw_sp1_ptp_transmitted() in particular.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-30 09:04:53 +03:00
|
|
|
.ptp_transmitted = mlxsw_sp_ptp_transmitted,
|
2018-07-18 11:14:45 +03:00
|
|
|
.txhdr_len = MLXSW_TXHDR_LEN,
|
|
|
|
|
.profile = &mlxsw_sp2_config_profile,
|
2018-04-01 17:34:57 +03:00
|
|
|
.res_query_enabled = true,
|
2020-09-15 11:40:58 +03:00
|
|
|
.fw_fatal_enabled = true,
|
2020-09-27 10:50:11 +03:00
|
|
|
.temp_warn_enabled = true,
|
2015-10-16 14:01:37 +02:00
|
|
|
};
|
|
|
|
|
|
2019-08-07 13:42:31 +03:00
|
|
|
static struct mlxsw_driver mlxsw_sp3_driver = {
|
|
|
|
|
.kind = mlxsw_sp3_driver_name,
|
|
|
|
|
.priv_size = sizeof(struct mlxsw_sp),
|
2020-09-15 11:40:52 +03:00
|
|
|
.fw_req_rev = &mlxsw_sp3_fw_rev,
|
|
|
|
|
.fw_filename = MLXSW_SP3_FW_FILENAME,
|
2020-01-15 13:53:44 +02:00
|
|
|
.init = mlxsw_sp3_init,
|
2019-08-07 13:42:31 +03:00
|
|
|
.fini = mlxsw_sp_fini,
|
|
|
|
|
.basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
|
|
|
|
|
.port_split = mlxsw_sp_port_split,
|
|
|
|
|
.port_unsplit = mlxsw_sp_port_unsplit,
|
|
|
|
|
.sb_pool_get = mlxsw_sp_sb_pool_get,
|
|
|
|
|
.sb_pool_set = mlxsw_sp_sb_pool_set,
|
|
|
|
|
.sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
|
|
|
|
|
.sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
|
|
|
|
|
.sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
|
|
|
|
|
.sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
|
|
|
|
|
.sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
|
|
|
|
|
.sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
|
|
|
|
|
.sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
|
|
|
|
|
.sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
|
2019-08-21 10:19:35 +03:00
|
|
|
.trap_init = mlxsw_sp_trap_init,
|
|
|
|
|
.trap_fini = mlxsw_sp_trap_fini,
|
|
|
|
|
.trap_action_set = mlxsw_sp_trap_action_set,
|
|
|
|
|
.trap_group_init = mlxsw_sp_trap_group_init,
|
2020-03-30 22:38:31 +03:00
|
|
|
.trap_group_set = mlxsw_sp_trap_group_set,
|
2020-03-30 22:38:28 +03:00
|
|
|
.trap_policer_init = mlxsw_sp_trap_policer_init,
|
|
|
|
|
.trap_policer_fini = mlxsw_sp_trap_policer_fini,
|
|
|
|
|
.trap_policer_set = mlxsw_sp_trap_policer_set,
|
|
|
|
|
.trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
|
2019-08-07 13:42:31 +03:00
|
|
|
.txhdr_construct = mlxsw_sp_txhdr_construct,
|
|
|
|
|
.resources_register = mlxsw_sp2_resources_register,
|
|
|
|
|
.params_register = mlxsw_sp2_params_register,
|
|
|
|
|
.params_unregister = mlxsw_sp2_params_unregister,
|
|
|
|
|
.ptp_transmitted = mlxsw_sp_ptp_transmitted,
|
|
|
|
|
.txhdr_len = MLXSW_TXHDR_LEN,
|
|
|
|
|
.profile = &mlxsw_sp2_config_profile,
|
|
|
|
|
.res_query_enabled = true,
|
2020-09-15 11:40:58 +03:00
|
|
|
.fw_fatal_enabled = true,
|
2020-09-27 10:50:11 +03:00
|
|
|
.temp_warn_enabled = true,
|
2019-08-07 13:42:31 +03:00
|
|
|
};
|
|
|
|
|
|
2017-02-03 10:29:07 +01:00
|
|
|
bool mlxsw_sp_port_dev_check(const struct net_device *dev)
|
2016-07-04 08:23:12 +02:00
|
|
|
{
|
|
|
|
|
return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-25 18:13:12 +00:00
|
|
|
static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev,
|
|
|
|
|
struct netdev_nested_priv *priv)
|
2016-10-17 19:15:49 -07:00
|
|
|
{
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
if (mlxsw_sp_port_dev_check(lower_dev)) {
|
2020-09-25 18:13:12 +00:00
|
|
|
priv->data = (void *)netdev_priv(lower_dev);
|
2016-10-17 19:15:49 -07:00
|
|
|
ret = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
|
2016-07-04 08:23:12 +02:00
|
|
|
{
|
2020-09-25 18:13:12 +00:00
|
|
|
struct netdev_nested_priv priv = {
|
|
|
|
|
.data = NULL,
|
|
|
|
|
};
|
2016-07-04 08:23:12 +02:00
|
|
|
|
|
|
|
|
if (mlxsw_sp_port_dev_check(dev))
|
|
|
|
|
return netdev_priv(dev);
|
|
|
|
|
|
2020-09-25 18:13:12 +00:00
|
|
|
netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv);
|
2016-10-17 19:15:49 -07:00
|
|
|
|
2020-09-25 18:13:12 +00:00
|
|
|
return (struct mlxsw_sp_port *)priv.data;
|
2016-07-04 08:23:12 +02:00
|
|
|
}
|
|
|
|
|
|
2017-03-10 08:53:39 +01:00
|
|
|
struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
|
2016-07-04 08:23:12 +02:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
|
|
|
|
|
return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-08 08:44:20 +02:00
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
|
2016-07-04 08:23:12 +02:00
|
|
|
{
|
2020-09-25 18:13:12 +00:00
|
|
|
struct netdev_nested_priv priv = {
|
|
|
|
|
.data = NULL,
|
|
|
|
|
};
|
2016-07-04 08:23:12 +02:00
|
|
|
|
|
|
|
|
if (mlxsw_sp_port_dev_check(dev))
|
|
|
|
|
return netdev_priv(dev);
|
|
|
|
|
|
2017-03-06 21:25:20 +01:00
|
|
|
netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
|
2020-09-25 18:13:12 +00:00
|
|
|
&priv);
|
2016-10-17 19:15:49 -07:00
|
|
|
|
2020-09-25 18:13:12 +00:00
|
|
|
return (struct mlxsw_sp_port *)priv.data;
|
2016-07-04 08:23:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
|
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
|
mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
|
|
|
|
|
if (mlxsw_sp_port)
|
|
|
|
|
dev_hold(mlxsw_sp_port->dev);
|
|
|
|
|
rcu_read_unlock();
|
|
|
|
|
return mlxsw_sp_port;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
dev_put(mlxsw_sp_port->dev);
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-19 06:08:45 +00:00
|
|
|
static void
|
|
|
|
|
mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
struct net_device *lag_dev)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
|
|
|
|
|
struct net_device *upper_dev;
|
|
|
|
|
struct list_head *iter;
|
|
|
|
|
|
|
|
|
|
if (netif_is_bridge_port(lag_dev))
|
|
|
|
|
mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
|
|
|
|
|
|
|
|
|
|
netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
|
|
|
|
|
if (!netif_is_bridge_port(upper_dev))
|
|
|
|
|
continue;
|
|
|
|
|
br_dev = netdev_master_upper_dev_get(upper_dev);
|
|
|
|
|
mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-03 12:12:28 +01:00
|
|
|
static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
char sldr_pl[MLXSW_REG_SLDR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
char sldr_pl[MLXSW_REG_SLDR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 lag_id, u8 port_index)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char slcor_pl[MLXSW_REG_SLCOR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
lag_id, port_index);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char slcor_pl[MLXSW_REG_SLCOR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
lag_id);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char slcor_pl[MLXSW_REG_SLCOR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
lag_id);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char slcor_pl[MLXSW_REG_SLCOR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
|
|
|
|
|
lag_id);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
struct net_device *lag_dev,
|
|
|
|
|
u16 *p_lag_id)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_upper *lag;
|
|
|
|
|
int free_lag_id = -1;
|
2016-10-21 16:07:23 +02:00
|
|
|
u64 max_lag;
|
2015-12-03 12:12:28 +01:00
|
|
|
int i;
|
|
|
|
|
|
2016-10-21 16:07:23 +02:00
|
|
|
max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
|
|
|
|
|
for (i = 0; i < max_lag; i++) {
|
2015-12-03 12:12:28 +01:00
|
|
|
lag = mlxsw_sp_lag_get(mlxsw_sp, i);
|
|
|
|
|
if (lag->ref_count) {
|
|
|
|
|
if (lag->dev == lag_dev) {
|
|
|
|
|
*p_lag_id = i;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
} else if (free_lag_id < 0) {
|
|
|
|
|
free_lag_id = i;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (free_lag_id < 0)
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
*p_lag_id = free_lag_id;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool
|
|
|
|
|
mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
struct net_device *lag_dev,
|
2017-10-04 17:48:51 -07:00
|
|
|
struct netdev_lag_upper_info *lag_upper_info,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2015-12-03 12:12:28 +01:00
|
|
|
{
|
|
|
|
|
u16 lag_id;
|
|
|
|
|
|
2017-10-04 17:48:51 -07:00
|
|
|
if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
|
2015-12-03 12:12:28 +01:00
|
|
|
return false;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
|
|
|
|
if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
|
2015-12-03 12:12:28 +01:00
|
|
|
return false;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
2015-12-03 12:12:28 +01:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
u16 lag_id, u8 *p_port_index)
|
|
|
|
|
{
|
2016-10-21 16:07:23 +02:00
|
|
|
u64 max_lag_members;
|
2015-12-03 12:12:28 +01:00
|
|
|
int i;
|
|
|
|
|
|
2016-10-21 16:07:23 +02:00
|
|
|
max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
|
|
|
|
|
MAX_LAG_MEMBERS);
|
|
|
|
|
for (i = 0; i < max_lag_members; i++) {
|
2015-12-03 12:12:28 +01:00
|
|
|
if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
|
|
|
|
|
*p_port_index = i;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
|
2020-12-06 10:22:21 +02:00
|
|
|
struct net_device *lag_dev,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
2015-12-03 12:12:28 +01:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
struct mlxsw_sp_upper *lag;
|
|
|
|
|
u16 lag_id;
|
|
|
|
|
u8 port_index;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
|
|
|
|
|
if (!lag->ref_count) {
|
|
|
|
|
err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
lag->dev = lag_dev;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_col_port_add;
|
|
|
|
|
|
|
|
|
|
mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
mlxsw_sp_port->lag_id = lag_id;
|
|
|
|
|
mlxsw_sp_port->lagged = 1;
|
|
|
|
|
lag->ref_count++;
|
2016-07-02 11:00:11 +02:00
|
|
|
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
/* Port is no longer usable as a router interface */
|
2018-12-20 19:42:33 +00:00
|
|
|
if (mlxsw_sp_port->default_vlan->fid)
|
|
|
|
|
mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
|
2016-07-02 11:00:11 +02:00
|
|
|
|
2020-12-06 10:22:21 +02:00
|
|
|
/* Join a router interface configured on the LAG, if exists */
|
|
|
|
|
err = mlxsw_sp_port_vlan_router_join(mlxsw_sp_port->default_vlan,
|
|
|
|
|
lag_dev, extack);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_router_join;
|
|
|
|
|
|
2015-12-03 12:12:28 +01:00
|
|
|
return 0;
|
|
|
|
|
|
2020-12-06 10:22:21 +02:00
|
|
|
err_router_join:
|
|
|
|
|
lag->ref_count--;
|
|
|
|
|
mlxsw_sp_port->lagged = 0;
|
|
|
|
|
mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
|
2015-12-03 12:12:28 +01:00
|
|
|
err_col_port_add:
|
|
|
|
|
if (!lag->ref_count)
|
|
|
|
|
mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:04:04 +02:00
|
|
|
static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
struct net_device *lag_dev)
|
2015-12-03 12:12:28 +01:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
u16 lag_id = mlxsw_sp_port->lag_id;
|
2016-06-20 23:04:20 +02:00
|
|
|
struct mlxsw_sp_upper *lag;
|
2015-12-03 12:12:28 +01:00
|
|
|
|
|
|
|
|
if (!mlxsw_sp_port->lagged)
|
2016-06-20 23:04:04 +02:00
|
|
|
return;
|
2015-12-03 12:12:28 +01:00
|
|
|
lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
|
|
|
|
|
WARN_ON(lag->ref_count == 0);
|
|
|
|
|
|
2016-06-20 23:04:04 +02:00
|
|
|
mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
|
2015-12-03 12:12:28 +01:00
|
|
|
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
/* Any VLANs configured on the port are no longer valid */
|
2018-12-20 19:42:33 +00:00
|
|
|
mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
|
|
|
|
|
mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
|
2018-12-19 06:08:45 +00:00
|
|
|
/* Make the LAG and its directly linked uppers leave bridges they
|
|
|
|
|
* are memeber in
|
|
|
|
|
*/
|
|
|
|
|
mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
|
2016-01-27 15:20:16 +01:00
|
|
|
|
2016-06-20 23:04:19 +02:00
|
|
|
if (lag->ref_count == 1)
|
2016-06-20 23:04:04 +02:00
|
|
|
mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
|
2015-12-03 12:12:28 +01:00
|
|
|
|
|
|
|
|
mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
mlxsw_sp_port->lagged = 0;
|
|
|
|
|
lag->ref_count--;
|
2016-07-02 11:00:11 +02:00
|
|
|
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
/* Make sure untagged frames are allowed to ingress */
|
2020-11-29 14:54:02 +02:00
|
|
|
mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
|
|
|
|
|
ETH_P_8021Q);
|
2015-12-03 12:12:28 +01:00
|
|
|
}
|
|
|
|
|
|
2015-12-03 12:12:30 +01:00
|
|
|
static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char sldr_pl[MLXSW_REG_SLDR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
u16 lag_id)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
char sldr_pl[MLXSW_REG_SLDR_LEN];
|
|
|
|
|
|
|
|
|
|
mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
|
|
|
|
|
mlxsw_sp_port->local_port);
|
|
|
|
|
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-12 16:29:51 +00:00
|
|
|
static int
|
|
|
|
|
mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
|
2015-12-03 12:12:30 +01:00
|
|
|
{
|
2019-02-12 16:29:51 +00:00
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
|
|
|
|
|
mlxsw_sp_port->lag_id);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_dist_port_add;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_dist_port_add:
|
|
|
|
|
mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
|
|
|
|
|
mlxsw_sp_port->lag_id);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
|
|
|
|
|
mlxsw_sp_port->lag_id);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_col_port_disable;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_col_port_disable:
|
|
|
|
|
mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
|
|
|
|
|
return err;
|
2015-12-03 12:12:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
struct netdev_lag_lower_state_info *info)
|
|
|
|
|
{
|
2019-02-12 16:29:51 +00:00
|
|
|
if (info->tx_enabled)
|
|
|
|
|
return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
|
|
|
|
|
else
|
|
|
|
|
return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
|
2015-12-03 12:12:30 +01:00
|
|
|
}
|
|
|
|
|
|
2017-04-18 16:55:37 +02:00
|
|
|
static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
|
|
|
|
|
bool enable)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
enum mlxsw_reg_spms_state spms_state;
|
|
|
|
|
char *spms_pl;
|
|
|
|
|
u16 vid;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
|
|
|
|
|
MLXSW_REG_SPMS_STATE_DISCARDING;
|
|
|
|
|
|
|
|
|
|
spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
|
|
|
|
|
if (!spms_pl)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
|
|
|
|
|
|
|
|
|
|
for (vid = 0; vid < VLAN_N_VID; vid++)
|
|
|
|
|
mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
|
|
|
|
|
|
|
|
|
|
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
|
|
|
|
|
kfree(spms_pl);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
2017-12-15 08:44:21 +01:00
|
|
|
u16 vid = 1;
|
2017-04-18 16:55:37 +02:00
|
|
|
int err;
|
|
|
|
|
|
2017-05-26 08:37:25 +02:00
|
|
|
err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
|
2017-04-18 16:55:37 +02:00
|
|
|
if (err)
|
|
|
|
|
return err;
|
2017-05-26 08:37:25 +02:00
|
|
|
err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_port_stp_set;
|
2018-12-20 19:42:33 +00:00
|
|
|
err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
|
2017-04-18 16:55:37 +02:00
|
|
|
true, false);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_port_vlan_set;
|
2017-12-15 08:44:21 +01:00
|
|
|
|
|
|
|
|
for (; vid <= VLAN_N_VID - 1; vid++) {
|
|
|
|
|
err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
|
|
|
|
|
vid, false);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_vid_learning_set;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-18 16:55:37 +02:00
|
|
|
return 0;
|
|
|
|
|
|
2017-12-15 08:44:21 +01:00
|
|
|
err_vid_learning_set:
|
|
|
|
|
for (vid--; vid >= 1; vid--)
|
|
|
|
|
mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
|
2017-04-18 16:55:37 +02:00
|
|
|
err_port_vlan_set:
|
|
|
|
|
mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
|
2017-05-26 08:37:25 +02:00
|
|
|
err_port_stp_set:
|
|
|
|
|
mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
|
2017-04-18 16:55:37 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
|
|
|
{
|
2017-12-15 08:44:21 +01:00
|
|
|
u16 vid;
|
|
|
|
|
|
|
|
|
|
for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
|
|
|
|
|
mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
|
|
|
|
|
vid, true);
|
|
|
|
|
|
2018-12-20 19:42:33 +00:00
|
|
|
mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
|
2017-04-18 16:55:37 +02:00
|
|
|
false, false);
|
|
|
|
|
mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
|
2017-05-26 08:37:25 +02:00
|
|
|
mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
|
2017-04-18 16:55:37 +02:00
|
|
|
}
|
|
|
|
|
|
2018-10-17 08:53:31 +00:00
|
|
|
static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
|
|
|
|
|
{
|
|
|
|
|
unsigned int num_vxlans = 0;
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct list_head *iter;
|
|
|
|
|
|
|
|
|
|
netdev_for_each_lower_dev(br_dev, dev, iter) {
|
|
|
|
|
if (netif_is_vxlan(dev))
|
|
|
|
|
num_vxlans++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return num_vxlans > 1;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-28 20:07:04 +00:00
|
|
|
static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
|
|
|
|
|
{
|
|
|
|
|
DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct list_head *iter;
|
|
|
|
|
|
|
|
|
|
netdev_for_each_lower_dev(br_dev, dev, iter) {
|
|
|
|
|
u16 pvid;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (!netif_is_vxlan(dev))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
|
|
|
|
|
if (err || !pvid)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (test_and_set_bit(pvid, vlans))
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-17 08:53:31 +00:00
|
|
|
static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
|
|
|
|
|
struct netlink_ext_ack *extack)
|
|
|
|
|
{
|
|
|
|
|
if (br_multicast_enabled(br_dev)) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-28 20:07:04 +00:00
|
|
|
if (!br_vlan_enabled(br_dev) &&
|
|
|
|
|
mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
|
2018-10-17 08:53:31 +00:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-28 20:07:04 +00:00
|
|
|
if (br_vlan_enabled(br_dev) &&
|
|
|
|
|
!mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
|
2018-10-17 08:53:31 +00:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:29 +02:00
|
|
|
static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
|
|
|
|
|
struct net_device *dev,
|
2015-12-03 12:12:30 +01:00
|
|
|
unsigned long event, void *ptr)
|
2015-10-16 14:01:37 +02:00
|
|
|
{
|
|
|
|
|
struct netdev_notifier_changeupper_info *info;
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
2017-10-04 17:48:51 -07:00
|
|
|
struct netlink_ext_ack *extack;
|
2015-10-16 14:01:37 +02:00
|
|
|
struct net_device *upper_dev;
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp;
|
2016-06-20 23:03:59 +02:00
|
|
|
int err = 0;
|
2020-11-29 14:54:06 +02:00
|
|
|
u16 proto;
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
|
|
|
|
info = ptr;
|
2017-10-04 17:48:51 -07:00
|
|
|
extack = netdev_notifier_info_to_extack(&info->info);
|
2015-10-16 14:01:37 +02:00
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_PRECHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
2016-06-20 23:04:00 +02:00
|
|
|
if (!is_vlan_dev(upper_dev) &&
|
|
|
|
|
!netif_is_lag_master(upper_dev) &&
|
2017-03-16 09:08:18 +01:00
|
|
|
!netif_is_bridge_master(upper_dev) &&
|
2018-07-14 11:39:51 +03:00
|
|
|
!netif_is_ovs_master(upper_dev) &&
|
|
|
|
|
!netif_is_macvlan(upper_dev)) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
|
2016-06-20 23:04:00 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
2016-06-20 23:04:01 +02:00
|
|
|
if (!info->linking)
|
2015-12-03 12:12:28 +01:00
|
|
|
break;
|
2018-10-17 08:53:31 +00:00
|
|
|
if (netif_is_bridge_master(upper_dev) &&
|
|
|
|
|
!mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
|
|
|
|
|
mlxsw_sp_bridge_has_vxlan(upper_dev) &&
|
|
|
|
|
!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
|
|
|
|
|
return -EOPNOTSUPP;
|
2017-12-25 09:05:33 +01:00
|
|
|
if (netdev_has_any_upper_dev(upper_dev) &&
|
|
|
|
|
(!netif_is_bridge_master(upper_dev) ||
|
|
|
|
|
!mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
|
|
|
|
|
upper_dev))) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
|
2017-09-01 10:52:31 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
2015-12-03 12:12:28 +01:00
|
|
|
if (netif_is_lag_master(upper_dev) &&
|
|
|
|
|
!mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
|
2017-10-04 17:48:51 -07:00
|
|
|
info->upper_info, extack))
|
2016-06-20 23:03:59 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
|
2016-06-20 23:04:01 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
2016-06-20 23:04:01 +02:00
|
|
|
if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
|
2017-10-04 17:48:51 -07:00
|
|
|
!netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
|
2016-06-20 23:04:01 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
2018-07-14 11:39:51 +03:00
|
|
|
if (netif_is_macvlan(upper_dev) &&
|
2020-02-20 09:07:59 +02:00
|
|
|
!mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) {
|
2018-07-14 11:39:51 +03:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
2017-10-04 17:48:51 -07:00
|
|
|
if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
|
2017-04-18 16:55:37 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
|
|
|
|
if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
|
2017-04-18 16:55:37 +02:00
|
|
|
return -EINVAL;
|
2017-10-04 17:48:51 -07:00
|
|
|
}
|
2020-11-29 14:54:06 +02:00
|
|
|
if (netif_is_bridge_master(upper_dev)) {
|
|
|
|
|
br_vlan_get_proto(upper_dev, &proto);
|
|
|
|
|
if (br_vlan_enabled(upper_dev) &&
|
|
|
|
|
proto != ETH_P_8021Q && proto != ETH_P_8021AD) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
if (vlan_uses_dev(lower_dev) &&
|
|
|
|
|
br_vlan_enabled(upper_dev) &&
|
|
|
|
|
proto == ETH_P_8021AD) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) {
|
|
|
|
|
struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev);
|
|
|
|
|
|
|
|
|
|
if (br_vlan_enabled(br_dev)) {
|
|
|
|
|
br_vlan_get_proto(br_dev, &proto);
|
|
|
|
|
if (proto == ETH_P_8021AD) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (is_vlan_dev(upper_dev) &&
|
|
|
|
|
ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
2015-10-16 14:01:37 +02:00
|
|
|
break;
|
|
|
|
|
case NETDEV_CHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
if (netif_is_bridge_master(upper_dev)) {
|
2016-06-20 23:04:06 +02:00
|
|
|
if (info->linking)
|
|
|
|
|
err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
|
2017-05-26 08:37:29 +02:00
|
|
|
lower_dev,
|
2017-10-08 11:57:56 +02:00
|
|
|
upper_dev,
|
|
|
|
|
extack);
|
2016-06-20 23:04:06 +02:00
|
|
|
else
|
2017-05-26 08:37:29 +02:00
|
|
|
mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
|
|
|
|
|
lower_dev,
|
|
|
|
|
upper_dev);
|
2015-12-03 12:12:28 +01:00
|
|
|
} else if (netif_is_lag_master(upper_dev)) {
|
2019-01-08 16:48:05 +00:00
|
|
|
if (info->linking) {
|
2015-12-03 12:12:28 +01:00
|
|
|
err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
|
2020-12-06 10:22:21 +02:00
|
|
|
upper_dev, extack);
|
2019-01-08 16:48:05 +00:00
|
|
|
} else {
|
2019-02-12 16:29:51 +00:00
|
|
|
mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
|
2016-06-20 23:04:04 +02:00
|
|
|
mlxsw_sp_port_lag_leave(mlxsw_sp_port,
|
|
|
|
|
upper_dev);
|
2019-01-08 16:48:05 +00:00
|
|
|
}
|
2017-04-18 16:55:37 +02:00
|
|
|
} else if (netif_is_ovs_master(upper_dev)) {
|
|
|
|
|
if (info->linking)
|
|
|
|
|
err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
|
|
|
|
|
else
|
|
|
|
|
mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
|
2018-07-14 11:39:52 +03:00
|
|
|
} else if (netif_is_macvlan(upper_dev)) {
|
|
|
|
|
if (!info->linking)
|
|
|
|
|
mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
|
2018-12-19 06:08:41 +00:00
|
|
|
} else if (is_vlan_dev(upper_dev)) {
|
|
|
|
|
struct net_device *br_dev;
|
|
|
|
|
|
|
|
|
|
if (!netif_is_bridge_port(upper_dev))
|
|
|
|
|
break;
|
|
|
|
|
if (info->linking)
|
|
|
|
|
break;
|
|
|
|
|
br_dev = netdev_master_upper_dev_get(upper_dev);
|
|
|
|
|
mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
|
|
|
|
|
br_dev);
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return err;
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
2015-12-03 12:12:30 +01:00
|
|
|
static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct netdev_notifier_changelowerstate_info *info;
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
mlxsw_sp_port = netdev_priv(dev);
|
|
|
|
|
info = ptr;
|
|
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_CHANGELOWERSTATE:
|
|
|
|
|
if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
|
|
|
|
|
err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
|
|
|
|
|
info->lower_state_info);
|
|
|
|
|
if (err)
|
|
|
|
|
netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return 0;
|
2015-12-03 12:12:30 +01:00
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:29 +02:00
|
|
|
static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
|
|
|
|
|
struct net_device *port_dev,
|
2015-12-03 12:12:30 +01:00
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_PRECHANGEUPPER:
|
|
|
|
|
case NETDEV_CHANGEUPPER:
|
2017-05-26 08:37:29 +02:00
|
|
|
return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
|
|
|
|
|
event, ptr);
|
2015-12-03 12:12:30 +01:00
|
|
|
case NETDEV_CHANGELOWERSTATE:
|
2017-05-26 08:37:29 +02:00
|
|
|
return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
|
|
|
|
|
ptr);
|
2015-12-03 12:12:30 +01:00
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return 0;
|
2015-12-03 12:12:30 +01:00
|
|
|
}
|
|
|
|
|
|
2015-12-03 12:12:28 +01:00
|
|
|
static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct list_head *iter;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
netdev_for_each_lower_dev(lag_dev, dev, iter) {
|
|
|
|
|
if (mlxsw_sp_port_dev_check(dev)) {
|
2017-05-26 08:37:29 +02:00
|
|
|
ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
|
|
|
|
|
ptr);
|
2016-06-20 23:03:59 +02:00
|
|
|
if (ret)
|
2015-12-03 12:12:28 +01:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return 0;
|
2015-12-03 12:12:28 +01:00
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:29 +02:00
|
|
|
static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
|
|
|
|
|
struct net_device *dev,
|
|
|
|
|
unsigned long event, void *ptr,
|
|
|
|
|
u16 vid)
|
2015-12-15 16:03:44 +01:00
|
|
|
{
|
|
|
|
|
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
|
2017-12-25 09:05:33 +01:00
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
|
2015-12-15 16:03:44 +01:00
|
|
|
struct netdev_notifier_changeupper_info *info = ptr;
|
2017-10-08 11:57:55 +02:00
|
|
|
struct netlink_ext_ack *extack;
|
2015-12-15 16:03:44 +01:00
|
|
|
struct net_device *upper_dev;
|
2016-06-20 23:03:59 +02:00
|
|
|
int err = 0;
|
2015-12-15 16:03:44 +01:00
|
|
|
|
2017-10-08 11:57:55 +02:00
|
|
|
extack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
|
2015-12-15 16:03:44 +01:00
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_PRECHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
2018-07-14 11:39:51 +03:00
|
|
|
if (!netif_is_bridge_master(upper_dev) &&
|
|
|
|
|
!netif_is_macvlan(upper_dev)) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
|
2016-06-20 23:03:59 +02:00
|
|
|
return -EINVAL;
|
2017-10-08 11:57:55 +02:00
|
|
|
}
|
2017-09-01 10:52:31 +02:00
|
|
|
if (!info->linking)
|
|
|
|
|
break;
|
2018-10-17 08:53:31 +00:00
|
|
|
if (netif_is_bridge_master(upper_dev) &&
|
|
|
|
|
!mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
|
|
|
|
|
mlxsw_sp_bridge_has_vxlan(upper_dev) &&
|
|
|
|
|
!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
|
|
|
|
|
return -EOPNOTSUPP;
|
2017-12-25 09:05:33 +01:00
|
|
|
if (netdev_has_any_upper_dev(upper_dev) &&
|
|
|
|
|
(!netif_is_bridge_master(upper_dev) ||
|
|
|
|
|
!mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
|
|
|
|
|
upper_dev))) {
|
2018-02-13 11:29:05 +01:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
|
2017-09-01 10:52:31 +02:00
|
|
|
return -EINVAL;
|
2017-10-08 11:57:55 +02:00
|
|
|
}
|
2018-07-14 11:39:51 +03:00
|
|
|
if (netif_is_macvlan(upper_dev) &&
|
2020-02-20 09:07:59 +02:00
|
|
|
!mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
|
2018-07-14 11:39:51 +03:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
2015-12-15 16:03:44 +01:00
|
|
|
break;
|
|
|
|
|
case NETDEV_CHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
2017-03-10 08:53:35 +01:00
|
|
|
if (netif_is_bridge_master(upper_dev)) {
|
|
|
|
|
if (info->linking)
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
|
|
|
|
|
vlan_dev,
|
2017-10-08 11:57:56 +02:00
|
|
|
upper_dev,
|
|
|
|
|
extack);
|
2017-03-10 08:53:35 +01:00
|
|
|
else
|
mlxsw: spectrum: Replace vPorts with Port-VLAN
As explained in the cover letter, since the introduction of the bridge
offload in the mlxsw driver, information related to the offloaded bridge
and bridge ports was stored in the individual port struct,
mlxsw_sp_port.
This lead to a bloated struct storing both physical properties of the
port (e.g., autoneg status) as well as logical properties of an upper
bridge port (e.g., learning, mrouter indication). While this might work
well for simple devices, it proved to be hard to extend when stacked
devices were taken into account and more advanced use-cases (e.g., IGMP
snooping) considered.
This patch removes the excess information from the above struct and
instead stores it in more appropriate structs that represent the bridge
port, the bridge itself and a VLAN configured on the bridge port.
The membership of a port in a bridge is denoted using the Port-VLAN
struct, which points to the bridge port and also member in the bridge
VLAN group of the VLAN it represents. This allows us to completely
remove the vPort abstraction and consolidate many of the code paths
relating to VLAN-aware and unaware bridges.
Note that the FID / vFID code is currently duplicated, but this will
soon go away when the common FID core will be introduced.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-26 08:37:31 +02:00
|
|
|
mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
|
|
|
|
|
vlan_dev,
|
|
|
|
|
upper_dev);
|
2018-07-14 11:39:52 +03:00
|
|
|
} else if (netif_is_macvlan(upper_dev)) {
|
|
|
|
|
if (!info->linking)
|
|
|
|
|
mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
|
2015-12-15 16:03:44 +01:00
|
|
|
} else {
|
2017-03-10 08:53:35 +01:00
|
|
|
err = -EINVAL;
|
|
|
|
|
WARN_ON(1);
|
2015-12-15 16:03:44 +01:00
|
|
|
}
|
2017-03-10 08:53:35 +01:00
|
|
|
break;
|
2015-12-15 16:03:44 +01:00
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return err;
|
2015-12-15 16:03:44 +01:00
|
|
|
}
|
|
|
|
|
|
2017-05-26 08:37:29 +02:00
|
|
|
static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
|
|
|
|
|
struct net_device *lag_dev,
|
|
|
|
|
unsigned long event,
|
|
|
|
|
void *ptr, u16 vid)
|
2015-12-15 16:03:47 +01:00
|
|
|
{
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct list_head *iter;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
netdev_for_each_lower_dev(lag_dev, dev, iter) {
|
|
|
|
|
if (mlxsw_sp_port_dev_check(dev)) {
|
2017-05-26 08:37:29 +02:00
|
|
|
ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
|
|
|
|
|
event, ptr,
|
|
|
|
|
vid);
|
2016-06-20 23:03:59 +02:00
|
|
|
if (ret)
|
2015-12-15 16:03:47 +01:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return 0;
|
2015-12-15 16:03:47 +01:00
|
|
|
}
|
|
|
|
|
|
2018-12-19 06:08:37 +00:00
|
|
|
static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
|
|
|
|
|
struct net_device *br_dev,
|
|
|
|
|
unsigned long event, void *ptr,
|
|
|
|
|
u16 vid)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
|
|
|
|
|
struct netdev_notifier_changeupper_info *info = ptr;
|
|
|
|
|
struct netlink_ext_ack *extack;
|
|
|
|
|
struct net_device *upper_dev;
|
|
|
|
|
|
|
|
|
|
if (!mlxsw_sp)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
extack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_PRECHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
|
|
|
|
if (!netif_is_macvlan(upper_dev)) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
if (!info->linking)
|
|
|
|
|
break;
|
|
|
|
|
if (netif_is_macvlan(upper_dev) &&
|
2020-02-20 09:07:59 +02:00
|
|
|
!mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
|
2018-12-19 06:08:37 +00:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case NETDEV_CHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
|
|
|
|
if (info->linking)
|
|
|
|
|
break;
|
|
|
|
|
if (netif_is_macvlan(upper_dev))
|
|
|
|
|
mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-15 16:03:44 +01:00
|
|
|
static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
|
|
|
|
|
u16 vid = vlan_dev_vlan_id(vlan_dev);
|
|
|
|
|
|
2015-12-15 16:03:47 +01:00
|
|
|
if (mlxsw_sp_port_dev_check(real_dev))
|
2017-05-26 08:37:29 +02:00
|
|
|
return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
|
|
|
|
|
event, ptr, vid);
|
2015-12-15 16:03:47 +01:00
|
|
|
else if (netif_is_lag_master(real_dev))
|
2017-05-26 08:37:29 +02:00
|
|
|
return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
|
|
|
|
|
real_dev, event,
|
|
|
|
|
ptr, vid);
|
2018-12-19 06:08:37 +00:00
|
|
|
else if (netif_is_bridge_master(real_dev))
|
|
|
|
|
return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
|
|
|
|
|
event, ptr, vid);
|
2015-12-15 16:03:44 +01:00
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return 0;
|
2015-12-15 16:03:44 +01:00
|
|
|
}
|
|
|
|
|
|
2018-07-14 11:39:51 +03:00
|
|
|
static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
|
|
|
|
|
struct netdev_notifier_changeupper_info *info = ptr;
|
|
|
|
|
struct netlink_ext_ack *extack;
|
|
|
|
|
struct net_device *upper_dev;
|
2020-11-29 14:54:06 +02:00
|
|
|
u16 proto;
|
2018-07-14 11:39:51 +03:00
|
|
|
|
|
|
|
|
if (!mlxsw_sp)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
extack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_PRECHANGEUPPER:
|
|
|
|
|
upper_dev = info->upper_dev;
|
|
|
|
|
if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
if (!info->linking)
|
|
|
|
|
break;
|
2020-11-29 14:54:06 +02:00
|
|
|
if (br_vlan_enabled(br_dev)) {
|
|
|
|
|
br_vlan_get_proto(br_dev, &proto);
|
|
|
|
|
if (proto == ETH_P_8021AD) {
|
2021-03-10 13:02:15 +02:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge");
|
2020-11-29 14:54:06 +02:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (is_vlan_dev(upper_dev) &&
|
|
|
|
|
ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
2018-07-14 11:39:51 +03:00
|
|
|
if (netif_is_macvlan(upper_dev) &&
|
2020-02-20 09:07:59 +02:00
|
|
|
!mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) {
|
2018-07-14 11:39:51 +03:00
|
|
|
NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case NETDEV_CHANGEUPPER:
|
2018-07-14 11:39:52 +03:00
|
|
|
upper_dev = info->upper_dev;
|
|
|
|
|
if (info->linking)
|
|
|
|
|
break;
|
2018-10-04 15:48:03 +00:00
|
|
|
if (is_vlan_dev(upper_dev))
|
|
|
|
|
mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
|
2018-07-14 11:39:52 +03:00
|
|
|
if (netif_is_macvlan(upper_dev))
|
|
|
|
|
mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
|
2018-07-14 11:39:51 +03:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
|
|
|
|
|
struct netdev_notifier_changeupper_info *info = ptr;
|
|
|
|
|
struct netlink_ext_ack *extack;
|
|
|
|
|
|
|
|
|
|
if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
extack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
|
|
|
|
|
/* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
|
|
|
|
|
NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
|
|
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-30 19:47:14 +03:00
|
|
|
static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct netdev_notifier_changeupper_info *info = ptr;
|
|
|
|
|
|
|
|
|
|
if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
|
|
|
|
|
return false;
|
|
|
|
|
return netif_is_l3_master(info->upper_dev);
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-17 08:53:31 +00:00
|
|
|
static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
|
|
|
|
|
struct net_device *dev,
|
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct netdev_notifier_changeupper_info *cu_info;
|
|
|
|
|
struct netdev_notifier_info *info = ptr;
|
|
|
|
|
struct netlink_ext_ack *extack;
|
|
|
|
|
struct net_device *upper_dev;
|
|
|
|
|
|
|
|
|
|
extack = netdev_notifier_info_to_extack(info);
|
|
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
|
case NETDEV_CHANGEUPPER:
|
|
|
|
|
cu_info = container_of(info,
|
|
|
|
|
struct netdev_notifier_changeupper_info,
|
|
|
|
|
info);
|
|
|
|
|
upper_dev = cu_info->upper_dev;
|
|
|
|
|
if (!netif_is_bridge_master(upper_dev))
|
|
|
|
|
return 0;
|
|
|
|
|
if (!mlxsw_sp_lower_get(upper_dev))
|
|
|
|
|
return 0;
|
|
|
|
|
if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
if (cu_info->linking) {
|
|
|
|
|
if (!netif_running(dev))
|
|
|
|
|
return 0;
|
2018-11-28 20:07:04 +00:00
|
|
|
/* When the bridge is VLAN-aware, the VNI of the VxLAN
|
|
|
|
|
* device needs to be mapped to a VLAN, but at this
|
|
|
|
|
* point no VLANs are configured on the VxLAN device
|
|
|
|
|
*/
|
|
|
|
|
if (br_vlan_enabled(upper_dev))
|
|
|
|
|
return 0;
|
2018-10-17 08:53:31 +00:00
|
|
|
return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
|
2018-11-28 20:07:02 +00:00
|
|
|
dev, 0, extack);
|
2018-10-17 08:53:31 +00:00
|
|
|
} else {
|
2018-11-28 20:07:04 +00:00
|
|
|
/* VLANs were already flushed, which triggered the
|
|
|
|
|
* necessary cleanup
|
|
|
|
|
*/
|
|
|
|
|
if (br_vlan_enabled(upper_dev))
|
|
|
|
|
return 0;
|
2018-11-28 20:07:01 +00:00
|
|
|
mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
|
2018-10-17 08:53:31 +00:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case NETDEV_PRE_UP:
|
|
|
|
|
upper_dev = netdev_master_upper_dev_get(dev);
|
|
|
|
|
if (!upper_dev)
|
|
|
|
|
return 0;
|
|
|
|
|
if (!netif_is_bridge_master(upper_dev))
|
|
|
|
|
return 0;
|
|
|
|
|
if (!mlxsw_sp_lower_get(upper_dev))
|
|
|
|
|
return 0;
|
2018-11-28 20:07:02 +00:00
|
|
|
return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
|
2018-10-17 08:53:31 +00:00
|
|
|
extack);
|
|
|
|
|
case NETDEV_DOWN:
|
|
|
|
|
upper_dev = netdev_master_upper_dev_get(dev);
|
|
|
|
|
if (!upper_dev)
|
|
|
|
|
return 0;
|
|
|
|
|
if (!netif_is_bridge_master(upper_dev))
|
|
|
|
|
return 0;
|
|
|
|
|
if (!mlxsw_sp_lower_get(upper_dev))
|
|
|
|
|
return 0;
|
2018-11-28 20:07:01 +00:00
|
|
|
mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
|
2018-10-17 08:53:31 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-16 16:26:37 +02:00
|
|
|
static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
|
2015-12-03 12:12:28 +01:00
|
|
|
unsigned long event, void *ptr)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev = netdev_notifier_info_to_dev(ptr);
|
2018-02-27 14:53:44 +01:00
|
|
|
struct mlxsw_sp_span_entry *span_entry;
|
2017-10-16 16:26:37 +02:00
|
|
|
struct mlxsw_sp *mlxsw_sp;
|
2016-06-20 23:03:59 +02:00
|
|
|
int err = 0;
|
2015-12-03 12:12:28 +01:00
|
|
|
|
2017-10-16 16:26:37 +02:00
|
|
|
mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
|
2018-02-27 14:53:44 +01:00
|
|
|
if (event == NETDEV_UNREGISTER) {
|
|
|
|
|
span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
|
|
|
|
|
if (span_entry)
|
|
|
|
|
mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
|
|
|
|
|
}
|
2018-02-27 14:53:46 +01:00
|
|
|
mlxsw_sp_span_respin(mlxsw_sp);
|
2018-02-27 14:53:44 +01:00
|
|
|
|
2018-10-17 08:53:31 +00:00
|
|
|
if (netif_is_vxlan(dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
|
2017-11-03 10:03:29 +01:00
|
|
|
if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
|
|
|
|
|
event, ptr);
|
2017-11-03 10:03:41 +01:00
|
|
|
else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
|
|
|
|
|
event, ptr);
|
2018-12-13 11:54:52 +00:00
|
|
|
else if (event == NETDEV_PRE_CHANGEADDR ||
|
|
|
|
|
event == NETDEV_CHANGEADDR ||
|
|
|
|
|
event == NETDEV_CHANGEMTU)
|
2018-12-13 11:54:48 +00:00
|
|
|
err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
|
2017-04-30 19:47:14 +03:00
|
|
|
else if (mlxsw_sp_is_vrf_event(event, ptr))
|
|
|
|
|
err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
|
2016-07-04 08:23:13 +02:00
|
|
|
else if (mlxsw_sp_port_dev_check(dev))
|
2017-05-26 08:37:29 +02:00
|
|
|
err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
|
2016-06-20 23:03:59 +02:00
|
|
|
else if (netif_is_lag_master(dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
|
|
|
|
|
else if (is_vlan_dev(dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
|
2018-07-14 11:39:51 +03:00
|
|
|
else if (netif_is_bridge_master(dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
|
|
|
|
|
else if (netif_is_macvlan(dev))
|
|
|
|
|
err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
|
2015-12-15 16:03:44 +01:00
|
|
|
|
2016-06-20 23:03:59 +02:00
|
|
|
return notifier_from_errno(err);
|
2015-12-03 12:12:28 +01:00
|
|
|
}
|
|
|
|
|
|
2017-10-18 09:56:55 -07:00
|
|
|
static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
|
|
|
|
|
.notifier_call = mlxsw_sp_inetaddr_valid_event,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
|
|
|
|
|
.notifier_call = mlxsw_sp_inet6addr_valid_event,
|
mlxsw: spectrum: Introduce support for router interfaces
Up until now we only supported bridged interfaces. Packets ingressing
through the switch ports were either classified to FIDs (in the case of
the VLAN-aware bridge) or vFIDs (in the case of VLAN-unaware bridges).
The packets were then forwarded according to the FDB. Routing was done
entirely in slowpath, by splitting the vFID range in two and using the
lower 0.5K vFIDs as dummy bridges that simply flooded all incoming
traffic to the CPU.
Instead, allow packets to be routed in the device by creating router
interfaces (RIFs) that will direct them to the router block.
Specifically, the RIFs introduced here are Sub-port RIFs used for VLAN
devices and port netdevs. Packets ingressing from the {Port / LAG ID, VID}
with which the RIF was programmed with will be assigned to a special
kind of FIDs called rFIDs and from there directed to the router.
Create a RIF whenever the first IPv4 address was programmed on a VLAN /
LAG / port netdev. Destroy it upon removal of the last IPv4 address.
Receive these notifications by registering for the 'inetaddr'
notification chain. A non-zero (10) priority is used for the
notification block, so that RIFs will be created before routes are
offloaded via FIB code.
Note that another trigger for RIF destruction are CHANGEUPPER
notifications causing the underlying FID's reference count to go down to
zero. This can happen, for example, when a VLAN netdev with an IP address
is put under bridge. While this configuration doesn't make sense it does
cause the device and the kernel to get out of sync when the netdev is
unbridged. We intend to address this in the future, hopefully in current
cycle.
Finally, Remove the lower 0.5K vFIDs, as they are deprecated by the RIFs,
which will trap packets according to their DIP.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-04 08:23:14 +02:00
|
|
|
};
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
|
2016-10-27 15:12:59 +02:00
|
|
|
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
|
|
|
|
|
{0, },
|
|
|
|
|
};
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
static struct pci_driver mlxsw_sp1_pci_driver = {
|
|
|
|
|
.name = mlxsw_sp1_driver_name,
|
|
|
|
|
.id_table = mlxsw_sp1_pci_id_table,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
|
|
|
|
|
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
|
|
|
|
|
{0, },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct pci_driver mlxsw_sp2_pci_driver = {
|
|
|
|
|
.name = mlxsw_sp2_driver_name,
|
|
|
|
|
.id_table = mlxsw_sp2_pci_id_table,
|
2016-10-27 15:12:59 +02:00
|
|
|
};
|
|
|
|
|
|
2019-08-07 13:42:31 +03:00
|
|
|
static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
|
|
|
|
|
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
|
|
|
|
|
{0, },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct pci_driver mlxsw_sp3_pci_driver = {
|
|
|
|
|
.name = mlxsw_sp3_driver_name,
|
|
|
|
|
.id_table = mlxsw_sp3_pci_id_table,
|
|
|
|
|
};
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
static int __init mlxsw_sp_module_init(void)
|
|
|
|
|
{
|
|
|
|
|
int err;
|
|
|
|
|
|
2017-10-18 09:56:55 -07:00
|
|
|
register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
|
|
|
|
|
register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
|
2016-09-01 10:37:43 +02:00
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_sp1_core_driver_register;
|
|
|
|
|
|
|
|
|
|
err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_sp2_core_driver_register;
|
|
|
|
|
|
2019-08-07 13:42:31 +03:00
|
|
|
err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_sp3_core_driver_register;
|
|
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
|
2015-10-16 14:01:37 +02:00
|
|
|
if (err)
|
2018-07-18 11:14:45 +03:00
|
|
|
goto err_sp1_pci_driver_register;
|
2016-10-27 15:12:59 +02:00
|
|
|
|
2018-07-18 11:14:45 +03:00
|
|
|
err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
|
2016-10-27 15:12:59 +02:00
|
|
|
if (err)
|
2018-07-18 11:14:45 +03:00
|
|
|
goto err_sp2_pci_driver_register;
|
2016-10-27 15:12:59 +02:00
|
|
|
|
2019-08-07 13:42:31 +03:00
|
|
|
err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_sp3_pci_driver_register;
|
|
|
|
|
|
2015-10-16 14:01:37 +02:00
|
|
|
return 0;
|
|
|
|
|
|
2019-08-07 13:42:31 +03:00
|
|
|
err_sp3_pci_driver_register:
|
|
|
|
|
mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
|
2018-07-18 11:14:45 +03:00
|
|
|
err_sp2_pci_driver_register:
|
2019-07-31 09:33:14 +03:00
|
|
|
mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
|
2018-07-18 11:14:45 +03:00
|
|
|
err_sp1_pci_driver_register:
|
2019-08-07 13:42:31 +03:00
|
|
|
mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
|
|
|
|
|
err_sp3_core_driver_register:
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
|
|
|
|
|
err_sp2_core_driver_register:
|
|
|
|
|
mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
|
|
|
|
|
err_sp1_core_driver_register:
|
2017-10-18 09:56:55 -07:00
|
|
|
unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
|
|
|
|
|
unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
|
2015-10-16 14:01:37 +02:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit mlxsw_sp_module_exit(void)
|
|
|
|
|
{
|
2019-08-07 13:42:31 +03:00
|
|
|
mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
|
|
|
|
|
mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
|
2019-08-07 13:42:31 +03:00
|
|
|
mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
|
2018-07-18 11:14:45 +03:00
|
|
|
mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
|
|
|
|
|
mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
|
2017-10-18 09:56:55 -07:00
|
|
|
unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
|
|
|
|
|
unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
|
2015-10-16 14:01:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
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module_init(mlxsw_sp_module_init);
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module_exit(mlxsw_sp_module_exit);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
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MODULE_DESCRIPTION("Mellanox Spectrum driver");
|
2018-07-18 11:14:45 +03:00
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|
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MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
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MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
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2019-08-07 13:42:31 +03:00
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MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
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2018-07-08 23:51:26 +03:00
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MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
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2019-10-30 11:34:51 +02:00
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|
MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);
|
2020-06-23 22:13:46 +03:00
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|
|
MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME);
|