2018-06-11 23:49:36 +09:00
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// SPDX-License-Identifier: GPL-2.0
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2012-07-06 17:08:07 +09:00
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/*
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2018-10-22 03:21:20 +09:00
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* Device Tree Source for the R-Mobile A1 (R8A77400) SoC
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2012-07-06 17:08:07 +09:00
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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2014-08-08 16:23:10 +02:00
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#include <dt-bindings/clock/r8a7740-clock.h>
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2016-01-25 09:52:58 +09:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2013-11-19 03:18:25 +01:00
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#include <dt-bindings/interrupt-controller/irq.h>
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2012-07-06 17:08:07 +09:00
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/ {
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compatible = "renesas,r8a7740";
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2014-04-30 02:41:28 +02:00
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interrupt-parent = <&gic>;
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2016-10-21 11:16:09 +02:00
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#address-cells = <1>;
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#size-cells = <1>;
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2012-07-06 17:08:07 +09:00
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cpus {
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2013-04-18 18:39:50 +01:00
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#address-cells = <1>;
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#size-cells = <0>;
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2012-07-06 17:08:07 +09:00
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cpu@0 {
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compatible = "arm,cortex-a9";
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2013-04-18 18:39:50 +01:00
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device_type = "cpu";
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reg = <0x0>;
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2014-05-08 08:32:29 +09:00
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clock-frequency = <800000000>;
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_a3sm>;
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2015-11-23 14:55:59 +01:00
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next-level-cache = <&L2>;
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2012-07-06 17:08:07 +09:00
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};
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};
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2013-04-17 12:34:05 +02:00
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gic: interrupt-controller@c2800000 {
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2015-11-20 13:36:53 +01:00
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compatible = "arm,pl390";
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2013-04-17 12:34:05 +02:00
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xc2800000 0x1000>,
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<0xc2000000 0x1000>;
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};
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2016-05-20 09:09:54 +02:00
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L2: cache-controller@f0100000 {
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2015-11-23 14:55:59 +01:00
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compatible = "arm,pl310-cache";
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reg = <0xf0100000 0x1000>;
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2016-01-25 09:52:58 +09:00
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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2015-11-23 14:55:59 +01:00
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power-domains = <&pd_a3sm>;
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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arm,shared-override;
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cache-unified;
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cache-level = <2>;
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};
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2015-01-14 12:13:01 +01:00
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dbsc3: memory-controller@fe400000 {
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compatible = "renesas,dbsc3-r8a7740";
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reg = <0xfe400000 0x400>;
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power-domains = <&pd_a4s>;
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};
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2013-07-24 12:59:09 +09:00
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pmu {
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compatible = "arm,cortex-a9-pmu";
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2016-01-25 09:52:58 +09:00
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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2013-07-24 12:59:09 +09:00
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};
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2014-12-03 14:41:46 +01:00
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ptm {
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compatible = "arm,coresight-etm3x";
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power-domains = <&pd_d4>;
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};
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2018-04-26 20:24:43 +02:00
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ceu0: ceu@fe910000 {
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reg = <0xfe910000 0x3000>;
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compatible = "renesas,r8a7740-ceu";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
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power-domains = <&pd_a4r>;
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status = "disabled";
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};
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2018-05-15 10:00:38 +02:00
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ceu1: ceu@fe914000 {
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reg = <0xfe914000 0x3000>;
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compatible = "renesas,r8a7740-ceu";
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
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power-domains = <&pd_a4r>;
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status = "disabled";
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};
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2014-08-12 09:04:38 +09:00
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cmt1: timer@e6138000 {
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2020-04-20 17:15:53 +02:00
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compatible = "renesas,r8a7740-cmt1";
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2014-08-12 09:04:38 +09:00
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reg = <0xe6138000 0x170>;
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2016-01-25 09:52:58 +09:00
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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2014-08-12 09:04:38 +09:00
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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clock-names = "fck";
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_c5>;
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2014-08-12 09:04:38 +09:00
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status = "disabled";
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};
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2013-04-17 12:34:05 +02:00
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/* irqpin0: IRQ0 - IRQ7 */
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2015-04-27 14:55:25 +02:00
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irqpin0: interrupt-controller@e6900000 {
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2013-11-28 08:15:04 +09:00
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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2013-04-17 12:34:05 +02:00
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900000 4>,
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<0xe6900010 4>,
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<0xe6900020 1>,
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<0xe6900040 1>,
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<0xe6900060 1>;
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ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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2014-09-12 15:15:20 +02:00
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_a4s>;
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2013-04-17 12:34:05 +02:00
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};
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/* irqpin1: IRQ8 - IRQ15 */
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2015-04-27 14:55:25 +02:00
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irqpin1: interrupt-controller@e6900004 {
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2013-11-28 08:15:04 +09:00
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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2013-04-17 12:34:05 +02:00
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900004 4>,
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<0xe6900014 4>,
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<0xe6900024 1>,
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<0xe6900044 1>,
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<0xe6900064 1>;
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ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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2014-09-12 15:15:20 +02:00
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_a4s>;
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2013-04-17 12:34:05 +02:00
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};
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/* irqpin2: IRQ16 - IRQ23 */
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2015-04-27 14:55:25 +02:00
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irqpin2: interrupt-controller@e6900008 {
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2013-11-28 08:15:04 +09:00
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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2013-04-17 12:34:05 +02:00
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900008 4>,
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<0xe6900018 4>,
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<0xe6900028 1>,
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<0xe6900048 1>,
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<0xe6900068 1>;
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ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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2014-09-12 15:15:20 +02:00
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_a4s>;
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2013-04-17 12:34:05 +02:00
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};
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/* irqpin3: IRQ24 - IRQ31 */
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2015-04-27 14:55:25 +02:00
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irqpin3: interrupt-controller@e690000c {
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2013-11-28 08:15:04 +09:00
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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2013-04-17 12:34:05 +02:00
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe690000c 4>,
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<0xe690001c 4>,
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<0xe690002c 1>,
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<0xe690004c 1>,
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<0xe690006c 1>;
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ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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2014-09-12 15:15:20 +02:00
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_a4s>;
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2013-04-17 12:34:05 +02:00
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};
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2014-05-07 22:32:29 +02:00
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ether: ethernet@e9a00000 {
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compatible = "renesas,gether-r8a7740";
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reg = <0xe9a00000 0x800>,
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<0xe9a01800 0x800>;
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2016-01-25 09:52:58 +09:00
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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2014-08-08 16:23:11 +02:00
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clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
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2014-12-03 14:41:46 +01:00
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power-domains = <&pd_a4s>;
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2014-05-07 22:32:29 +02:00
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phy-mode = "mii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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2013-04-17 12:34:05 +02:00
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i2c0: i2c@fff20000 {
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#address-cells = <1>;
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#size-cells = <0>;
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2014-03-27 11:45:44 +01:00
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compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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2013-04-17 12:34:05 +02:00
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reg = <0xfff20000 0x425>;
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ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
|
|
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a4r>;
|
2013-09-26 13:06:01 +02:00
|
|
|
status = "disabled";
|
2013-04-17 12:34:05 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@e6c20000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2014-03-27 11:45:44 +01:00
|
|
|
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
|
2013-04-17 12:34:05 +02:00
|
|
|
reg = <0xe6c20000 0x425>;
|
ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
|
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2013-09-26 13:06:01 +02:00
|
|
|
status = "disabled";
|
2013-04-17 12:34:05 +02:00
|
|
|
};
|
2012-11-20 14:02:54 +01:00
|
|
|
|
2014-07-07 09:54:41 +02:00
|
|
|
scifa0: serial@e6c40000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6c40000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa1: serial@e6c50000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6c50000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa2: serial@e6c60000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6c60000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
2014-10-02 20:42:29 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa3: serial@e6c70000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6c70000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa4: serial@e6c80000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6c80000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa5: serial@e6cb0000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6cb0000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa6: serial@e6cc0000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6cc0000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa7: serial@e6cd0000 {
|
|
|
|
|
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
|
|
|
|
|
reg = <0xe6cd0000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2015-04-27 15:55:23 +02:00
|
|
|
scifb: serial@e6c30000 {
|
2014-07-07 09:54:41 +02:00
|
|
|
compatible = "renesas,scifb-r8a7740", "renesas,scifb";
|
|
|
|
|
reg = <0xe6c30000 0x100>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
|
2016-01-29 10:47:34 +01:00
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2014-07-07 09:54:41 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-08-21 13:23:51 +02:00
|
|
|
pfc: pinctrl@e6050000 {
|
2012-11-20 14:02:54 +01:00
|
|
|
compatible = "renesas,pfc-r8a7740";
|
|
|
|
|
reg = <0xe6050000 0x8000>,
|
|
|
|
|
<0xe605800c 0x20>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
ARM: shmobile: r8a7740 dtsi: Add missing "gpio-ranges" to gpio node
If a GPIO driver uses gpiochip_add_pin_range() (which is usually the
case for GPIO/PFC combos), the GPIO hogging mechanism configured from DT
doesn't work:
requesting hog GPIO lcd0 (chip r8a7740_pfc, offset 176) failed
The actual error code is -517 == -EPROBE_DEFER.
The problem is that PFC+GPIO registration is handled in multiple steps:
1. pinctrl_register(),
2. gpiochip_add(),
3. gpiochip_add_pin_range().
Configuration of the hogs is handled in gpiochip_add():
gpiochip_add
of_gpiochip_add
of_gpiochip_scan_hogs
gpiod_hog
gpiochip_request_own_desc
__gpiod_request
chip->request
pinctrl_request_gpio
pinctrl_get_device_gpio_range
However, at this point the GPIO controller hasn't been added to
pinctrldev_list yet, so the range can't be found, and the operation fails
with -EPROBE_DEFER.
To fix this, add a "gpio-ranges" property to the gpio device node, so
the range is added by of_gpiochip_add_pin_range(), which is called by
of_gpiochip_add() before the call to of_gpiochip_scan_hogs().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-04 15:55:15 +02:00
|
|
|
gpio-ranges = <&pfc 0 0 212>;
|
2013-12-11 04:26:28 +01:00
|
|
|
interrupts-extended =
|
|
|
|
|
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
|
|
|
|
|
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
|
|
|
|
|
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
|
|
|
|
|
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
|
|
|
|
|
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
|
|
|
|
|
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
|
|
|
|
|
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
|
|
|
|
|
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_c5>;
|
2012-11-20 14:02:54 +01:00
|
|
|
};
|
2013-09-09 16:33:57 -07:00
|
|
|
|
2013-07-26 00:51:00 +02:00
|
|
|
tpu: pwm@e6600000 {
|
|
|
|
|
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
|
2017-12-19 17:02:05 +01:00
|
|
|
reg = <0xe6600000 0x148>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2013-07-26 00:51:00 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
};
|
2013-09-27 10:02:57 +02:00
|
|
|
|
2013-10-21 19:35:08 -07:00
|
|
|
mmcif0: mmc@e6bd0000 {
|
2014-03-27 11:45:44 +01:00
|
|
|
compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
|
2013-09-27 10:02:57 +02:00
|
|
|
reg = <0xe6bd0000 0x100>;
|
ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
|
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp3_clks R8A7740_CLK_MMC>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2013-09-27 10:02:57 +02:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-07-10 21:08:56 +09:00
|
|
|
sdhi0: mmc@e6850000 {
|
2013-09-27 10:02:57 +02:00
|
|
|
compatible = "renesas,sdhi-r8a7740";
|
|
|
|
|
reg = <0xe6850000 0x100>;
|
ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
|
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2013-09-27 10:02:57 +02:00
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-sdio-irq;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-07-10 21:08:56 +09:00
|
|
|
sdhi1: mmc@e6860000 {
|
2013-09-27 10:02:57 +02:00
|
|
|
compatible = "renesas,sdhi-r8a7740";
|
|
|
|
|
reg = <0xe6860000 0x100>;
|
ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
|
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2013-09-27 10:02:57 +02:00
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-sdio-irq;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-10-21 19:35:08 -07:00
|
|
|
|
2020-07-10 21:08:56 +09:00
|
|
|
sdhi2: mmc@e6870000 {
|
2013-10-21 19:35:08 -07:00
|
|
|
compatible = "renesas,sdhi-r8a7740";
|
|
|
|
|
reg = <0xe6870000 0x100>;
|
ARM: dts: renesas: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property, leading
to warnings like:
pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long
pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-12-13 17:41:10 +01:00
|
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a3sp>;
|
2013-10-21 19:35:08 -07:00
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-sdio-irq;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-12-03 17:28:41 -08:00
|
|
|
|
|
|
|
|
sh_fsi2: sound@fe1f0000 {
|
|
|
|
|
#sound-dai-cells = <1>;
|
2014-03-27 11:45:44 +01:00
|
|
|
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
|
2013-12-03 17:28:41 -08:00
|
|
|
reg = <0xfe1f0000 0x400>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 9 0x4>;
|
2014-08-08 16:23:11 +02:00
|
|
|
clocks = <&mstp3_clks R8A7740_CLK_FSI>;
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a4mp>;
|
2013-12-03 17:28:41 -08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2014-08-08 16:23:10 +02:00
|
|
|
|
2014-10-22 11:38:28 +02:00
|
|
|
tmu0: timer@fff80000 {
|
|
|
|
|
compatible = "renesas,tmu-r8a7740", "renesas,tmu";
|
|
|
|
|
reg = <0xfff80000 0x2c>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
2014-10-22 11:38:28 +02:00
|
|
|
clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
|
|
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a4r>;
|
2014-10-22 11:38:28 +02:00
|
|
|
|
|
|
|
|
#renesas,channels = <3>;
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tmu1: timer@fff90000 {
|
|
|
|
|
compatible = "renesas,tmu-r8a7740", "renesas,tmu";
|
|
|
|
|
reg = <0xfff90000 0x2c>;
|
2016-01-25 09:52:58 +09:00
|
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
2014-10-22 11:38:28 +02:00
|
|
|
clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
|
|
|
|
|
clock-names = "fck";
|
2014-12-03 14:41:46 +01:00
|
|
|
power-domains = <&pd_a4r>;
|
2014-10-22 11:38:28 +02:00
|
|
|
|
|
|
|
|
#renesas,channels = <3>;
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-08 16:23:10 +02:00
|
|
|
clocks {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
/* External root clock */
|
2016-03-18 08:14:31 +09:00
|
|
|
extalr_clk: extalr {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
extal1_clk: extal1 {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
extal2_clk: extal2 {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
dv_clk: dv {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <27000000>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fmsick_clk: fmsick {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fmsock_clk: fmsock {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fsiack_clk: fsiack {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fsibck_clk: fsibck {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Special CPG clocks */
|
|
|
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
|
|
|
|
compatible = "renesas,r8a7740-cpg-clocks";
|
|
|
|
|
reg = <0xe6150000 0x10000>;
|
2020-05-08 11:59:18 +02:00
|
|
|
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
2014-08-08 16:23:10 +02:00
|
|
|
#clock-cells = <1>;
|
|
|
|
|
clock-output-names = "system", "pllc0", "pllc1",
|
|
|
|
|
"pllc2", "r",
|
|
|
|
|
"usb24s",
|
|
|
|
|
"i", "zg", "b", "m1", "hp",
|
|
|
|
|
"hpp", "usbp", "s", "zb", "m3",
|
|
|
|
|
"cp";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Variable factor clocks (DIV6) */
|
2016-03-18 08:14:31 +09:00
|
|
|
vclk1_clk: vclk1@e6150008 {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150008 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_USB24S>,
|
|
|
|
|
<&extal1_div2_clk>, <&extalr_clk>, <0>,
|
|
|
|
|
<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
vclk2_clk: vclk2@e615000c {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe615000c 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_USB24S>,
|
|
|
|
|
<&extal1_div2_clk>, <&extalr_clk>, <0>,
|
|
|
|
|
<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fmsi_clk: fmsi@e6150010 {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150010 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fmso_clk: fmso@e6150014 {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150014 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
fsia_clk: fsia@e6150018 {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150018 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
sub_clk: sub@e6150080 {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150080 4>;
|
2015-01-21 17:17:39 +01:00
|
|
|
clocks = <&pllc1_div2_clk>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
|
2014-08-08 16:23:10 +02:00
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
spu_clk: spu@e6150084 {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150084 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
vou_clk: vou@e6150088 {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe6150088 4>;
|
|
|
|
|
clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
|
|
|
|
|
<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
stpro_clk: stpro@e615009c {
|
2015-01-21 17:17:39 +01:00
|
|
|
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0xe615009c 4>;
|
|
|
|
|
clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
2014-08-08 16:23:10 +02:00
|
|
|
|
|
|
|
|
/* Fixed factor clocks */
|
2016-03-18 08:14:31 +09:00
|
|
|
pllc1_div2_clk: pllc1_div2 {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <2>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
};
|
2016-03-18 08:14:31 +09:00
|
|
|
extal1_div2_clk: extal1_div2 {
|
2014-08-08 16:23:10 +02:00
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&extal1_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <2>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Gate clocks */
|
|
|
|
|
subck_clks: subck_clks@e6150080 {
|
|
|
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0xe6150080 4>;
|
|
|
|
|
clocks = <&sub_clk>, <&sub_clk>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 19:49:35 +01:00
|
|
|
clock-indices = <
|
2014-08-08 16:23:10 +02:00
|
|
|
R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
|
|
|
|
"subck", "subck2";
|
|
|
|
|
};
|
|
|
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
|
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0xe6150134 4>, <0xe6150038 4>;
|
|
|
|
|
clocks = <&cpg_clocks R8A7740_CLK_S>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_B>,
|
2014-11-05 11:04:34 +01:00
|
|
|
<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
|
2014-08-08 16:23:10 +02:00
|
|
|
<&cpg_clocks R8A7740_CLK_B>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 19:49:35 +01:00
|
|
|
clock-indices = <
|
2014-08-08 16:23:10 +02:00
|
|
|
R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
|
|
|
|
|
R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
|
|
|
|
|
R8A7740_CLK_LCDC0
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
|
|
|
|
"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
|
|
|
|
|
"tmu1", "lcdc0";
|
|
|
|
|
};
|
|
|
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
|
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0xe6150138 4>, <0xe6150040 4>;
|
2014-09-12 15:15:20 +02:00
|
|
|
clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
|
2014-08-08 16:23:10 +02:00
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
|
|
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
|
|
|
|
<&sub_clk>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 19:49:35 +01:00
|
|
|
clock-indices = <
|
2014-09-12 15:15:20 +02:00
|
|
|
R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
|
|
|
|
|
R8A7740_CLK_SCIFA7
|
2014-08-08 16:23:10 +02:00
|
|
|
R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
|
|
|
|
|
R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
|
|
|
|
|
R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
|
|
|
|
|
R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
|
|
|
|
|
R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
|
|
|
|
|
R8A7740_CLK_SCIFA4
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
2014-09-12 15:15:20 +02:00
|
|
|
"scifa6", "intca",
|
|
|
|
|
"scifa7", "dmac1", "dmac2", "dmac3",
|
2014-08-08 16:23:10 +02:00
|
|
|
"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
|
|
|
|
|
"scifa2", "scifa3", "scifa4";
|
|
|
|
|
};
|
|
|
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
|
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0xe615013c 4>, <0xe6150048 4>;
|
|
|
|
|
clocks = <&cpg_clocks R8A7740_CLK_R>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&sub_clk>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 19:49:35 +01:00
|
|
|
clock-indices = <
|
2014-08-08 16:23:10 +02:00
|
|
|
R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
|
|
|
|
|
R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
|
|
|
|
|
R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
|
|
|
|
"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
|
|
|
|
|
"mmc", "gether", "tpu0";
|
|
|
|
|
};
|
|
|
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
|
|
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0xe6150140 4>, <0xe615004c 4>;
|
|
|
|
|
clocks = <&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
|
|
|
<&cpg_clocks R8A7740_CLK_HP>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 19:49:35 +01:00
|
|
|
clock-indices = <
|
2014-08-08 16:23:10 +02:00
|
|
|
R8A7740_CLK_USBH R8A7740_CLK_SDHI2
|
|
|
|
|
R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
|
|
|
|
"usbhost", "sdhi2", "usbfunc", "usphy";
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-12-03 14:41:46 +01:00
|
|
|
|
|
|
|
|
sysc: system-controller@e6180000 {
|
|
|
|
|
compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
|
|
|
|
|
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
|
|
|
|
|
|
|
|
|
|
pm-domains {
|
|
|
|
|
pd_c5: c5 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
|
|
|
|
|
pd_a4lc: a4lc@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_a4mp: a4mp@2 {
|
|
|
|
|
reg = <2>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_d4: d4@3 {
|
|
|
|
|
reg = <3>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_a4r: a4r@5 {
|
|
|
|
|
reg = <5>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
|
|
|
|
|
pd_a3rv: a3rv@6 {
|
|
|
|
|
reg = <6>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_a4s: a4s@10 {
|
|
|
|
|
reg = <10>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
|
|
|
|
|
pd_a3sp: a3sp@11 {
|
|
|
|
|
reg = <11>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_a3sm: a3sm@12 {
|
|
|
|
|
reg = <12>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_a3sg: a3sg@13 {
|
|
|
|
|
reg = <13>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pd_a4su: a4su@20 {
|
|
|
|
|
reg = <20>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2012-07-06 17:08:07 +09:00
|
|
|
};
|
