forked from Minki/linux
710 lines
22 KiB
C
710 lines
22 KiB
C
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/*
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* This file is part of the Chelsio T3 Ethernet driver.
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*
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* Copyright (C) 2005-2006 Chelsio Communications. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
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* release for licensing terms and conditions.
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*/
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#ifndef __CHELSIO_COMMON_H
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#define __CHELSIO_COMMON_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include "version.h"
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#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
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#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
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#define CH_ALERT(adap, fmt, ...) \
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dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
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/*
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* More powerful macro that selectively prints messages based on msg_enable.
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* For info and debugging messages.
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*/
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#define CH_MSG(adapter, level, category, fmt, ...) do { \
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if ((adapter)->msg_enable & NETIF_MSG_##category) \
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dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
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## __VA_ARGS__); \
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} while (0)
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#ifdef DEBUG
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# define CH_DBG(adapter, category, fmt, ...) \
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CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
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#else
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# define CH_DBG(adapter, category, fmt, ...)
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#endif
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/* Additional NETIF_MSG_* categories */
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#define NETIF_MSG_MMIO 0x8000000
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struct t3_rx_mode {
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struct net_device *dev;
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struct dev_mc_list *mclist;
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unsigned int idx;
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};
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static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev,
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struct dev_mc_list *mclist)
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{
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p->dev = dev;
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p->mclist = mclist;
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p->idx = 0;
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}
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static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm)
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{
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u8 *addr = NULL;
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if (rm->mclist && rm->idx < rm->dev->mc_count) {
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addr = rm->mclist->dmi_addr;
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rm->mclist = rm->mclist->next;
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rm->idx++;
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}
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return addr;
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}
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enum {
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MAX_NPORTS = 2, /* max # of ports */
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MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
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EEPROMSIZE = 8192, /* Serial EEPROM size */
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RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
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TCB_SIZE = 128, /* TCB size */
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NMTUS = 16, /* size of MTU table */
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NCCTRL_WIN = 32, /* # of congestion control windows */
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};
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#define MAX_RX_COALESCING_LEN 16224U
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enum {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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enum {
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SUPPORTED_OFFLOAD = 1 << 24,
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SUPPORTED_IRQ = 1 << 25
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};
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enum { /* adapter interrupt-maintained statistics */
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STAT_ULP_CH0_PBL_OOB,
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STAT_ULP_CH1_PBL_OOB,
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STAT_PCI_CORR_ECC,
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IRQ_NUM_STATS /* keep last */
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};
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enum {
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SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
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SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
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SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
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};
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enum sge_context_type { /* SGE egress context types */
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SGE_CNTXT_RDMA = 0,
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SGE_CNTXT_ETH = 2,
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SGE_CNTXT_OFLD = 4,
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SGE_CNTXT_CTRL = 5
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};
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enum {
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AN_PKT_SIZE = 32, /* async notification packet size */
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IMMED_PKT_SIZE = 48 /* packet size for immediate data */
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};
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struct sg_ent { /* SGE scatter/gather entry */
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u32 len[2];
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u64 addr[2];
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};
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#ifndef SGE_NUM_GENBITS
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/* Must be 1 or 2 */
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# define SGE_NUM_GENBITS 2
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#endif
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#define TX_DESC_FLITS 16U
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#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
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struct cphy;
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struct adapter;
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struct mdio_ops {
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int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int *val);
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int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int val);
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};
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struct adapter_info {
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unsigned char nports; /* # of ports */
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unsigned char phy_base_addr; /* MDIO PHY base address */
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unsigned char mdien;
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unsigned char mdiinv;
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unsigned int gpio_out; /* GPIO output settings */
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unsigned int gpio_intr; /* GPIO IRQ enable mask */
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unsigned long caps; /* adapter capabilities */
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const struct mdio_ops *mdio_ops; /* MDIO operations */
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const char *desc; /* product description */
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};
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struct port_type_info {
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void (*phy_prep)(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *ops);
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unsigned int caps;
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const char *desc;
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};
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struct mc5_stats {
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unsigned long parity_err;
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unsigned long active_rgn_full;
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unsigned long nfa_srch_err;
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unsigned long unknown_cmd;
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unsigned long reqq_parity_err;
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unsigned long dispq_parity_err;
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unsigned long del_act_empty;
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};
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struct mc7_stats {
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unsigned long corr_err;
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unsigned long uncorr_err;
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unsigned long parity_err;
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unsigned long addr_err;
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};
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struct mac_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_octets_bad; /* total # of octets in error frames */
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u64 tx_frames; /* all good frames */
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u64 tx_mcast_frames; /* good multicast frames */
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u64 tx_bcast_frames; /* good broadcast frames */
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u64 tx_pause; /* # of transmitted pause frames */
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u64 tx_deferred; /* frames with deferred transmissions */
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u64 tx_late_collisions; /* # of late collisions */
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u64 tx_total_collisions; /* # of total collisions */
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u64 tx_excess_collisions; /* frame errors from excessive collissions */
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u64 tx_underrun; /* # of Tx FIFO underruns */
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u64 tx_len_errs; /* # of Tx length errors */
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u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
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u64 tx_excess_deferral; /* # of frames with excessive deferral */
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u64 tx_fcs_errs; /* # of frames with bad FCS */
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u64 tx_frames_64; /* # of Tx frames in a particular range */
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u64 tx_frames_65_127;
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u64 tx_frames_128_255;
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u64 tx_frames_256_511;
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u64 tx_frames_512_1023;
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u64 tx_frames_1024_1518;
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u64 tx_frames_1519_max;
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u64 rx_octets; /* total # of octets in good frames */
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u64 rx_octets_bad; /* total # of octets in error frames */
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u64 rx_frames; /* all good frames */
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u64 rx_mcast_frames; /* good multicast frames */
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u64 rx_bcast_frames; /* good broadcast frames */
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u64 rx_pause; /* # of received pause frames */
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u64 rx_fcs_errs; /* # of received frames with bad FCS */
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u64 rx_align_errs; /* alignment errors */
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u64 rx_symbol_errs; /* symbol errors */
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u64 rx_data_errs; /* data errors */
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u64 rx_sequence_errs; /* sequence errors */
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u64 rx_runt; /* # of runt frames */
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u64 rx_jabber; /* # of jabber frames */
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u64 rx_short; /* # of short frames */
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u64 rx_too_long; /* # of oversized frames */
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u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
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u64 rx_frames_64; /* # of Rx frames in a particular range */
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u64 rx_frames_65_127;
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u64 rx_frames_128_255;
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u64 rx_frames_256_511;
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u64 rx_frames_512_1023;
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u64 rx_frames_1024_1518;
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u64 rx_frames_1519_max;
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u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
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unsigned long tx_fifo_parity_err;
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unsigned long rx_fifo_parity_err;
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unsigned long tx_fifo_urun;
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unsigned long rx_fifo_ovfl;
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unsigned long serdes_signal_loss;
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unsigned long xaui_pcs_ctc_err;
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unsigned long xaui_pcs_align_change;
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};
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struct tp_mib_stats {
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u32 ipInReceive_hi;
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u32 ipInReceive_lo;
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u32 ipInHdrErrors_hi;
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u32 ipInHdrErrors_lo;
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u32 ipInAddrErrors_hi;
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u32 ipInAddrErrors_lo;
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u32 ipInUnknownProtos_hi;
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u32 ipInUnknownProtos_lo;
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u32 ipInDiscards_hi;
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u32 ipInDiscards_lo;
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u32 ipInDelivers_hi;
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u32 ipInDelivers_lo;
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u32 ipOutRequests_hi;
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u32 ipOutRequests_lo;
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u32 ipOutDiscards_hi;
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u32 ipOutDiscards_lo;
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u32 ipOutNoRoutes_hi;
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u32 ipOutNoRoutes_lo;
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u32 ipReasmTimeout;
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u32 ipReasmReqds;
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u32 ipReasmOKs;
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u32 ipReasmFails;
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u32 reserved[8];
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u32 tcpActiveOpens;
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u32 tcpPassiveOpens;
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u32 tcpAttemptFails;
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u32 tcpEstabResets;
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u32 tcpOutRsts;
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u32 tcpCurrEstab;
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u32 tcpInSegs_hi;
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u32 tcpInSegs_lo;
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u32 tcpOutSegs_hi;
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u32 tcpOutSegs_lo;
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u32 tcpRetransSeg_hi;
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u32 tcpRetransSeg_lo;
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u32 tcpInErrs_hi;
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u32 tcpInErrs_lo;
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u32 tcpRtoMin;
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u32 tcpRtoMax;
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};
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struct tp_params {
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unsigned int nchan; /* # of channels */
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unsigned int pmrx_size; /* total PMRX capacity */
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unsigned int pmtx_size; /* total PMTX capacity */
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unsigned int cm_size; /* total CM capacity */
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unsigned int chan_rx_size; /* per channel Rx size */
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unsigned int chan_tx_size; /* per channel Tx size */
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unsigned int rx_pg_size; /* Rx page size */
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unsigned int tx_pg_size; /* Tx page size */
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unsigned int rx_num_pgs; /* # of Rx pages */
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unsigned int tx_num_pgs; /* # of Tx pages */
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unsigned int ntimer_qs; /* # of timer queues */
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};
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struct qset_params { /* SGE queue set parameters */
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unsigned int polling; /* polling/interrupt service for rspq */
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unsigned int coalesce_usecs; /* irq coalescing timer */
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unsigned int rspq_size; /* # of entries in response queue */
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unsigned int fl_size; /* # of entries in regular free list */
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unsigned int jumbo_size; /* # of entries in jumbo free list */
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unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
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unsigned int cong_thres; /* FL congestion threshold */
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};
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struct sge_params {
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unsigned int max_pkt_size; /* max offload pkt size */
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struct qset_params qset[SGE_QSETS];
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};
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struct mc5_params {
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unsigned int mode; /* selects MC5 width */
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unsigned int nservers; /* size of server region */
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unsigned int nfilters; /* size of filter region */
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unsigned int nroutes; /* size of routing region */
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};
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/* Default MC5 region sizes */
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enum {
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DEFAULT_NSERVERS = 512,
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DEFAULT_NFILTERS = 128
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};
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/* MC5 modes, these must be non-0 */
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enum {
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MC5_MODE_144_BIT = 1,
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MC5_MODE_72_BIT = 2
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};
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struct vpd_params {
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unsigned int cclk;
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unsigned int mclk;
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unsigned int uclk;
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unsigned int mdc;
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unsigned int mem_timing;
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u8 eth_base[6];
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u8 port_type[MAX_NPORTS];
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unsigned short xauicfg[2];
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};
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struct pci_params {
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unsigned int vpd_cap_addr;
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unsigned int pcie_cap_addr;
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unsigned short speed;
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unsigned char width;
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unsigned char variant;
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};
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enum {
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PCI_VARIANT_PCI,
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PCI_VARIANT_PCIX_MODE1_PARITY,
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PCI_VARIANT_PCIX_MODE1_ECC,
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PCI_VARIANT_PCIX_266_MODE2,
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PCI_VARIANT_PCIE
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};
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struct adapter_params {
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|
|
struct sge_params sge;
|
||
|
|
struct mc5_params mc5;
|
||
|
|
struct tp_params tp;
|
||
|
|
struct vpd_params vpd;
|
||
|
|
struct pci_params pci;
|
||
|
|
|
||
|
|
const struct adapter_info *info;
|
||
|
|
|
||
|
|
unsigned short mtus[NMTUS];
|
||
|
|
unsigned short a_wnd[NCCTRL_WIN];
|
||
|
|
unsigned short b_wnd[NCCTRL_WIN];
|
||
|
|
|
||
|
|
unsigned int nports; /* # of ethernet ports */
|
||
|
|
unsigned int stats_update_period; /* MAC stats accumulation period */
|
||
|
|
unsigned int linkpoll_period; /* link poll period in 0.1s */
|
||
|
|
unsigned int rev; /* chip revision */
|
||
|
|
};
|
||
|
|
|
||
|
|
struct trace_params {
|
||
|
|
u32 sip;
|
||
|
|
u32 sip_mask;
|
||
|
|
u32 dip;
|
||
|
|
u32 dip_mask;
|
||
|
|
u16 sport;
|
||
|
|
u16 sport_mask;
|
||
|
|
u16 dport;
|
||
|
|
u16 dport_mask;
|
||
|
|
u32 vlan:12;
|
||
|
|
u32 vlan_mask:12;
|
||
|
|
u32 intf:4;
|
||
|
|
u32 intf_mask:4;
|
||
|
|
u8 proto;
|
||
|
|
u8 proto_mask;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct link_config {
|
||
|
|
unsigned int supported; /* link capabilities */
|
||
|
|
unsigned int advertising; /* advertised capabilities */
|
||
|
|
unsigned short requested_speed; /* speed user has requested */
|
||
|
|
unsigned short speed; /* actual link speed */
|
||
|
|
unsigned char requested_duplex; /* duplex user has requested */
|
||
|
|
unsigned char duplex; /* actual link duplex */
|
||
|
|
unsigned char requested_fc; /* flow control user has requested */
|
||
|
|
unsigned char fc; /* actual link flow control */
|
||
|
|
unsigned char autoneg; /* autonegotiating? */
|
||
|
|
unsigned int link_ok; /* link up? */
|
||
|
|
};
|
||
|
|
|
||
|
|
#define SPEED_INVALID 0xffff
|
||
|
|
#define DUPLEX_INVALID 0xff
|
||
|
|
|
||
|
|
struct mc5 {
|
||
|
|
struct adapter *adapter;
|
||
|
|
unsigned int tcam_size;
|
||
|
|
unsigned char part_type;
|
||
|
|
unsigned char parity_enabled;
|
||
|
|
unsigned char mode;
|
||
|
|
struct mc5_stats stats;
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline unsigned int t3_mc5_size(const struct mc5 *p)
|
||
|
|
{
|
||
|
|
return p->tcam_size;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct mc7 {
|
||
|
|
struct adapter *adapter; /* backpointer to adapter */
|
||
|
|
unsigned int size; /* memory size in bytes */
|
||
|
|
unsigned int width; /* MC7 interface width */
|
||
|
|
unsigned int offset; /* register address offset for MC7 instance */
|
||
|
|
const char *name; /* name of MC7 instance */
|
||
|
|
struct mc7_stats stats; /* MC7 statistics */
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline unsigned int t3_mc7_size(const struct mc7 *p)
|
||
|
|
{
|
||
|
|
return p->size;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct cmac {
|
||
|
|
struct adapter *adapter;
|
||
|
|
unsigned int offset;
|
||
|
|
unsigned int nucast; /* # of address filters for unicast MACs */
|
||
|
|
struct mac_stats stats;
|
||
|
|
};
|
||
|
|
|
||
|
|
enum {
|
||
|
|
MAC_DIRECTION_RX = 1,
|
||
|
|
MAC_DIRECTION_TX = 2,
|
||
|
|
MAC_RXFIFO_SIZE = 32768
|
||
|
|
};
|
||
|
|
|
||
|
|
/* IEEE 802.3ae specified MDIO devices */
|
||
|
|
enum {
|
||
|
|
MDIO_DEV_PMA_PMD = 1,
|
||
|
|
MDIO_DEV_WIS = 2,
|
||
|
|
MDIO_DEV_PCS = 3,
|
||
|
|
MDIO_DEV_XGXS = 4
|
||
|
|
};
|
||
|
|
|
||
|
|
/* PHY loopback direction */
|
||
|
|
enum {
|
||
|
|
PHY_LOOPBACK_TX = 1,
|
||
|
|
PHY_LOOPBACK_RX = 2
|
||
|
|
};
|
||
|
|
|
||
|
|
/* PHY interrupt types */
|
||
|
|
enum {
|
||
|
|
cphy_cause_link_change = 1,
|
||
|
|
cphy_cause_fifo_error = 2
|
||
|
|
};
|
||
|
|
|
||
|
|
/* PHY operations */
|
||
|
|
struct cphy_ops {
|
||
|
|
void (*destroy)(struct cphy *phy);
|
||
|
|
int (*reset)(struct cphy *phy, int wait);
|
||
|
|
|
||
|
|
int (*intr_enable)(struct cphy *phy);
|
||
|
|
int (*intr_disable)(struct cphy *phy);
|
||
|
|
int (*intr_clear)(struct cphy *phy);
|
||
|
|
int (*intr_handler)(struct cphy *phy);
|
||
|
|
|
||
|
|
int (*autoneg_enable)(struct cphy *phy);
|
||
|
|
int (*autoneg_restart)(struct cphy *phy);
|
||
|
|
|
||
|
|
int (*advertise)(struct cphy *phy, unsigned int advertise_map);
|
||
|
|
int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
|
||
|
|
int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
|
||
|
|
int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
|
||
|
|
int *duplex, int *fc);
|
||
|
|
int (*power_down)(struct cphy *phy, int enable);
|
||
|
|
};
|
||
|
|
|
||
|
|
/* A PHY instance */
|
||
|
|
struct cphy {
|
||
|
|
int addr; /* PHY address */
|
||
|
|
struct adapter *adapter; /* associated adapter */
|
||
|
|
unsigned long fifo_errors; /* FIFO over/under-flows */
|
||
|
|
const struct cphy_ops *ops; /* PHY operations */
|
||
|
|
int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr,
|
||
|
|
int reg_addr, unsigned int *val);
|
||
|
|
int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr,
|
||
|
|
int reg_addr, unsigned int val);
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Convenience MDIO read/write wrappers */
|
||
|
|
static inline int mdio_read(struct cphy *phy, int mmd, int reg,
|
||
|
|
unsigned int *valp)
|
||
|
|
{
|
||
|
|
return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int mdio_write(struct cphy *phy, int mmd, int reg,
|
||
|
|
unsigned int val)
|
||
|
|
{
|
||
|
|
return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Convenience initializer */
|
||
|
|
static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
|
||
|
|
int phy_addr, struct cphy_ops *phy_ops,
|
||
|
|
const struct mdio_ops *mdio_ops)
|
||
|
|
{
|
||
|
|
phy->adapter = adapter;
|
||
|
|
phy->addr = phy_addr;
|
||
|
|
phy->ops = phy_ops;
|
||
|
|
if (mdio_ops) {
|
||
|
|
phy->mdio_read = mdio_ops->read;
|
||
|
|
phy->mdio_write = mdio_ops->write;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
|
||
|
|
#define MAC_STATS_ACCUM_SECS 180
|
||
|
|
|
||
|
|
#define XGM_REG(reg_addr, idx) \
|
||
|
|
((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
|
||
|
|
|
||
|
|
struct addr_val_pair {
|
||
|
|
unsigned int reg_addr;
|
||
|
|
unsigned int val;
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "adapter.h"
|
||
|
|
|
||
|
|
#ifndef PCI_VENDOR_ID_CHELSIO
|
||
|
|
# define PCI_VENDOR_ID_CHELSIO 0x1425
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define for_each_port(adapter, iter) \
|
||
|
|
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
||
|
|
|
||
|
|
#define adapter_info(adap) ((adap)->params.info)
|
||
|
|
|
||
|
|
static inline int uses_xaui(const struct adapter *adap)
|
||
|
|
{
|
||
|
|
return adapter_info(adap)->caps & SUPPORTED_AUI;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int is_10G(const struct adapter *adap)
|
||
|
|
{
|
||
|
|
return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int is_offload(const struct adapter *adap)
|
||
|
|
{
|
||
|
|
return adapter_info(adap)->caps & SUPPORTED_OFFLOAD;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
|
||
|
|
{
|
||
|
|
return adap->params.vpd.cclk / 1000;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int is_pcie(const struct adapter *adap)
|
||
|
|
{
|
||
|
|
return adap->params.pci.variant == PCI_VARIANT_PCIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
|
||
|
|
u32 val);
|
||
|
|
void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
|
||
|
|
int n, unsigned int offset);
|
||
|
|
int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
|
||
|
|
int polarity, int attempts, int delay, u32 *valp);
|
||
|
|
static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
|
||
|
|
int polarity, int attempts, int delay)
|
||
|
|
{
|
||
|
|
return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
|
||
|
|
delay, NULL);
|
||
|
|
}
|
||
|
|
int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
|
||
|
|
unsigned int set);
|
||
|
|
int t3_phy_reset(struct cphy *phy, int mmd, int wait);
|
||
|
|
int t3_phy_advertise(struct cphy *phy, unsigned int advert);
|
||
|
|
int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
|
||
|
|
|
||
|
|
void t3_intr_enable(struct adapter *adapter);
|
||
|
|
void t3_intr_disable(struct adapter *adapter);
|
||
|
|
void t3_intr_clear(struct adapter *adapter);
|
||
|
|
void t3_port_intr_enable(struct adapter *adapter, int idx);
|
||
|
|
void t3_port_intr_disable(struct adapter *adapter, int idx);
|
||
|
|
void t3_port_intr_clear(struct adapter *adapter, int idx);
|
||
|
|
int t3_slow_intr_handler(struct adapter *adapter);
|
||
|
|
int t3_phy_intr_handler(struct adapter *adapter);
|
||
|
|
|
||
|
|
void t3_link_changed(struct adapter *adapter, int port_id);
|
||
|
|
int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
|
||
|
|
const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
|
||
|
|
int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
|
||
|
|
int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
|
||
|
|
int t3_seeprom_wp(struct adapter *adapter, int enable);
|
||
|
|
int t3_read_flash(struct adapter *adapter, unsigned int addr,
|
||
|
|
unsigned int nwords, u32 *data, int byte_oriented);
|
||
|
|
int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
|
||
|
|
int t3_get_fw_version(struct adapter *adapter, u32 *vers);
|
||
|
|
int t3_check_fw_version(struct adapter *adapter);
|
||
|
|
int t3_init_hw(struct adapter *adapter, u32 fw_params);
|
||
|
|
void mac_prep(struct cmac *mac, struct adapter *adapter, int index);
|
||
|
|
void early_hw_init(struct adapter *adapter, const struct adapter_info *ai);
|
||
|
|
int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
|
||
|
|
int reset);
|
||
|
|
void t3_led_ready(struct adapter *adapter);
|
||
|
|
void t3_fatal_err(struct adapter *adapter);
|
||
|
|
void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
|
||
|
|
void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
|
||
|
|
const u8 * cpus, const u16 *rspq);
|
||
|
|
int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map);
|
||
|
|
int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
|
||
|
|
int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
|
||
|
|
unsigned int n, unsigned int *valp);
|
||
|
|
int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
|
||
|
|
u64 *buf);
|
||
|
|
|
||
|
|
int t3_mac_reset(struct cmac *mac);
|
||
|
|
void t3b_pcs_reset(struct cmac *mac);
|
||
|
|
int t3_mac_enable(struct cmac *mac, int which);
|
||
|
|
int t3_mac_disable(struct cmac *mac, int which);
|
||
|
|
int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
|
||
|
|
int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
|
||
|
|
int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
|
||
|
|
int t3_mac_set_num_ucast(struct cmac *mac, int n);
|
||
|
|
const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
|
||
|
|
int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
|
||
|
|
|
||
|
|
void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
|
||
|
|
int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
|
||
|
|
unsigned int nroutes);
|
||
|
|
void t3_mc5_intr_handler(struct mc5 *mc5);
|
||
|
|
int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
|
||
|
|
u32 *buf);
|
||
|
|
|
||
|
|
int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh);
|
||
|
|
void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size);
|
||
|
|
void t3_tp_set_offload_mode(struct adapter *adap, int enable);
|
||
|
|
void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
|
||
|
|
void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
|
||
|
|
unsigned short alpha[NCCTRL_WIN],
|
||
|
|
unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
|
||
|
|
void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]);
|
||
|
|
void t3_get_cong_cntl_tab(struct adapter *adap,
|
||
|
|
unsigned short incr[NMTUS][NCCTRL_WIN]);
|
||
|
|
void t3_config_trace_filter(struct adapter *adapter,
|
||
|
|
const struct trace_params *tp, int filter_index,
|
||
|
|
int invert, int enable);
|
||
|
|
int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
|
||
|
|
|
||
|
|
void t3_sge_prep(struct adapter *adap, struct sge_params *p);
|
||
|
|
void t3_sge_init(struct adapter *adap, struct sge_params *p);
|
||
|
|
int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
|
||
|
|
enum sge_context_type type, int respq, u64 base_addr,
|
||
|
|
unsigned int size, unsigned int token, int gen,
|
||
|
|
unsigned int cidx);
|
||
|
|
int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
|
||
|
|
int gts_enable, u64 base_addr, unsigned int size,
|
||
|
|
unsigned int esize, unsigned int cong_thres, int gen,
|
||
|
|
unsigned int cidx);
|
||
|
|
int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
|
||
|
|
int irq_vec_idx, u64 base_addr, unsigned int size,
|
||
|
|
unsigned int fl_thres, int gen, unsigned int cidx);
|
||
|
|
int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
|
||
|
|
unsigned int size, int rspq, int ovfl_mode,
|
||
|
|
unsigned int credits, unsigned int credit_thres);
|
||
|
|
int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
|
||
|
|
int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
|
||
|
|
int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
|
||
|
|
int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
|
||
|
|
int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]);
|
||
|
|
int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]);
|
||
|
|
int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]);
|
||
|
|
int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]);
|
||
|
|
int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
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unsigned int credits);
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void t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops);
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void t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops);
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void t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops);
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void t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
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const struct mdio_ops *mdio_ops);
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void t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops);
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#endif /* __CHELSIO_COMMON_H */
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