30 lines
933 B
C
30 lines
933 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_TXRX_H_
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#define _ICE_TXRX_H_
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#define ICE_DFLT_IRQ_WORK 256
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/* this enum matches hardware bits and is meant to be used by DYN_CTLN
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* registers and QINT registers or more generally anywhere in the manual
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* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
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* register but instead is a special value meaning "don't update" ITR0/1/2.
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*/
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enum ice_dyn_idx_t {
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ICE_IDX_ITR0 = 0,
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ICE_IDX_ITR1 = 1,
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ICE_IDX_ITR2 = 2,
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ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
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};
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/* indices into GLINT_ITR registers */
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#define ICE_RX_ITR ICE_IDX_ITR0
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#define ICE_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
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#define ICE_ITR_8K 0x003E
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/* apply ITR HW granularity translation to program the HW registers */
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#define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> (itr_gran))
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#endif /* _ICE_TXRX_H_ */
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