linux/include/dt-bindings/clock/gxbb-clkc.h

/*
 * GXBB clock tree IDs
 */

#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H

#define CLKID_CPUCLK		1
#define CLKID_HDMI_PLL		2
#define CLKID_FCLK_DIV2		4
#define CLKID_FCLK_DIV3		5
#define CLKID_FCLK_DIV4		6
#define CLKID_CLK81		12
#define CLKID_MPLL2		15
#define CLKID_SPI		34
#define CLKID_I2C		22
#define CLKID_SAR_ADC		23
#define CLKID_ETH		36
#define CLKID_USB0		50
#define CLKID_USB1		51
#define CLKID_USB		55
#define CLKID_HDMI_PCLK		63
#define CLKID_USB1_DDR_BRIDGE	64
#define CLKID_USB0_DDR_BRIDGE	65
#define CLKID_SANA		69
#define CLKID_GCLK_VENCI_INT0	77
#define CLKID_AO_I2C		93
#define CLKID_SD_EMMC_A		94
#define CLKID_SD_EMMC_B		95
#define CLKID_SD_EMMC_C		96
#define CLKID_SAR_ADC_CLK	97
#define CLKID_SAR_ADC_SEL	98

#endif /* __GXBB_CLKC_H */
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00			`/*`
			`* GXBB clock tree IDs`
			`*/`

			`#ifndef __GXBB_CLKC_H`
			`#define __GXBB_CLKC_H`

			`#define CLKID_CPUCLK 1`
clk: meson-gxbb: Export PWM related clocks for DT Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com 2016-08-22 12:49:37 +00:00			`#define CLKID_HDMI_PLL 2`
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-08-02 21:40:11 +00:00			`#define CLKID_FCLK_DIV2 4`
clk: meson-gxbb: Export PWM related clocks for DT Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com 2016-08-22 12:49:37 +00:00			`#define CLKID_FCLK_DIV3 5`
			`#define CLKID_FCLK_DIV4 6`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00			`#define CLKID_CLK81 12`
clk: gxbb: expose MPLL2 clock for use by DT This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-06 21:38:44 +00:00			`#define CLKID_MPLL2 15`
clk: gxbb: expose spifc clock SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-07 15:13:39 +00:00			`#define CLKID_SPI 34`
clk: gxbb: expose i2c clocks I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-14 10:06:05 +00:00			`#define CLKID_I2C 22`
clk: gxbb: add the SAR ADC clocks and expose them The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2017-01-19 14:58:20 +00:00			`#define CLKID_SAR_ADC 23`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00			`#define CLKID_ETH 36`
clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-04 21:31:46 +00:00			`#define CLKID_USB0 50`
			`#define CLKID_USB1 51`
			`#define CLKID_USB 55`
clk: meson-gxbb: Export HDMI clocks Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2017-01-17 12:08:48 +00:00			`#define CLKID_HDMI_PCLK 63`
clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-04 21:31:46 +00:00			`#define CLKID_USB1_DDR_BRIDGE 64`
			`#define CLKID_USB0_DDR_BRIDGE 65`
clk: gxbb: add the SAR ADC clocks and expose them The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2017-01-19 14:58:20 +00:00			`#define CLKID_SANA 69`
clk: meson-gxbb: Export HDMI clocks Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2017-01-17 12:08:48 +00:00			`#define CLKID_GCLK_VENCI_INT0 77`
clk: gxbb: expose i2c clocks I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2016-09-14 10:06:05 +00:00			`#define CLKID_AO_I2C 93`
clk: gxbb: add MMC gate clocks, and expose for DT Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-08-02 21:40:11 +00:00			`#define CLKID_SD_EMMC_A 94`
			`#define CLKID_SD_EMMC_B 95`
			`#define CLKID_SD_EMMC_C 96`
clk: gxbb: add the SAR ADC clocks and expose them The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> 2017-01-19 14:58:20 +00:00			`#define CLKID_SAR_ADC_CLK 97`
			`#define CLKID_SAR_ADC_SEL 98`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-23 22:44:26 +00:00
			`#endif /* __GXBB_CLKC_H */`