forked from Minki/linux
106 lines
3.9 KiB
C
106 lines
3.9 KiB
C
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/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
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#define __ASM_ARCH_MSM_IRQS_8XXX_H
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/* MSM ACPU Interrupt Numbers */
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#define INT_A9_M2A_0 0
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#define INT_A9_M2A_1 1
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#define INT_A9_M2A_2 2
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#define INT_A9_M2A_3 3
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#define INT_A9_M2A_4 4
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#define INT_A9_M2A_5 5
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#define INT_A9_M2A_6 6
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#define INT_GP_TIMER_EXP 7
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#define INT_DEBUG_TIMER_EXP 8
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#define INT_SIRC_0 9
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#define INT_SDC3_0 10
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#define INT_SDC3_1 11
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#define INT_SDC4_0 12
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#define INT_SDC4_1 13
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#define INT_AD6_EXT_VFR 14
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#define INT_USB_OTG 15
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#define INT_MDDI_PRI 16
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#define INT_MDDI_EXT 17
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#define INT_MDDI_CLIENT 18
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#define INT_MDP 19
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#define INT_GRAPHICS 20
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#define INT_ADM_AARM 21
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#define INT_ADSP_A11 22
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#define INT_ADSP_A9_A11 23
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#define INT_SDC1_0 24
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#define INT_SDC1_1 25
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#define INT_SDC2_0 26
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#define INT_SDC2_1 27
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#define INT_KEYSENSE 28
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#define INT_TCHSCRN_SSBI 29
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#define INT_TCHSCRN1 30
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#define INT_TCHSCRN2 31
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#define INT_TCSR_MPRPH_SC1 (32 + 0)
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#define INT_USB_FS2 (32 + 1)
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#define INT_PWB_I2C (32 + 2)
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#define INT_SOFTRESET (32 + 3)
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#define INT_NAND_WR_ER_DONE (32 + 4)
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#define INT_NAND_OP_DONE (32 + 5)
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#define INT_TCSR_MPRPH_SC2 (32 + 6)
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#define INT_OP_PEN (32 + 7)
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#define INT_AD_HSSD (32 + 8)
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#define INT_ARM11_PM (32 + 9)
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#define INT_SDMA_NON_SECURE (32 + 10)
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#define INT_TSIF_IRQ (32 + 11)
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#define INT_UART1DM_IRQ (32 + 12)
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#define INT_UART1DM_RX (32 + 13)
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#define INT_SDMA_SECURE (32 + 14)
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#define INT_SI2S_SLAVE (32 + 15)
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#define INT_SC_I2CPU (32 + 16)
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#define INT_SC_DBG_RDTRFULL (32 + 17)
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#define INT_SC_DBG_WDTRFULL (32 + 18)
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#define INT_SCPLL_CTL_DONE (32 + 19)
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#define INT_UART2DM_IRQ (32 + 20)
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#define INT_UART2DM_RX (32 + 21)
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#define INT_VDC_MEC (32 + 22)
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#define INT_VDC_DB (32 + 23)
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#define INT_VDC_AXI (32 + 24)
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#define INT_VFE (32 + 25)
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#define INT_USB_HS (32 + 26)
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#define INT_AUDIO_OUT0 (32 + 27)
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#define INT_AUDIO_OUT1 (32 + 28)
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#define INT_CRYPTO (32 + 29)
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#define INT_AD6M_IDLE (32 + 30)
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#define INT_SIRC_1 (32 + 31)
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#define NR_GPIO_IRQS 165
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#define NR_MSM_IRQS 64
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#define NR_BOARD_IRQS 64
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#endif
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