arch/arm/include/asm/hardware/cache-tauros2.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * arch/arm/include/asm/hardware/cache-tauros2.h
 *
 * Copyright (C) 2008 Marvell Semiconductor
 */

#define CACHE_TAUROS2_PREFETCH_ON	(1 << 0)
#define CACHE_TAUROS2_LINEFILL_BURST8	(1 << 1)

extern void __init tauros2_init(unsigned int features);
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1) Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2022-06-07 16:11:14 +02:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> 2009-11-24 19:33:52 +02:00			`/*`
			`* arch/arm/include/asm/hardware/cache-tauros2.h`
			`*`
			`* Copyright (C) 2008 Marvell Semiconductor`
			`*/`

ARM: cache: add extra feature enable for tauros2 The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> 2012-07-31 14:13:12 +08:00			`#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)`
			`#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)`

			`extern void __init tauros2_init(unsigned int features);`