2006-08-29 22:12:40 +00:00
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/*
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* pata_opti.c - ATI PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Based on
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* linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002
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*
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* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
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*
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* Authors:
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* Jaromir Koutek <miri@punknet.cz>,
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* Jan Harkes <jaharkes@cwi.nl>,
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* Mark Lord <mlord@pobox.com>
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* Some parts of code are from ali14xx.c and from rz1000.c.
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*
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* Also consulted the FreeBSD prototype driver by Kevin Day to try
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* and resolve some confusions. Further documentation can be found in
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* Ralf Brown's interrupt list
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*
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* If you have other variants of the Opti range (Viper/Vendetta) please
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* try this driver with those PCI idents and report back. For the later
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* chips see the pata_optidma driver
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_opti"
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2007-03-09 12:24:15 +00:00
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#define DRV_VERSION "0.2.9"
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2006-08-29 22:12:40 +00:00
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enum {
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READ_REG = 0, /* index of Read cycle timing register */
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WRITE_REG = 1, /* index of Write cycle timing register */
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CNTRL_REG = 3, /* index of Control register */
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STRAP_REG = 5, /* index of Strap register */
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MISC_REG = 6 /* index of Miscellaneous register */
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};
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/**
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* opti_pre_reset - probe begin
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* @ap: ATA port
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 07:50:52 +00:00
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* @deadline: deadline jiffies for the operation
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2006-08-29 22:12:40 +00:00
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*
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* Set up cable type and use generic probe init
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*/
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 07:50:52 +00:00
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static int opti_pre_reset(struct ata_port *ap, unsigned long deadline)
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2006-08-29 22:12:40 +00:00
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const struct pci_bits opti_enable_bits[] = {
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{ 0x45, 1, 0x80, 0x00 },
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{ 0x40, 1, 0x08, 0x00 }
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};
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2006-09-26 16:53:38 +00:00
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if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no]))
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return -ENOENT;
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 07:50:52 +00:00
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return ata_std_prereset(ap, deadline);
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2006-08-29 22:12:40 +00:00
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}
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/**
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* opti_probe_reset - probe reset
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* @ap: ATA port
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*
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* Perform the ATA probe and bus reset sequence plus specific handling
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* for this hardware. The Opti needs little handling - we have no UDMA66
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* capability that needs cable detection. All we must do is check the port
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* is enabled.
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*/
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static void opti_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, opti_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* opti_write_reg - control register setup
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* @ap: ATA port
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* @value: value
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* @reg: control register number
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*
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* The Opti uses magic 'trapdoor' register accesses to do configuration
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* rather than using PCI space as other controllers do. The double inw
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* on the error register activates configuration mode. We can then write
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* the control register
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*/
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static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
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{
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2007-02-01 06:06:36 +00:00
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void __iomem *regio = ap->ioaddr.cmd_addr;
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2006-08-29 22:12:40 +00:00
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/* These 3 unlock the control register access */
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2007-02-01 06:06:36 +00:00
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ioread16(regio + 1);
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ioread16(regio + 1);
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iowrite8(3, regio + 2);
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2006-08-29 22:12:40 +00:00
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/* Do the I/O */
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2007-02-01 06:06:36 +00:00
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iowrite8(val, regio + reg);
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2006-08-29 22:12:40 +00:00
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/* Relock */
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2007-02-01 06:06:36 +00:00
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iowrite8(0x83, regio + 2);
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2006-08-29 22:12:40 +00:00
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}
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/**
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* opti_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Timing numbers are taken from
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* the FreeBSD driver then pre computed to keep the code clean. There
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* are two tables depending on the hardware clock speed.
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*/
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static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct ata_device *pair = ata_dev_pair(adev);
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int clock;
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int pio = adev->pio_mode - XFER_PIO_0;
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2007-02-01 06:06:36 +00:00
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void __iomem *regio = ap->ioaddr.cmd_addr;
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2006-08-29 22:12:40 +00:00
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u8 addr;
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/* Address table precomputed with prefetch off and a DCLK of 2 */
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static const u8 addr_timing[2][5] = {
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{ 0x30, 0x20, 0x20, 0x10, 0x10 },
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{ 0x20, 0x20, 0x10, 0x10, 0x10 }
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};
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static const u8 data_rec_timing[2][5] = {
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{ 0x6B, 0x56, 0x42, 0x32, 0x31 },
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{ 0x58, 0x44, 0x32, 0x22, 0x21 }
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};
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2007-02-01 06:06:36 +00:00
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iowrite8(0xff, regio + 5);
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clock = ioread16(regio + 5) & 1;
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2006-08-29 22:12:40 +00:00
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/*
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* As with many controllers the address setup time is shared
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* and must suit both devices if present.
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*/
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addr = addr_timing[clock][pio];
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if (pair) {
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/* Hardware constraint */
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u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0];
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if (pair_addr > addr)
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addr = pair_addr;
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}
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/* Commence primary programming sequence */
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opti_write_reg(ap, adev->devno, MISC_REG);
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opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
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opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
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opti_write_reg(ap, addr, MISC_REG);
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/* Programming sequence complete, override strapping */
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opti_write_reg(ap, 0x85, CNTRL_REG);
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}
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static struct scsi_host_template opti_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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2006-11-29 02:26:47 +00:00
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.slave_destroy = ata_scsi_slave_destroy,
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2006-08-29 22:12:40 +00:00
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations opti_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = opti_set_piomode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = opti_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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2007-03-09 12:24:15 +00:00
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.cable_detect = ata_cable_40wire,
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2006-08-29 22:12:40 +00:00
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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2006-09-27 09:41:13 +00:00
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2007-02-01 06:06:36 +00:00
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.data_xfer = ata_data_xfer,
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2006-08-29 22:12:40 +00:00
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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2007-01-26 07:27:58 +00:00
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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2006-08-29 22:12:40 +00:00
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.port_start = ata_port_start,
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};
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static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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2007-05-04 10:43:58 +00:00
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static const struct ata_port_info info = {
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2006-08-29 22:12:40 +00:00
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.sht = &opti_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.port_ops = &opti_port_ops
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};
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2007-05-04 10:43:58 +00:00
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const struct ata_port_info *ppi[] = { &info, NULL };
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2006-08-29 22:12:40 +00:00
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static int printed_version;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
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2007-05-04 10:43:58 +00:00
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return ata_pci_init_one(dev, ppi);
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2006-08-29 22:12:40 +00:00
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}
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static const struct pci_device_id opti[] = {
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2006-09-29 00:21:59 +00:00
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{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
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{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
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{ },
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2006-08-29 22:12:40 +00:00
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};
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static struct pci_driver opti_pci_driver = {
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2006-09-29 00:21:59 +00:00
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.name = DRV_NAME,
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2006-08-29 22:12:40 +00:00
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.id_table = opti,
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|
|
|
.probe = opti_init_one,
|
2006-11-22 16:57:36 +00:00
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 08:31:26 +00:00
|
|
|
#ifdef CONFIG_PM
|
2006-11-22 16:57:36 +00:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = ata_pci_device_resume,
|
2007-03-02 08:31:26 +00:00
|
|
|
#endif
|
2006-08-29 22:12:40 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init opti_init(void)
|
|
|
|
{
|
|
|
|
return pci_register_driver(&opti_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit opti_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&opti_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for Opti 621/621X");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, opti);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(opti_init);
|
|
|
|
module_exit(opti_exit);
|