458 lines
11 KiB
C
458 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 Intel Corporation */
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#include "igc_phy.h"
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/**
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* igc_check_reset_block - Check if PHY reset is blocked
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* @hw: pointer to the HW structure
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*
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* Read the PHY management control register and check whether a PHY reset
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* is blocked. If a reset is not blocked return 0, otherwise
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* return IGC_ERR_BLK_PHY_RESET (12).
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*/
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s32 igc_check_reset_block(struct igc_hw *hw)
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{
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u32 manc;
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manc = rd32(IGC_MANC);
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return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
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IGC_ERR_BLK_PHY_RESET : 0;
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}
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/**
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* igc_get_phy_id - Retrieve the PHY ID and revision
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* @hw: pointer to the HW structure
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*
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* Reads the PHY registers and stores the PHY ID and possibly the PHY
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* revision in the hardware structure.
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*/
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s32 igc_get_phy_id(struct igc_hw *hw)
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{
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struct igc_phy_info *phy = &hw->phy;
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s32 ret_val = 0;
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u16 phy_id;
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ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
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if (ret_val)
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goto out;
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phy->id = (u32)(phy_id << 16);
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usleep_range(200, 500);
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ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
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if (ret_val)
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goto out;
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phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
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phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
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out:
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return ret_val;
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}
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/**
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* igc_phy_has_link - Polls PHY for link
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* @hw: pointer to the HW structure
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* @iterations: number of times to poll for link
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* @usec_interval: delay between polling attempts
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* @success: pointer to whether polling was successful or not
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*
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* Polls the PHY status register for link, 'iterations' number of times.
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*/
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s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations,
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u32 usec_interval, bool *success)
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{
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u16 i, phy_status;
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s32 ret_val = 0;
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for (i = 0; i < iterations; i++) {
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/* Some PHYs require the PHY_STATUS register to be read
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* twice due to the link bit being sticky. No harm doing
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* it across the board.
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*/
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ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
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if (ret_val && usec_interval > 0) {
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/* If the first read fails, another entity may have
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* ownership of the resources, wait and try again to
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* see if they have relinquished the resources yet.
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*/
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if (usec_interval >= 1000)
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mdelay(usec_interval / 1000);
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else
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udelay(usec_interval);
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}
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ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
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if (ret_val)
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break;
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if (phy_status & MII_SR_LINK_STATUS)
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break;
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if (usec_interval >= 1000)
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mdelay(usec_interval / 1000);
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else
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udelay(usec_interval);
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}
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*success = (i < iterations) ? true : false;
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return ret_val;
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}
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/**
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* igc_power_up_phy_copper - Restore copper link in case of PHY power down
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* @hw: pointer to the HW structure
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*
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* In the case of a PHY power down to save power, or to turn off link during a
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* driver unload, restore the link to previous settings.
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*/
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void igc_power_up_phy_copper(struct igc_hw *hw)
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{
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u16 mii_reg = 0;
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/* The PHY will retain its settings across a power down/up cycle */
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hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
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mii_reg &= ~MII_CR_POWER_DOWN;
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hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
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}
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/**
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* igc_power_down_phy_copper - Power down copper PHY
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* @hw: pointer to the HW structure
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*
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* Power down PHY to save power when interface is down and wake on lan
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* is not enabled.
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*/
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void igc_power_down_phy_copper(struct igc_hw *hw)
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{
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u16 mii_reg = 0;
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/* The PHY will retain its settings across a power down/up cycle */
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hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
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mii_reg |= MII_CR_POWER_DOWN;
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/* Temporary workaround - should be removed when PHY will implement
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* IEEE registers as properly
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*/
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/* hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);*/
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usleep_range(1000, 2000);
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}
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/**
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* igc_check_downshift - Checks whether a downshift in speed occurred
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* @hw: pointer to the HW structure
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*
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* Success returns 0, Failure returns 1
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*
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* A downshift is detected by querying the PHY link health.
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*/
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s32 igc_check_downshift(struct igc_hw *hw)
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{
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struct igc_phy_info *phy = &hw->phy;
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u16 phy_data, offset, mask;
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s32 ret_val;
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switch (phy->type) {
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case igc_phy_i225:
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default:
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/* speed downshift not supported */
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phy->speed_downgraded = false;
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ret_val = 0;
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goto out;
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}
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ret_val = phy->ops.read_reg(hw, offset, &phy_data);
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if (!ret_val)
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phy->speed_downgraded = (phy_data & mask) ? true : false;
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out:
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return ret_val;
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}
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/**
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* igc_phy_hw_reset - PHY hardware reset
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* @hw: pointer to the HW structure
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*
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* Verify the reset block is not blocking us from resetting. Acquire
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* semaphore (if necessary) and read/set/write the device control reset
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* bit in the PHY. Wait the appropriate delay time for the device to
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* reset and release the semaphore (if necessary).
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*/
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s32 igc_phy_hw_reset(struct igc_hw *hw)
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{
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struct igc_phy_info *phy = &hw->phy;
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s32 ret_val;
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u32 ctrl;
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ret_val = igc_check_reset_block(hw);
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if (ret_val) {
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ret_val = 0;
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goto out;
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}
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ret_val = phy->ops.acquire(hw);
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if (ret_val)
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goto out;
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ctrl = rd32(IGC_CTRL);
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wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
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wrfl();
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udelay(phy->reset_delay_us);
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wr32(IGC_CTRL, ctrl);
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wrfl();
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usleep_range(1500, 2000);
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phy->ops.release(hw);
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out:
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return ret_val;
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}
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/**
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* igc_read_phy_reg_mdic - Read MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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*
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* Reads the MDI control register in the PHY at offset and stores the
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* information read to data.
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*/
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static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
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{
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struct igc_phy_info *phy = &hw->phy;
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u32 i, mdic = 0;
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s32 ret_val = 0;
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if (offset > MAX_PHY_REG_ADDRESS) {
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hw_dbg("PHY Address %d is out of range\n", offset);
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ret_val = -IGC_ERR_PARAM;
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goto out;
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}
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/* Set up Op-code, Phy Address, and register offset in the MDI
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* Control register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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mdic = ((offset << IGC_MDIC_REG_SHIFT) |
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(phy->addr << IGC_MDIC_PHY_SHIFT) |
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(IGC_MDIC_OP_READ));
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wr32(IGC_MDIC, mdic);
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/* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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* the lower time out
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*/
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for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
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usleep_range(500, 1000);
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mdic = rd32(IGC_MDIC);
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if (mdic & IGC_MDIC_READY)
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break;
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}
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if (!(mdic & IGC_MDIC_READY)) {
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hw_dbg("MDI Read did not complete\n");
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ret_val = -IGC_ERR_PHY;
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goto out;
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}
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if (mdic & IGC_MDIC_ERROR) {
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hw_dbg("MDI Error\n");
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ret_val = -IGC_ERR_PHY;
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goto out;
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}
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*data = (u16)mdic;
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out:
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return ret_val;
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}
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/**
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* igc_write_phy_reg_mdic - Write MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write to register at offset
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*
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* Writes data to MDI control register in the PHY at offset.
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*/
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static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
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{
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struct igc_phy_info *phy = &hw->phy;
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u32 i, mdic = 0;
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s32 ret_val = 0;
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if (offset > MAX_PHY_REG_ADDRESS) {
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hw_dbg("PHY Address %d is out of range\n", offset);
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ret_val = -IGC_ERR_PARAM;
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goto out;
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}
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/* Set up Op-code, Phy Address, and register offset in the MDI
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* Control register. The MAC will take care of interfacing with the
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* PHY to write the desired data.
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*/
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mdic = (((u32)data) |
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(offset << IGC_MDIC_REG_SHIFT) |
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(phy->addr << IGC_MDIC_PHY_SHIFT) |
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(IGC_MDIC_OP_WRITE));
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wr32(IGC_MDIC, mdic);
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/* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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* the lower time out
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*/
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for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
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usleep_range(500, 1000);
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mdic = rd32(IGC_MDIC);
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if (mdic & IGC_MDIC_READY)
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break;
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}
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if (!(mdic & IGC_MDIC_READY)) {
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hw_dbg("MDI Write did not complete\n");
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ret_val = -IGC_ERR_PHY;
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goto out;
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}
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if (mdic & IGC_MDIC_ERROR) {
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hw_dbg("MDI Error\n");
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ret_val = -IGC_ERR_PHY;
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goto out;
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}
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out:
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return ret_val;
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}
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/**
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* __igc_access_xmdio_reg - Read/write XMDIO register
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* @hw: pointer to the HW structure
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* @address: XMDIO address to program
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* @dev_addr: device address to program
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* @data: pointer to value to read/write from/to the XMDIO address
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* @read: boolean flag to indicate read or write
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*/
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static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
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u8 dev_addr, u16 *data, bool read)
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{
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s32 ret_val;
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ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
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if (ret_val)
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return ret_val;
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ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
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if (ret_val)
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return ret_val;
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ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
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dev_addr);
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if (ret_val)
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return ret_val;
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if (read)
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ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
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else
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ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
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if (ret_val)
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return ret_val;
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/* Recalibrate the device back to 0 */
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ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
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if (ret_val)
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return ret_val;
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return ret_val;
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}
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/**
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* igc_read_xmdio_reg - Read XMDIO register
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* @hw: pointer to the HW structure
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* @addr: XMDIO address to program
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* @dev_addr: device address to program
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* @data: value to be read from the EMI address
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*/
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static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr,
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u8 dev_addr, u16 *data)
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{
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return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
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}
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/**
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* igc_write_xmdio_reg - Write XMDIO register
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* @hw: pointer to the HW structure
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* @addr: XMDIO address to program
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* @dev_addr: device address to program
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* @data: value to be written to the XMDIO address
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*/
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static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr,
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u8 dev_addr, u16 data)
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{
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return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
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}
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/**
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* igc_write_phy_reg_gpy - Write GPY PHY register
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write at register offset
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*
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* Acquires semaphore, if necessary, then writes the data to PHY register
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* at the offset. Release any acquired semaphores before exiting.
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*/
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s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
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{
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u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
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s32 ret_val;
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offset = offset & GPY_REG_MASK;
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if (!dev_addr) {
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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ret_val = igc_write_phy_reg_mdic(hw, offset, data);
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if (ret_val)
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return ret_val;
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hw->phy.ops.release(hw);
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} else {
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ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
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data);
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}
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return ret_val;
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}
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|
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|
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|
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/**
|
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|
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* igc_read_phy_reg_gpy - Read GPY PHY register
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* @hw: pointer to the HW structure
|
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|
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* @offset: lower half is register offset to read to
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|
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* upper half is MMD to use.
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|
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* @data: data to read at register offset
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|
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*
|
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|
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* Acquires semaphore, if necessary, then reads the data in the PHY register
|
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|
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* at the offset. Release any acquired semaphores before exiting.
|
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|
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*/
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|
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s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
|
||
|
|
{
|
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|
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u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
|
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|
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s32 ret_val;
|
||
|
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|
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|
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offset = offset & GPY_REG_MASK;
|
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|
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|
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|
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if (!dev_addr) {
|
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|
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ret_val = hw->phy.ops.acquire(hw);
|
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|
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if (ret_val)
|
||
|
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return ret_val;
|
||
|
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ret_val = igc_read_phy_reg_mdic(hw, offset, data);
|
||
|
|
if (ret_val)
|
||
|
|
return ret_val;
|
||
|
|
hw->phy.ops.release(hw);
|
||
|
|
} else {
|
||
|
|
ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
|
||
|
|
data);
|
||
|
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}
|
||
|
|
|
||
|
|
return ret_val;
|
||
|
|
}
|