2008-07-18 04:55:51 +00:00
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#ifndef __SPARC64_MMU_CONTEXT_H
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#define __SPARC64_MMU_CONTEXT_H
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/* Derived heavily from Linus's Alpha/AXP ASN code... */
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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2017-02-03 23:16:44 +00:00
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#include <linux/mm_types.h>
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2008-07-18 04:55:51 +00:00
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#include <asm/spitfire.h>
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#include <asm-generic/mm_hooks.h>
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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extern spinlock_t ctx_alloc_lock;
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extern unsigned long tlb_context_cache;
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extern unsigned long mmu_context_bmap[];
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2017-05-31 15:25:23 +00:00
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DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
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2014-05-16 21:25:50 +00:00
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void get_new_mmu_context(struct mm_struct *mm);
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int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void destroy_context(struct mm_struct *mm);
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2008-07-18 04:55:51 +00:00
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2014-05-16 21:25:50 +00:00
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void __tsb_context_switch(unsigned long pgd_pa,
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struct tsb_config *tsb_base,
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struct tsb_config *tsb_huge,
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sparc64: Prevent perf from running during super critical sections
This fixes another cause of random segfaults and bus errors that may
occur while running perf with the callgraph option.
Critical sections beginning with spin_lock_irqsave() raise the interrupt
level to PIL_NORMAL_MAX (14) and intentionally do not block performance
counter interrupts, which arrive at PIL_NMI (15).
But some sections of code are "super critical" with respect to perf
because the perf_callchain_user() path accesses user space and may cause
TLB activity as well as faults as it unwinds the user stack.
One particular critical section occurs in switch_mm:
spin_lock_irqsave(&mm->context.lock, flags);
...
load_secondary_context(mm);
tsb_context_switch(mm);
...
spin_unlock_irqrestore(&mm->context.lock, flags);
If a perf interrupt arrives in between load_secondary_context() and
tsb_context_switch(), then perf_callchain_user() could execute with
the context ID of one process, but with an active TSB for a different
process. When the user stack is accessed, it is very likely to
incur a TLB miss, since the h/w context ID has been changed. The TLB
will then be reloaded with a translation from the TSB for one process,
but using a context ID for another process. This exposes memory from
one process to another, and since it is a mapping for stack memory,
this usually causes the new process to crash quickly.
This super critical section needs more protection than is provided
by spin_lock_irqsave() since perf interrupts must not be allowed in.
Since __tsb_context_switch already goes through the trouble of
disabling interrupts completely, we fix this by moving the secondary
context load down into this better protected region.
Orabug: 25577560
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-17 15:22:27 +00:00
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unsigned long tsb_descr_pa,
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unsigned long secondary_ctx);
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2008-07-18 04:55:51 +00:00
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sparc64: Prevent perf from running during super critical sections
This fixes another cause of random segfaults and bus errors that may
occur while running perf with the callgraph option.
Critical sections beginning with spin_lock_irqsave() raise the interrupt
level to PIL_NORMAL_MAX (14) and intentionally do not block performance
counter interrupts, which arrive at PIL_NMI (15).
But some sections of code are "super critical" with respect to perf
because the perf_callchain_user() path accesses user space and may cause
TLB activity as well as faults as it unwinds the user stack.
One particular critical section occurs in switch_mm:
spin_lock_irqsave(&mm->context.lock, flags);
...
load_secondary_context(mm);
tsb_context_switch(mm);
...
spin_unlock_irqrestore(&mm->context.lock, flags);
If a perf interrupt arrives in between load_secondary_context() and
tsb_context_switch(), then perf_callchain_user() could execute with
the context ID of one process, but with an active TSB for a different
process. When the user stack is accessed, it is very likely to
incur a TLB miss, since the h/w context ID has been changed. The TLB
will then be reloaded with a translation from the TSB for one process,
but using a context ID for another process. This exposes memory from
one process to another, and since it is a mapping for stack memory,
this usually causes the new process to crash quickly.
This super critical section needs more protection than is provided
by spin_lock_irqsave() since perf interrupts must not be allowed in.
Since __tsb_context_switch already goes through the trouble of
disabling interrupts completely, we fix this by moving the secondary
context load down into this better protected region.
Orabug: 25577560
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-17 15:22:27 +00:00
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static inline void tsb_context_switch_ctx(struct mm_struct *mm,
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unsigned long ctx)
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2008-07-18 04:55:51 +00:00
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{
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__tsb_context_switch(__pa(mm->pgd),
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2016-12-20 03:17:08 +00:00
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&mm->context.tsb_block[MM_TSB_BASE],
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2012-10-08 23:34:29 +00:00
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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2016-12-20 03:17:08 +00:00
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(mm->context.tsb_block[MM_TSB_HUGE].tsb ?
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&mm->context.tsb_block[MM_TSB_HUGE] :
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2008-07-18 04:55:51 +00:00
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NULL)
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#else
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NULL
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#endif
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sparc64: Prevent perf from running during super critical sections
This fixes another cause of random segfaults and bus errors that may
occur while running perf with the callgraph option.
Critical sections beginning with spin_lock_irqsave() raise the interrupt
level to PIL_NORMAL_MAX (14) and intentionally do not block performance
counter interrupts, which arrive at PIL_NMI (15).
But some sections of code are "super critical" with respect to perf
because the perf_callchain_user() path accesses user space and may cause
TLB activity as well as faults as it unwinds the user stack.
One particular critical section occurs in switch_mm:
spin_lock_irqsave(&mm->context.lock, flags);
...
load_secondary_context(mm);
tsb_context_switch(mm);
...
spin_unlock_irqrestore(&mm->context.lock, flags);
If a perf interrupt arrives in between load_secondary_context() and
tsb_context_switch(), then perf_callchain_user() could execute with
the context ID of one process, but with an active TSB for a different
process. When the user stack is accessed, it is very likely to
incur a TLB miss, since the h/w context ID has been changed. The TLB
will then be reloaded with a translation from the TSB for one process,
but using a context ID for another process. This exposes memory from
one process to another, and since it is a mapping for stack memory,
this usually causes the new process to crash quickly.
This super critical section needs more protection than is provided
by spin_lock_irqsave() since perf interrupts must not be allowed in.
Since __tsb_context_switch already goes through the trouble of
disabling interrupts completely, we fix this by moving the secondary
context load down into this better protected region.
Orabug: 25577560
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-17 15:22:27 +00:00
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, __pa(&mm->context.tsb_descr[MM_TSB_BASE]),
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ctx);
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2008-07-18 04:55:51 +00:00
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}
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sparc64: Prevent perf from running during super critical sections
This fixes another cause of random segfaults and bus errors that may
occur while running perf with the callgraph option.
Critical sections beginning with spin_lock_irqsave() raise the interrupt
level to PIL_NORMAL_MAX (14) and intentionally do not block performance
counter interrupts, which arrive at PIL_NMI (15).
But some sections of code are "super critical" with respect to perf
because the perf_callchain_user() path accesses user space and may cause
TLB activity as well as faults as it unwinds the user stack.
One particular critical section occurs in switch_mm:
spin_lock_irqsave(&mm->context.lock, flags);
...
load_secondary_context(mm);
tsb_context_switch(mm);
...
spin_unlock_irqrestore(&mm->context.lock, flags);
If a perf interrupt arrives in between load_secondary_context() and
tsb_context_switch(), then perf_callchain_user() could execute with
the context ID of one process, but with an active TSB for a different
process. When the user stack is accessed, it is very likely to
incur a TLB miss, since the h/w context ID has been changed. The TLB
will then be reloaded with a translation from the TSB for one process,
but using a context ID for another process. This exposes memory from
one process to another, and since it is a mapping for stack memory,
this usually causes the new process to crash quickly.
This super critical section needs more protection than is provided
by spin_lock_irqsave() since perf interrupts must not be allowed in.
Since __tsb_context_switch already goes through the trouble of
disabling interrupts completely, we fix this by moving the secondary
context load down into this better protected region.
Orabug: 25577560
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-17 15:22:27 +00:00
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#define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
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2014-05-16 21:25:50 +00:00
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void tsb_grow(struct mm_struct *mm,
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unsigned long tsb_index,
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unsigned long mm_rss);
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2008-07-18 04:55:51 +00:00
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#ifdef CONFIG_SMP
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2014-05-16 21:25:50 +00:00
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void smp_tsb_sync(struct mm_struct *mm);
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2008-07-18 04:55:51 +00:00
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#else
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#define smp_tsb_sync(__mm) do { } while (0)
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#endif
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/* Set MMU context in the actual hardware. */
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#define load_secondary_context(__mm) \
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__asm__ __volatile__( \
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"\n661: stxa %0, [%1] %2\n" \
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" .section .sun4v_1insn_patch, \"ax\"\n" \
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" .word 661b\n" \
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" stxa %0, [%1] %3\n" \
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" .previous\n" \
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" flush %%g6\n" \
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: /* No outputs */ \
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: "r" (CTX_HWBITS((__mm)->context)), \
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"r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
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2014-05-16 21:25:50 +00:00
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void __flush_tlb_mm(unsigned long, unsigned long);
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2008-07-18 04:55:51 +00:00
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2013-04-08 20:29:46 +00:00
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/* Switch the current MM context. */
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2008-07-18 04:55:51 +00:00
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static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
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{
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unsigned long ctx_valid, flags;
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2017-05-31 15:25:23 +00:00
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int cpu = smp_processor_id();
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2008-07-18 04:55:51 +00:00
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2017-05-31 15:25:23 +00:00
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per_cpu(per_cpu_secondary_mm, cpu) = mm;
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2008-07-18 04:55:51 +00:00
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if (unlikely(mm == &init_mm))
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return;
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spin_lock_irqsave(&mm->context.lock, flags);
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ctx_valid = CTX_VALID(mm->context);
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if (!ctx_valid)
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get_new_mmu_context(mm);
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/* We have to be extremely careful here or else we will miss
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* a TSB grow if we switch back and forth between a kernel
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* thread and an address space which has it's TSB size increased
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* on another processor.
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*
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* It is possible to play some games in order to optimize the
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* switch, but the safest thing to do is to unconditionally
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* perform the secondary context load and the TSB context switch.
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*
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* For reference the bad case is, for address space "A":
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*
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* CPU 0 CPU 1
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* run address space A
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* set cpu0's bits in cpu_vm_mask
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* switch to kernel thread, borrow
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* address space A via entry_lazy_tlb
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* run address space A
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* set cpu1's bit in cpu_vm_mask
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* flush_tlb_pending()
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* reset cpu_vm_mask to just cpu1
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* TSB grow
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* run address space A
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* context was valid, so skip
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* TSB context switch
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*
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* At that point cpu0 continues to use a stale TSB, the one from
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* before the TSB grow performed on cpu1. cpu1 did not cross-call
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* cpu0 to update it's TSB because at that point the cpu_vm_mask
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* only had cpu1 set in it.
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*/
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sparc64: Prevent perf from running during super critical sections
This fixes another cause of random segfaults and bus errors that may
occur while running perf with the callgraph option.
Critical sections beginning with spin_lock_irqsave() raise the interrupt
level to PIL_NORMAL_MAX (14) and intentionally do not block performance
counter interrupts, which arrive at PIL_NMI (15).
But some sections of code are "super critical" with respect to perf
because the perf_callchain_user() path accesses user space and may cause
TLB activity as well as faults as it unwinds the user stack.
One particular critical section occurs in switch_mm:
spin_lock_irqsave(&mm->context.lock, flags);
...
load_secondary_context(mm);
tsb_context_switch(mm);
...
spin_unlock_irqrestore(&mm->context.lock, flags);
If a perf interrupt arrives in between load_secondary_context() and
tsb_context_switch(), then perf_callchain_user() could execute with
the context ID of one process, but with an active TSB for a different
process. When the user stack is accessed, it is very likely to
incur a TLB miss, since the h/w context ID has been changed. The TLB
will then be reloaded with a translation from the TSB for one process,
but using a context ID for another process. This exposes memory from
one process to another, and since it is a mapping for stack memory,
this usually causes the new process to crash quickly.
This super critical section needs more protection than is provided
by spin_lock_irqsave() since perf interrupts must not be allowed in.
Since __tsb_context_switch already goes through the trouble of
disabling interrupts completely, we fix this by moving the secondary
context load down into this better protected region.
Orabug: 25577560
Signed-off-by: Dave Aldridge <david.j.aldridge@oracle.com>
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-17 15:22:27 +00:00
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tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
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2008-07-18 04:55:51 +00:00
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/* Any time a processor runs a context on an address space
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* for the first time, we must flush that context out of the
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* local TLB.
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*/
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2009-03-16 04:10:39 +00:00
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if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
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cpumask_set_cpu(cpu, mm_cpumask(mm));
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2008-07-18 04:55:51 +00:00
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__flush_tlb_mm(CTX_HWBITS(mm->context),
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SECONDARY_CONTEXT);
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}
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spin_unlock_irqrestore(&mm->context.lock, flags);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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2017-05-31 15:25:21 +00:00
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#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
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2008-07-18 04:55:51 +00:00
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC64_MMU_CONTEXT_H) */
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