2018-05-08 10:39:47 +00:00
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#ifndef __NV50_KMS_CORE_H__
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#define __NV50_KMS_CORE_H__
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#include "disp.h"
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#include "atom.h"
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drm/nouveau/kms/nvd9-: Add CRC support
This introduces support for CRC readback on gf119+, using the
documentation generously provided to us by Nvidia:
https://github.com/NVIDIA/open-gpu-doc/blob/master/Display-CRC/display-crc.txt
We expose all available CRC sources. SF, SOR, PIOR, and DAC are exposed
through a single set of "outp" sources: outp-active/auto for a CRC of
the scanout region, outp-complete for a CRC of both the scanout and
blanking/sync region combined, and outp-inactive for a CRC of only the
blanking/sync region. For each source, nouveau selects the appropriate
tap point based on the output path in use. We also expose an "rg"
source, which allows for capturing CRCs of the scanout raster before
it's encoded into a video signal in the output path. This tap point is
referred to as the raster generator.
Note that while there's some other neat features that can be used with
CRC capture on nvidia hardware, like capturing from two CRC sources
simultaneously, I couldn't see any usecase for them and did not
implement them.
Nvidia only allows for accessing CRCs through a shared DMA region that
we program through the core EVO/NvDisplay channel which is referred to
as the notifier context. The notifier context is limited to either 255
(for Fermi-Pascal) or 2047 (Volta+) entries to store CRCs in, and
unfortunately the hardware simply drops CRCs and reports an overflow
once all available entries in the notifier context are filled.
Since the DRM CRC API and igt-gpu-tools don't expect there to be a limit
on how many CRCs can be captured, we work around this in nouveau by
allocating two separate notifier contexts for each head instead of one.
We schedule a vblank worker ahead of time so that once we start getting
close to filling up all of the available entries in the notifier
context, we can swap the currently used notifier context out with
another pre-prepared notifier context in a manner similar to page
flipping.
Unfortunately, the hardware only allows us to this by flushing two
separate updates on the core channel: one to release the current
notifier context handle, and one to program the next notifier context's
handle. When the hardware processes the first update, the CRC for the
current frame is lost. However, the second update can be flushed
immediately without waiting for the first to complete so that CRC
generation resumes on the next frame. According to Nvidia's hardware
engineers, there isn't any cleaner way of flipping notifier contexts
that would avoid this.
Since using vblank workers to swap out the notifier context will ensure
we can usually flush both updates to hardware within the timespan of a
single frame, we can also ensure that there will only be exactly one
frame lost between the first and second update being executed by the
hardware. This gives us the guarantee that we're always correctly
matching each CRC entry with it's respective frame even after a context
flip. And since IGT will retrieve the CRC entry for a frame by waiting
until it receives a CRC for any subsequent frames, this doesn't cause an
issue with any tests and is much simpler than trying to change the
current DRM API to accommodate.
In order to facilitate testing of correct handling of this limitation,
we also expose a debugfs interface to manually control the threshold for
when we start trying to flip the notifier context. We will use this in
igt to trigger a context flip for testing purposes without needing to
wait for the notifier to completely fill up. This threshold is reset
to the default value set by nouveau after each capture, and is exposed
in a separate folder within each CRTC's debugfs directory labelled
"nv_crc".
Changes since v1:
* Forgot to finish saving crc.h before saving, whoops. This just adds
some corrections to the empty function declarations that we use if
CONFIG_DEBUG_FS isn't enabled.
Changes since v2:
* Don't check return code from debugfs_create_dir() or
debugfs_create_file() - Greg K-H
Changes since v3:
(no functional changes)
* Fix SPDX license identifiers (checkpatch)
* s/uint32_t/u32/ (checkpatch)
* Fix indenting in switch cases (checkpatch)
Changes since v4:
* Remove unneeded param changes with nv50_head_flush_clr/set
* Rebase
Changes since v5:
* Remove set but unused variable (outp) in nv50_crc_atomic_check() -
Kbuild bot
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200627194657.156514-10-lyude@redhat.com
2019-10-07 18:20:12 +00:00
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#include "crc.h"
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2020-05-11 22:41:24 +00:00
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#include <nouveau_encoder.h>
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2018-05-08 10:39:47 +00:00
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struct nv50_core {
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const struct nv50_core_func *func;
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struct nv50_dmac chan;
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2020-02-03 08:36:30 +00:00
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bool assign_windows;
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2018-05-08 10:39:47 +00:00
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};
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int nv50_core_new(struct nouveau_drm *, struct nv50_core **);
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void nv50_core_del(struct nv50_core **);
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struct nv50_core_func {
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2020-06-20 07:04:57 +00:00
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int (*init)(struct nv50_core *);
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2018-05-08 10:39:47 +00:00
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void (*ntfy_init)(struct nouveau_bo *, u32 offset);
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2020-05-11 22:41:24 +00:00
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int (*caps_init)(struct nouveau_drm *, struct nv50_disp *);
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2018-05-08 10:39:47 +00:00
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int (*ntfy_wait_done)(struct nouveau_bo *, u32 offset,
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struct nvif_device *);
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2020-06-20 07:10:46 +00:00
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int (*update)(struct nv50_core *, u32 *interlock, bool ntfy);
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2018-05-08 10:39:47 +00:00
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2020-02-03 08:36:30 +00:00
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struct {
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2020-06-20 07:12:16 +00:00
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int (*owner)(struct nv50_core *);
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2020-02-03 08:36:30 +00:00
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} wndw;
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2018-05-08 10:39:47 +00:00
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const struct nv50_head_func *head;
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drm/nouveau/kms/nvd9-: Add CRC support
This introduces support for CRC readback on gf119+, using the
documentation generously provided to us by Nvidia:
https://github.com/NVIDIA/open-gpu-doc/blob/master/Display-CRC/display-crc.txt
We expose all available CRC sources. SF, SOR, PIOR, and DAC are exposed
through a single set of "outp" sources: outp-active/auto for a CRC of
the scanout region, outp-complete for a CRC of both the scanout and
blanking/sync region combined, and outp-inactive for a CRC of only the
blanking/sync region. For each source, nouveau selects the appropriate
tap point based on the output path in use. We also expose an "rg"
source, which allows for capturing CRCs of the scanout raster before
it's encoded into a video signal in the output path. This tap point is
referred to as the raster generator.
Note that while there's some other neat features that can be used with
CRC capture on nvidia hardware, like capturing from two CRC sources
simultaneously, I couldn't see any usecase for them and did not
implement them.
Nvidia only allows for accessing CRCs through a shared DMA region that
we program through the core EVO/NvDisplay channel which is referred to
as the notifier context. The notifier context is limited to either 255
(for Fermi-Pascal) or 2047 (Volta+) entries to store CRCs in, and
unfortunately the hardware simply drops CRCs and reports an overflow
once all available entries in the notifier context are filled.
Since the DRM CRC API and igt-gpu-tools don't expect there to be a limit
on how many CRCs can be captured, we work around this in nouveau by
allocating two separate notifier contexts for each head instead of one.
We schedule a vblank worker ahead of time so that once we start getting
close to filling up all of the available entries in the notifier
context, we can swap the currently used notifier context out with
another pre-prepared notifier context in a manner similar to page
flipping.
Unfortunately, the hardware only allows us to this by flushing two
separate updates on the core channel: one to release the current
notifier context handle, and one to program the next notifier context's
handle. When the hardware processes the first update, the CRC for the
current frame is lost. However, the second update can be flushed
immediately without waiting for the first to complete so that CRC
generation resumes on the next frame. According to Nvidia's hardware
engineers, there isn't any cleaner way of flipping notifier contexts
that would avoid this.
Since using vblank workers to swap out the notifier context will ensure
we can usually flush both updates to hardware within the timespan of a
single frame, we can also ensure that there will only be exactly one
frame lost between the first and second update being executed by the
hardware. This gives us the guarantee that we're always correctly
matching each CRC entry with it's respective frame even after a context
flip. And since IGT will retrieve the CRC entry for a frame by waiting
until it receives a CRC for any subsequent frames, this doesn't cause an
issue with any tests and is much simpler than trying to change the
current DRM API to accommodate.
In order to facilitate testing of correct handling of this limitation,
we also expose a debugfs interface to manually control the threshold for
when we start trying to flip the notifier context. We will use this in
igt to trigger a context flip for testing purposes without needing to
wait for the notifier to completely fill up. This threshold is reset
to the default value set by nouveau after each capture, and is exposed
in a separate folder within each CRTC's debugfs directory labelled
"nv_crc".
Changes since v1:
* Forgot to finish saving crc.h before saving, whoops. This just adds
some corrections to the empty function declarations that we use if
CONFIG_DEBUG_FS isn't enabled.
Changes since v2:
* Don't check return code from debugfs_create_dir() or
debugfs_create_file() - Greg K-H
Changes since v3:
(no functional changes)
* Fix SPDX license identifiers (checkpatch)
* s/uint32_t/u32/ (checkpatch)
* Fix indenting in switch cases (checkpatch)
Changes since v4:
* Remove unneeded param changes with nv50_head_flush_clr/set
* Rebase
Changes since v5:
* Remove set but unused variable (outp) in nv50_crc_atomic_check() -
Kbuild bot
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200627194657.156514-10-lyude@redhat.com
2019-10-07 18:20:12 +00:00
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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const struct nv50_crc_func *crc;
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#endif
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2018-05-08 10:39:47 +00:00
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const struct nv50_outp_func {
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2020-06-20 07:20:39 +00:00
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int (*ctrl)(struct nv50_core *, int or, u32 ctrl,
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2018-05-08 10:39:47 +00:00
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struct nv50_head_atom *);
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2020-05-11 22:41:24 +00:00
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/* XXX: Only used by SORs and PIORs for now */
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void (*get_caps)(struct nv50_disp *,
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struct nouveau_encoder *, int or);
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2018-05-08 10:39:47 +00:00
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} *dac, *pior, *sor;
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};
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int core507d_new(struct nouveau_drm *, s32, struct nv50_core **);
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2018-05-08 10:39:47 +00:00
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int core507d_new_(const struct nv50_core_func *, struct nouveau_drm *, s32,
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struct nv50_core **);
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2020-06-20 07:04:57 +00:00
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int core507d_init(struct nv50_core *);
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2018-05-08 10:39:47 +00:00
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void core507d_ntfy_init(struct nouveau_bo *, u32);
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2020-09-04 20:27:58 +00:00
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int core507d_read_caps(struct nv50_disp *disp);
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2020-05-11 22:41:24 +00:00
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int core507d_caps_init(struct nouveau_drm *, struct nv50_disp *);
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2018-05-08 10:39:47 +00:00
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int core507d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *);
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2020-06-20 07:10:46 +00:00
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int core507d_update(struct nv50_core *, u32 *, bool);
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2018-05-08 10:39:47 +00:00
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2018-05-08 10:39:47 +00:00
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extern const struct nv50_outp_func dac507d;
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extern const struct nv50_outp_func sor507d;
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extern const struct nv50_outp_func pior507d;
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2018-05-08 10:39:47 +00:00
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int core827d_new(struct nouveau_drm *, s32, struct nv50_core **);
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int core907d_new(struct nouveau_drm *, s32, struct nv50_core **);
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2020-09-04 20:27:58 +00:00
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int core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp);
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2018-05-08 10:39:47 +00:00
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extern const struct nv50_outp_func dac907d;
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extern const struct nv50_outp_func sor907d;
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int core917d_new(struct nouveau_drm *, s32, struct nv50_core **);
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2018-05-08 10:39:48 +00:00
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int corec37d_new(struct nouveau_drm *, s32, struct nv50_core **);
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2020-05-11 22:41:24 +00:00
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int corec37d_caps_init(struct nouveau_drm *, struct nv50_disp *);
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2018-12-11 04:50:02 +00:00
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int corec37d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *);
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2020-06-20 07:10:46 +00:00
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int corec37d_update(struct nv50_core *, u32 *, bool);
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2020-06-20 07:12:16 +00:00
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int corec37d_wndw_owner(struct nv50_core *);
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2018-05-08 10:39:48 +00:00
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extern const struct nv50_outp_func sorc37d;
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2018-12-11 04:50:02 +00:00
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int corec57d_new(struct nouveau_drm *, s32, struct nv50_core **);
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2018-05-08 10:39:47 +00:00
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#endif
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