2012-08-14 00:04:04 +00:00
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2015-01-14 05:24:57 +00:00
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#include "nv50.h"
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2015-08-20 04:54:19 +00:00
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#include "rootnv50.h"
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2014-02-20 11:33:34 +00:00
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2012-08-14 00:04:04 +00:00
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static int
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2015-01-14 05:24:57 +00:00
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gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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2012-08-14 00:04:04 +00:00
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{
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2015-08-20 04:54:07 +00:00
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struct nv50_disp *disp;
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2012-08-14 00:04:04 +00:00
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int ret;
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2015-01-14 05:24:57 +00:00
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ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
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2015-08-20 04:54:07 +00:00
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"display", &disp);
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*pobject = nv_object(disp);
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2012-08-14 00:04:04 +00:00
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if (ret)
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return ret;
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2015-08-20 04:54:07 +00:00
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
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2014-08-11 04:38:10 +00:00
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if (ret)
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return ret;
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2015-08-20 04:54:19 +00:00
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nv_engine(disp)->sclass = gt215_disp_root_oclass;
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2015-08-20 04:54:07 +00:00
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nv_engine(disp)->cclass = &nv50_disp_cclass;
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nv_subdev(disp)->intr = nv50_disp_intr;
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INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
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disp->sclass = gt215_disp_sclass;
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disp->head.nr = 2;
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disp->dac.nr = 3;
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disp->sor.nr = 4;
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disp->pior.nr = 3;
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disp->dac.power = nv50_dac_power;
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disp->dac.sense = nv50_dac_sense;
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disp->sor.power = nv50_sor_power;
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disp->sor.hda_eld = gt215_hda_eld;
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disp->sor.hdmi = gt215_hdmi_ctrl;
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disp->pior.power = nv50_pior_power;
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2012-08-14 00:04:04 +00:00
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return 0;
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}
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2015-01-14 05:24:57 +00:00
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struct nvkm_oclass *
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gt215_disp_oclass = &(struct nv50_disp_impl) {
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2014-02-20 11:33:34 +00:00
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.base.base.handle = NV_ENGINE(DISP, 0x85),
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2015-01-14 05:24:57 +00:00
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.base.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gt215_disp_ctor,
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.dtor = _nvkm_disp_dtor,
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.init = _nvkm_disp_init,
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.fini = _nvkm_disp_fini,
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2012-08-14 00:04:04 +00:00
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},
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2015-08-20 04:54:15 +00:00
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.base.outp.internal.crt = nv50_dac_output_new,
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.base.outp.internal.tmds = nv50_sor_output_new,
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.base.outp.internal.lvds = nv50_sor_output_new,
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.base.outp.internal.dp = g94_sor_dp_new,
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.base.outp.external.lvds = nv50_pior_output_new,
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.base.outp.external.dp = nv50_pior_dp_new,
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2014-08-09 18:10:20 +00:00
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.base.vblank = &nv50_disp_vblank_func,
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2015-01-14 05:24:57 +00:00
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.mthd.core = &g94_disp_core_mthd_chan,
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.mthd.base = &g84_disp_base_mthd_chan,
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.mthd.ovly = &g84_disp_ovly_mthd_chan,
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2014-02-20 05:14:10 +00:00
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.mthd.prev = 0x000004,
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2015-08-20 04:54:19 +00:00
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.head.scanoutpos = nv50_disp_root_scanoutpos,
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2014-02-20 11:33:34 +00:00
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}.base.base;
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