2007-04-27 01:53:52 +00:00
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#ifndef _ASM_POWERPC_MMU_HASH64_H_
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#define _ASM_POWERPC_MMU_HASH64_H_
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/*
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* PowerPC64 memory management structures
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*
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* Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
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* PPC64 rework.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/asm-compat.h>
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#include <asm/page.h>
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/*
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* Segment table
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*/
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#define STE_ESID_V 0x80
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#define STE_ESID_KS 0x20
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#define STE_ESID_KP 0x10
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#define STE_ESID_N 0x08
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#define STE_VSID_SHIFT 12
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/* Location of cpu0's segment table */
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2011-03-06 18:09:07 +00:00
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#define STAB0_PAGE 0x8
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2007-04-27 01:53:52 +00:00
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#define STAB0_OFFSET (STAB0_PAGE << 12)
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#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
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#ifndef __ASSEMBLY__
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extern char initial_stab[];
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#endif /* ! __ASSEMBLY */
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/*
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* SLB
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*/
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#define SLB_NUM_BOLTED 3
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#define SLB_CACHE_ENTRIES 8
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2009-08-28 12:06:29 +00:00
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#define SLB_MIN_SIZE 32
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2007-04-27 01:53:52 +00:00
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/* Bits in the SLB ESID word */
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#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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2007-10-11 10:37:10 +00:00
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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2007-04-27 01:53:52 +00:00
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#define SLB_VSID_B ASM_CONST(0xc000000000000000)
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#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
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#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
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#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
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#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
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#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
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#define SLB_VSID_L ASM_CONST(0x0000000000000100)
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#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
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#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
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#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
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#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
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#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
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#define SLB_VSID_KERNEL (SLB_VSID_KP)
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#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
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#define SLBIE_C (0x08000000)
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2007-10-11 10:37:10 +00:00
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#define SLBIE_SSIZE_SHIFT 25
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2007-04-27 01:53:52 +00:00
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/*
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* Hash table
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*/
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#define HPTES_PER_GROUP 8
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2007-05-10 05:28:44 +00:00
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#define HPTE_V_SSIZE_SHIFT 62
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2007-04-27 01:53:52 +00:00
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#define HPTE_V_AVPN_SHIFT 7
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2007-05-10 05:28:44 +00:00
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#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
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2007-04-27 01:53:52 +00:00
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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2007-11-26 16:24:43 +00:00
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#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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2007-04-27 01:53:52 +00:00
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#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
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#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
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#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
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#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
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#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
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#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
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#define HPTE_R_TS ASM_CONST(0x4000000000000000)
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
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2007-04-27 01:53:52 +00:00
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#define HPTE_R_RPN_SHIFT 12
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
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2007-04-27 01:53:52 +00:00
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#define HPTE_R_PP ASM_CONST(0x0000000000000003)
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#define HPTE_R_N ASM_CONST(0x0000000000000004)
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_G ASM_CONST(0x0000000000000008)
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#define HPTE_R_M ASM_CONST(0x0000000000000010)
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#define HPTE_R_I ASM_CONST(0x0000000000000020)
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#define HPTE_R_W ASM_CONST(0x0000000000000040)
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#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
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2007-04-27 01:53:52 +00:00
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#define HPTE_R_C ASM_CONST(0x0000000000000080)
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#define HPTE_R_R ASM_CONST(0x0000000000000100)
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KVM: PPC: Add support for Book3S processors in hypervisor mode
This adds support for KVM running on 64-bit Book 3S processors,
specifically POWER7, in hypervisor mode. Using hypervisor mode means
that the guest can use the processor's supervisor mode. That means
that the guest can execute privileged instructions and access privileged
registers itself without trapping to the host. This gives excellent
performance, but does mean that KVM cannot emulate a processor
architecture other than the one that the hardware implements.
This code assumes that the guest is running paravirtualized using the
PAPR (Power Architecture Platform Requirements) interface, which is the
interface that IBM's PowerVM hypervisor uses. That means that existing
Linux distributions that run on IBM pSeries machines will also run
under KVM without modification. In order to communicate the PAPR
hypercalls to qemu, this adds a new KVM_EXIT_PAPR_HCALL exit code
to include/linux/kvm.h.
Currently the choice between book3s_hv support and book3s_pr support
(i.e. the existing code, which runs the guest in user mode) has to be
made at kernel configuration time, so a given kernel binary can only
do one or the other.
This new book3s_hv code doesn't support MMIO emulation at present.
Since we are running paravirtualized guests, this isn't a serious
restriction.
With the guest running in supervisor mode, most exceptions go straight
to the guest. We will never get data or instruction storage or segment
interrupts, alignment interrupts, decrementer interrupts, program
interrupts, single-step interrupts, etc., coming to the hypervisor from
the guest. Therefore this introduces a new KVMTEST_NONHV macro for the
exception entry path so that we don't have to do the KVM test on entry
to those exception handlers.
We do however get hypervisor decrementer, hypervisor data storage,
hypervisor instruction storage, and hypervisor emulation assist
interrupts, so we have to handle those.
In hypervisor mode, real-mode accesses can access all of RAM, not just
a limited amount. Therefore we put all the guest state in the vcpu.arch
and use the shadow_vcpu in the PACA only for temporary scratch space.
We allocate the vcpu with kzalloc rather than vzalloc, and we don't use
anything in the kvmppc_vcpu_book3s struct, so we don't allocate it.
We don't have a shared page with the guest, but we still need a
kvm_vcpu_arch_shared struct to store the values of various registers,
so we include one in the vcpu_arch struct.
The POWER7 processor has a restriction that all threads in a core have
to be in the same partition. MMU-on kernel code counts as a partition
(partition 0), so we have to do a partition switch on every entry to and
exit from the guest. At present we require the host and guest to run
in single-thread mode because of this hardware restriction.
This code allocates a hashed page table for the guest and initializes
it with HPTEs for the guest's Virtual Real Memory Area (VRMA). We
require that the guest memory is allocated using 16MB huge pages, in
order to simplify the low-level memory management. This also means that
we can get away without tracking paging activity in the host for now,
since huge pages can't be paged or swapped.
This also adds a few new exports needed by the book3s_hv code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:21:34 +00:00
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#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
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2007-04-27 01:53:52 +00:00
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2007-06-14 05:31:34 +00:00
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#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
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#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
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2007-04-27 01:53:52 +00:00
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/* Values for PP (assumes Ks=0, Kp=1) */
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/* pp0 will always be 0 for linux */
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#define PP_RWXX 0 /* Supervisor read/write, User none */
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#define PP_RWRX 1 /* Supervisor read/write, User read */
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */
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#define PP_RXRX 3 /* Supervisor read, User read */
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#ifndef __ASSEMBLY__
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2007-06-13 04:52:56 +00:00
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struct hash_pte {
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2007-04-27 01:53:52 +00:00
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unsigned long v;
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unsigned long r;
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2007-06-13 04:52:56 +00:00
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};
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2007-04-27 01:53:52 +00:00
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2007-06-13 04:52:56 +00:00
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extern struct hash_pte *htab_address;
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2007-04-27 01:53:52 +00:00
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extern unsigned long htab_size_bytes;
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extern unsigned long htab_hash_mask;
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def
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{
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unsigned int shift; /* number of bits */
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unsigned int penc; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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};
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#endif /* __ASSEMBLY__ */
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2007-05-10 05:28:44 +00:00
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|
|
/*
|
|
|
|
|
* Segment sizes.
|
|
|
|
|
* These are the values used by hardware in the B field of
|
|
|
|
|
* SLB entries and the first dword of MMU hashtable entries.
|
|
|
|
|
* The B field is 2 bits; the values 2 and 3 are unused and reserved.
|
|
|
|
|
*/
|
|
|
|
|
#define MMU_SEGSIZE_256M 0
|
|
|
|
|
#define MMU_SEGSIZE_1T 1
|
|
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
|
2007-04-27 01:53:52 +00:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
|
|
|
|
/*
|
2007-10-11 10:37:10 +00:00
|
|
|
* The current system page and segment sizes
|
2007-04-27 01:53:52 +00:00
|
|
|
*/
|
|
|
|
|
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
|
|
|
|
|
extern int mmu_linear_psize;
|
|
|
|
|
extern int mmu_virtual_psize;
|
|
|
|
|
extern int mmu_vmalloc_psize;
|
[POWERPC] vmemmap fixes to use smaller pages
This changes vmemmap to use a different region (region 0xf) of the
address space, and to configure the page size of that region
dynamically at boot.
The problem with the current approach of always using 16M pages is that
it's not well suited to machines that have small amounts of memory such
as small partitions on pseries, or PS3's.
In fact, on the PS3, failure to allocate the 16M page backing vmmemmap
tends to prevent hotplugging the HV's "additional" memory, thus limiting
the available memory even more, from my experience down to something
like 80M total, which makes it really not very useable.
The logic used by my match to choose the vmemmap page size is:
- If 16M pages are available and there's 1G or more RAM at boot,
use that size.
- Else if 64K pages are available, use that
- Else use 4K pages
I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages)
and it seems to work fine.
Note that I intend to change the way we organize the kernel regions &
SLBs so the actual region will change from 0xf back to something else at
one point, as I simplify the SLB miss handler, but that will be for a
later patch.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-30 05:41:48 +00:00
|
|
|
extern int mmu_vmemmap_psize;
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int mmu_io_psize;
|
2007-10-11 10:37:10 +00:00
|
|
|
extern int mmu_kernel_ssize;
|
|
|
|
|
extern int mmu_highuser_ssize;
|
2007-12-06 06:24:48 +00:00
|
|
|
extern u16 mmu_slb_size;
|
2008-05-08 04:27:08 +00:00
|
|
|
extern unsigned long tce_alloc_start, tce_alloc_end;
|
2007-04-27 01:53:52 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If the processor supports 64k normal pages but not 64k cache
|
|
|
|
|
* inhibited pages, we have to be prepared to switch processes
|
|
|
|
|
* to use 4k pages when they create cache-inhibited mappings.
|
|
|
|
|
* If this is the case, mmu_ci_restrictions will be set to 1.
|
|
|
|
|
*/
|
|
|
|
|
extern int mmu_ci_restrictions;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This function sets the AVPN and L fields of the HPTE appropriately
|
|
|
|
|
* for the page size
|
|
|
|
|
*/
|
2007-10-11 10:37:10 +00:00
|
|
|
static inline unsigned long hpte_encode_v(unsigned long va, int psize,
|
|
|
|
|
int ssize)
|
2007-04-27 01:53:52 +00:00
|
|
|
{
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned long v;
|
2007-04-27 01:53:52 +00:00
|
|
|
v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
|
|
|
|
|
v <<= HPTE_V_AVPN_SHIFT;
|
|
|
|
|
if (psize != MMU_PAGE_4K)
|
|
|
|
|
v |= HPTE_V_LARGE;
|
2007-10-11 10:37:10 +00:00
|
|
|
v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
|
2007-04-27 01:53:52 +00:00
|
|
|
return v;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This function sets the ARPN, and LP fields of the HPTE appropriately
|
|
|
|
|
* for the page size. We assume the pa is already "clean" that is properly
|
|
|
|
|
* aligned for the requested page size
|
|
|
|
|
*/
|
|
|
|
|
static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
|
|
|
|
|
{
|
|
|
|
|
unsigned long r;
|
|
|
|
|
|
|
|
|
|
/* A 4K page needs no special encoding */
|
|
|
|
|
if (psize == MMU_PAGE_4K)
|
|
|
|
|
return pa & HPTE_R_RPN;
|
|
|
|
|
else {
|
|
|
|
|
unsigned int penc = mmu_psize_defs[psize].penc;
|
|
|
|
|
unsigned int shift = mmu_psize_defs[psize].shift;
|
|
|
|
|
return (pa & ~((1ul << shift) - 1)) | (penc << 12);
|
|
|
|
|
}
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
2007-10-11 10:37:10 +00:00
|
|
|
* Build a VA given VSID, EA and segment size
|
2007-04-27 01:53:52 +00:00
|
|
|
*/
|
2007-10-11 10:37:10 +00:00
|
|
|
static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
|
|
|
|
|
int ssize)
|
|
|
|
|
{
|
|
|
|
|
if (ssize == MMU_SEGSIZE_256M)
|
|
|
|
|
return (vsid << 28) | (ea & 0xfffffffUL);
|
|
|
|
|
return (vsid << 40) | (ea & 0xffffffffffUL);
|
|
|
|
|
}
|
2007-04-27 01:53:52 +00:00
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
/*
|
|
|
|
|
* This hashes a virtual address
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
|
|
|
|
|
int ssize)
|
2007-04-27 01:53:52 +00:00
|
|
|
{
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned long hash, vsid;
|
|
|
|
|
|
|
|
|
|
if (ssize == MMU_SEGSIZE_256M) {
|
|
|
|
|
hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
|
|
|
|
|
} else {
|
|
|
|
|
vsid = va >> 40;
|
|
|
|
|
hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
|
|
|
|
|
}
|
|
|
|
|
return hash & 0x7fffffffffUL;
|
2007-04-27 01:53:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
extern int __hash_page_4K(unsigned long ea, unsigned long access,
|
|
|
|
|
unsigned long vsid, pte_t *ptep, unsigned long trap,
|
[POWERPC] Provide a way to protect 4k subpages when using 64k pages
Using 64k pages on 64-bit PowerPC systems makes life difficult for
emulators that are trying to emulate an ISA, such as x86, which use a
smaller page size, since the emulator can no longer use the MMU and
the normal system calls for controlling page protections. Of course,
the emulator can emulate the MMU by checking and possibly remapping
the address for each memory access in software, but that is pretty
slow.
This provides a facility for such programs to control the access
permissions on individual 4k sub-pages of 64k pages. The idea is
that the emulator supplies an array of protection masks to apply to a
specified range of virtual addresses. These masks are applied at the
level where hardware PTEs are inserted into the hardware page table
based on the Linux PTEs, so the Linux PTEs are not affected. Note
that this new mechanism does not allow any access that would otherwise
be prohibited; it can only prohibit accesses that would otherwise be
allowed. This new facility is only available on 64-bit PowerPC and
only when the kernel is configured for 64k pages.
The masks are supplied using a new subpage_prot system call, which
takes a starting virtual address and length, and a pointer to an array
of protection masks in memory. The array has a 32-bit word per 64k
page to be protected; each 32-bit word consists of 16 2-bit fields,
for which 0 allows any access (that is otherwise allowed), 1 prevents
write accesses, and 2 or 3 prevent any access.
Implicit in this is that the regions of the address space that are
protected are switched to use 4k hardware pages rather than 64k
hardware pages (on machines with hardware 64k page support). In fact
the whole process is switched to use 4k hardware pages when the
subpage_prot system call is used, but this could be improved in future
to switch only the affected segments.
The subpage protection bits are stored in a 3 level tree akin to the
page table tree. The top level of this tree is stored in a structure
that is appended to the top level of the page table tree, i.e., the
pgd array. Since it will often only be 32-bit addresses (below 4GB)
that are protected, the pointers to the first four bottom level pages
are also stored in this structure (each bottom level page contains the
protection bits for 1GB of address space), so the protection bits for
addresses below 4GB can be accessed with one fewer loads than those
for higher addresses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-23 21:35:13 +00:00
|
|
|
unsigned int local, int ssize, int subpage_prot);
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int __hash_page_64K(unsigned long ea, unsigned long access,
|
|
|
|
|
unsigned long vsid, pte_t *ptep, unsigned long trap,
|
2007-10-11 10:37:10 +00:00
|
|
|
unsigned int local, int ssize);
|
2007-04-27 01:53:52 +00:00
|
|
|
struct mm_struct;
|
2009-10-26 19:24:31 +00:00
|
|
|
unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
|
powerpc/mm: Allow more flexible layouts for hugepage pagetables
Currently each available hugepage size uses a slightly different
pagetable layout: that is, the bottem level table of pointers to
hugepages is a different size, and may branch off from the normal page
tables at a different level. Every hugepage aware path that needs to
walk the pagetables must therefore look up the hugepage size from the
slice info first, and work out the correct way to walk the pagetables
accordingly. Future hardware is likely to add more possible hugepage
sizes, more layout options and more mess.
This patch, therefore reworks the handling of hugepage pagetables to
reduce this complexity. In the new scheme, instead of having to
consult the slice mask, pagetable walking code can check a flag in the
PGD/PUD/PMD entries to see where to branch off to hugepage pagetables,
and the entry also contains the information (eseentially hugepage
shift) necessary to then interpret that table without recourse to the
slice mask. This scheme can be extended neatly to handle multiple
levels of self-describing "special" hugepage pagetables, although for
now we assume only one level exists.
This approach means that only the pagetable allocation path needs to
know how the pagetables should be set out. All other (hugepage)
pagetable walking paths can just interpret the structure as they go.
There already was a flag bit in PGD/PUD/PMD entries for hugepage
directory pointers, but it was only used for debug. We alter that
flag bit to instead be a 0 in the MSB to indicate a hugepage pagetable
pointer (normally it would be 1 since the pointer lies in the linear
mapping). This means that asm pagetable walking can test for (and
punt on) hugepage pointers with the same test that checks for
unpopulated page directory entries (beq becomes bge), since hugepage
pointers will always be positive, and normal pointers always negative.
While we're at it, we get rid of the confusing (and grep defeating)
#defining of hugepte_shift to be the same thing as mmu_huge_psizes.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-10-26 19:24:31 +00:00
|
|
|
int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
|
|
|
|
|
pte_t *ptep, unsigned long trap, int local, int ssize,
|
|
|
|
|
unsigned int shift, unsigned int mmu_psize);
|
2010-07-23 00:31:13 +00:00
|
|
|
extern void hash_failure_debug(unsigned long ea, unsigned long access,
|
|
|
|
|
unsigned long vsid, unsigned long trap,
|
|
|
|
|
int ssize, int psize, unsigned long pte);
|
2007-04-27 01:53:52 +00:00
|
|
|
extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
|
2008-08-05 06:19:56 +00:00
|
|
|
unsigned long pstart, unsigned long prot,
|
2007-10-11 10:37:10 +00:00
|
|
|
int psize, int ssize);
|
2008-07-24 04:27:54 +00:00
|
|
|
extern void add_gpage(unsigned long addr, unsigned long page_size,
|
|
|
|
|
unsigned long number_of_pages);
|
[POWERPC] Provide a way to protect 4k subpages when using 64k pages
Using 64k pages on 64-bit PowerPC systems makes life difficult for
emulators that are trying to emulate an ISA, such as x86, which use a
smaller page size, since the emulator can no longer use the MMU and
the normal system calls for controlling page protections. Of course,
the emulator can emulate the MMU by checking and possibly remapping
the address for each memory access in software, but that is pretty
slow.
This provides a facility for such programs to control the access
permissions on individual 4k sub-pages of 64k pages. The idea is
that the emulator supplies an array of protection masks to apply to a
specified range of virtual addresses. These masks are applied at the
level where hardware PTEs are inserted into the hardware page table
based on the Linux PTEs, so the Linux PTEs are not affected. Note
that this new mechanism does not allow any access that would otherwise
be prohibited; it can only prohibit accesses that would otherwise be
allowed. This new facility is only available on 64-bit PowerPC and
only when the kernel is configured for 64k pages.
The masks are supplied using a new subpage_prot system call, which
takes a starting virtual address and length, and a pointer to an array
of protection masks in memory. The array has a 32-bit word per 64k
page to be protected; each 32-bit word consists of 16 2-bit fields,
for which 0 allows any access (that is otherwise allowed), 1 prevents
write accesses, and 2 or 3 prevent any access.
Implicit in this is that the regions of the address space that are
protected are switched to use 4k hardware pages rather than 64k
hardware pages (on machines with hardware 64k page support). In fact
the whole process is switched to use 4k hardware pages when the
subpage_prot system call is used, but this could be improved in future
to switch only the affected segments.
The subpage protection bits are stored in a 3 level tree akin to the
page table tree. The top level of this tree is stored in a structure
that is appended to the top level of the page table tree, i.e., the
pgd array. Since it will often only be 32-bit addresses (below 4GB)
that are protected, the pointers to the first four bottom level pages
are also stored in this structure (each bottom level page contains the
protection bits for 1GB of address space), so the protection bits for
addresses below 4GB can be accessed with one fewer loads than those
for higher addresses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-23 21:35:13 +00:00
|
|
|
extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
|
2007-04-27 01:53:52 +00:00
|
|
|
|
|
|
|
|
extern void hpte_init_native(void);
|
|
|
|
|
extern void hpte_init_lpar(void);
|
|
|
|
|
extern void hpte_init_iSeries(void);
|
|
|
|
|
extern void hpte_init_beat(void);
|
2007-10-02 08:23:46 +00:00
|
|
|
extern void hpte_init_beat_v3(void);
|
2007-04-27 01:53:52 +00:00
|
|
|
|
|
|
|
|
extern void stabs_alloc(void);
|
|
|
|
|
extern void slb_initialize(void);
|
|
|
|
|
extern void slb_flush_and_rebolt(void);
|
|
|
|
|
extern void stab_initialize(unsigned long stab);
|
|
|
|
|
|
2007-08-03 01:55:39 +00:00
|
|
|
extern void slb_vmalloc_update(void);
|
2009-08-28 12:06:29 +00:00
|
|
|
extern void slb_set_size(u16 size);
|
2007-04-27 01:53:52 +00:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* VSID allocation
|
|
|
|
|
*
|
|
|
|
|
* We first generate a 36-bit "proto-VSID". For kernel addresses this
|
|
|
|
|
* is equal to the ESID, for user addresses it is:
|
|
|
|
|
* (context << 15) | (esid & 0x7fff)
|
|
|
|
|
*
|
|
|
|
|
* The two forms are distinguishable because the top bit is 0 for user
|
|
|
|
|
* addresses, whereas the top two bits are 1 for kernel addresses.
|
|
|
|
|
* Proto-VSIDs with the top two bits equal to 0b10 are reserved for
|
|
|
|
|
* now.
|
|
|
|
|
*
|
|
|
|
|
* The proto-VSIDs are then scrambled into real VSIDs with the
|
|
|
|
|
* multiplicative hash:
|
|
|
|
|
*
|
|
|
|
|
* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
|
|
|
|
|
* where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
|
|
|
|
|
* VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
|
|
|
|
|
*
|
|
|
|
|
* This scramble is only well defined for proto-VSIDs below
|
|
|
|
|
* 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
|
|
|
|
|
* reserved. VSID_MULTIPLIER is prime, so in particular it is
|
|
|
|
|
* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
|
|
|
|
|
* Because the modulus is 2^n-1 we can compute it efficiently without
|
|
|
|
|
* a divide or extra multiply (see below).
|
|
|
|
|
*
|
|
|
|
|
* This scheme has several advantages over older methods:
|
|
|
|
|
*
|
|
|
|
|
* - We have VSIDs allocated for every kernel address
|
|
|
|
|
* (i.e. everything above 0xC000000000000000), except the very top
|
|
|
|
|
* segment, which simplifies several things.
|
|
|
|
|
*
|
|
|
|
|
* - We allow for 15 significant bits of ESID and 20 bits of
|
|
|
|
|
* context for user addresses. i.e. 8T (43 bits) of address space for
|
|
|
|
|
* up to 1M contexts (although the page table structure and context
|
|
|
|
|
* allocation will need changes to take advantage of this).
|
|
|
|
|
*
|
|
|
|
|
* - The scramble function gives robust scattering in the hash
|
|
|
|
|
* table (at least based on some initial results). The previous
|
|
|
|
|
* method was more susceptible to pathological cases giving excessive
|
|
|
|
|
* hash collisions.
|
|
|
|
|
*/
|
|
|
|
|
/*
|
|
|
|
|
* WARNING - If you change these you must make sure the asm
|
|
|
|
|
* implementations in slb_allocate (slb_low.S), do_stab_bolted
|
|
|
|
|
* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
|
|
|
|
|
*
|
|
|
|
|
* You'll also need to change the precomputed VSID values in head.S
|
|
|
|
|
* which are used by the iSeries firmware.
|
|
|
|
|
*/
|
|
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
|
|
|
|
|
#define VSID_BITS_256M 36
|
|
|
|
|
#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
|
2007-04-27 01:53:52 +00:00
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
|
|
|
|
|
#define VSID_BITS_1T 24
|
|
|
|
|
#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
|
|
|
|
|
|
|
|
|
|
#define CONTEXT_BITS 19
|
|
|
|
|
#define USER_ESID_BITS 16
|
|
|
|
|
#define USER_ESID_BITS_1T 4
|
2007-04-27 01:53:52 +00:00
|
|
|
|
|
|
|
|
#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
|
|
|
|
|
|
|
|
|
|
/*
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* This macro generates asm code to compute the VSID scramble
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register continaing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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*
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* - rt and rx must be different registers
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2007-10-11 10:37:10 +00:00
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* - The answer will end up in the low VSID_BITS bits of rt. The higher
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2007-04-27 01:53:52 +00:00
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* bits may contain other garbage, so you may need to mask the
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* result.
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*/
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2007-10-11 10:37:10 +00:00
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#define ASM_VSID_SCRAMBLE(rt, rx, size) \
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lis rx,VSID_MULTIPLIER_##size@h; \
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ori rx,rx,VSID_MULTIPLIER_##size@l; \
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2007-04-27 01:53:52 +00:00
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mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
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\
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2007-10-11 10:37:10 +00:00
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srdi rx,rt,VSID_BITS_##size; \
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clrldi rt,rt,(64-VSID_BITS_##size); \
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2007-04-27 01:53:52 +00:00
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add rt,rt,rx; /* add high and low bits */ \
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/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
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* 2^36-1+2^28-1. That in particular means that if r3 >= \
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* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
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* the bit clear, r3 already has the answer we want, if it \
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* doesn't, the answer is the low 36 bits of r3+1. So in all \
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* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
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addi rx,rt,1; \
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2007-10-11 10:37:10 +00:00
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srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
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2007-04-27 01:53:52 +00:00
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add rt,rt,rx
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#ifndef __ASSEMBLY__
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2009-11-26 18:56:04 +00:00
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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/*
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* For the sub-page protection option, we extend the PGD with one of
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* these. Basically we have a 3-level tree, with the top level being
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* the protptrs array. To optimize speed and memory consumption when
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* only addresses < 4GB are being protected, pointers to the first
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* four pages of sub-page protection words are stored in the low_prot
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* array.
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* Each page of sub-page protection words protects 1GB (4 bytes
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* protects 64k). For the 3-level tree, each page of pointers then
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* protects 8TB.
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*/
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struct subpage_prot_table {
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unsigned long maxaddr; /* only addresses < this are protected */
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unsigned int **protptrs[2];
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unsigned int *low_prot[4];
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};
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#define SBP_L1_BITS (PAGE_SHIFT - 2)
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#define SBP_L2_BITS (PAGE_SHIFT - 3)
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#define SBP_L1_COUNT (1 << SBP_L1_BITS)
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|
#define SBP_L2_COUNT (1 << SBP_L2_BITS)
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|
|
#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
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|
#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
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|
extern void subpage_prot_free(struct mm_struct *mm);
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|
extern void subpage_prot_init_new_context(struct mm_struct *mm);
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|
#else
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|
static inline void subpage_prot_free(struct mm_struct *mm) {}
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static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
|
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|
#endif /* CONFIG_PPC_SUBPAGE_PROT */
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|
2007-04-27 01:53:52 +00:00
|
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|
typedef unsigned long mm_context_id_t;
|
2011-05-02 20:43:04 +00:00
|
|
|
struct spinlock;
|
2007-04-27 01:53:52 +00:00
|
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|
|
typedef struct {
|
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|
|
mm_context_id_t id;
|
2007-05-08 06:27:27 +00:00
|
|
|
u16 user_psize; /* page size index */
|
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|
|
#ifdef CONFIG_PPC_MM_SLICES
|
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|
|
u64 low_slices_psize; /* SLB page size encodings */
|
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|
|
u64 high_slices_psize; /* 4 bits per slice for now */
|
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|
|
#else
|
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|
|
u16 sllp; /* SLB page size encoding */
|
2007-04-27 01:53:52 +00:00
|
|
|
#endif
|
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|
|
|
unsigned long vdso_base;
|
2009-11-26 18:56:04 +00:00
|
|
|
#ifdef CONFIG_PPC_SUBPAGE_PROT
|
|
|
|
|
struct subpage_prot_table spt;
|
|
|
|
|
#endif /* CONFIG_PPC_SUBPAGE_PROT */
|
2011-05-02 20:43:04 +00:00
|
|
|
#ifdef CONFIG_PPC_ICSWX
|
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|
|
|
struct spinlock *cop_lockp; /* guard acop and cop_pid */
|
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|
|
unsigned long acop; /* mask of enabled coprocessor types */
|
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|
|
unsigned int cop_pid; /* pid value used with coprocessors */
|
|
|
|
|
#endif /* CONFIG_PPC_ICSWX */
|
2007-04-27 01:53:52 +00:00
|
|
|
} mm_context_t;
|
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|
|
|
|
|
|
#if 0
|
2007-10-11 10:37:10 +00:00
|
|
|
/*
|
|
|
|
|
* The code below is equivalent to this function for arguments
|
|
|
|
|
* < 2^VSID_BITS, which is all this should ever be called
|
|
|
|
|
* with. However gcc is not clever enough to compute the
|
|
|
|
|
* modulus (2^n-1) without a second multiply.
|
|
|
|
|
*/
|
2010-08-02 20:35:18 +00:00
|
|
|
#define vsid_scramble(protovsid, size) \
|
2007-10-11 10:37:10 +00:00
|
|
|
((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
|
2007-04-27 01:53:52 +00:00
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
#else /* 1 */
|
|
|
|
|
#define vsid_scramble(protovsid, size) \
|
|
|
|
|
({ \
|
|
|
|
|
unsigned long x; \
|
|
|
|
|
x = (protovsid) * VSID_MULTIPLIER_##size; \
|
|
|
|
|
x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
|
|
|
|
|
(x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
|
|
|
|
|
})
|
2007-04-27 01:53:52 +00:00
|
|
|
#endif /* 1 */
|
|
|
|
|
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
/* This is only valid for addresses >= PAGE_OFFSET */
|
2007-10-11 10:37:10 +00:00
|
|
|
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
|
2007-04-27 01:53:52 +00:00
|
|
|
{
|
2007-10-11 10:37:10 +00:00
|
|
|
if (ssize == MMU_SEGSIZE_256M)
|
|
|
|
|
return vsid_scramble(ea >> SID_SHIFT, 256M);
|
|
|
|
|
return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
|
2007-04-27 01:53:52 +00:00
|
|
|
}
|
|
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
/* Returns the segment size indicator for a user address */
|
|
|
|
|
static inline int user_segment_size(unsigned long addr)
|
2007-04-27 01:53:52 +00:00
|
|
|
{
|
2007-10-11 10:37:10 +00:00
|
|
|
/* Use 1T segments if possible for addresses >= 1T */
|
|
|
|
|
if (addr >= (1UL << SID_SHIFT_1T))
|
|
|
|
|
return mmu_highuser_ssize;
|
|
|
|
|
return MMU_SEGSIZE_256M;
|
2007-04-27 01:53:52 +00:00
|
|
|
}
|
|
|
|
|
|
2007-10-11 10:37:10 +00:00
|
|
|
/* This is only valid for user addresses (which are below 2^44) */
|
|
|
|
|
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
|
|
|
|
|
int ssize)
|
|
|
|
|
{
|
|
|
|
|
if (ssize == MMU_SEGSIZE_256M)
|
|
|
|
|
return vsid_scramble((context << USER_ESID_BITS)
|
|
|
|
|
| (ea >> SID_SHIFT), 256M);
|
|
|
|
|
return vsid_scramble((context << USER_ESID_BITS_1T)
|
|
|
|
|
| (ea >> SID_SHIFT_1T), 1T);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This is only used on legacy iSeries in lparmap.c,
|
|
|
|
|
* hence the 256MB segment assumption.
|
|
|
|
|
*/
|
|
|
|
|
#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \
|
|
|
|
|
VSID_MODULUS_256M)
|
2007-04-27 01:53:52 +00:00
|
|
|
#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
|
|
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
|
|
|
|
#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
|
