2021-12-07 09:00:30 -08:00
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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* Copyright (c) 2021 Innovative Advantage
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*/
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#include <soc/mscc/ocelot_vcap.h>
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#include <soc/mscc/vsc7514_regs.h>
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#include "ocelot.h"
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const u32 vsc7514_ana_regmap[] = {
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REG(ANA_ADVLEARN, 0x009000),
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REG(ANA_VLANMASK, 0x009004),
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REG(ANA_PORT_B_DOMAIN, 0x009008),
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REG(ANA_ANAGEFIL, 0x00900c),
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REG(ANA_ANEVENTS, 0x009010),
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REG(ANA_STORMLIMIT_BURST, 0x009014),
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REG(ANA_STORMLIMIT_CFG, 0x009018),
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REG(ANA_ISOLATED_PORTS, 0x009028),
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REG(ANA_COMMUNITY_PORTS, 0x00902c),
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REG(ANA_AUTOAGE, 0x009030),
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REG(ANA_MACTOPTIONS, 0x009034),
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REG(ANA_LEARNDISC, 0x009038),
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REG(ANA_AGENCTRL, 0x00903c),
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REG(ANA_MIRRORPORTS, 0x009040),
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REG(ANA_EMIRRORPORTS, 0x009044),
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REG(ANA_FLOODING, 0x009048),
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REG(ANA_FLOODING_IPMC, 0x00904c),
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REG(ANA_SFLOW_CFG, 0x009050),
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REG(ANA_PORT_MODE, 0x009080),
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REG(ANA_PGID_PGID, 0x008c00),
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REG(ANA_TABLES_ANMOVED, 0x008b30),
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REG(ANA_TABLES_MACHDATA, 0x008b34),
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REG(ANA_TABLES_MACLDATA, 0x008b38),
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REG(ANA_TABLES_MACACCESS, 0x008b3c),
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REG(ANA_TABLES_MACTINDX, 0x008b40),
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REG(ANA_TABLES_VLANACCESS, 0x008b44),
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REG(ANA_TABLES_VLANTIDX, 0x008b48),
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REG(ANA_TABLES_ISDXACCESS, 0x008b4c),
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REG(ANA_TABLES_ISDXTIDX, 0x008b50),
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REG(ANA_TABLES_ENTRYLIM, 0x008b00),
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REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54),
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REG(ANA_TABLES_PTP_ID_LOW, 0x008b58),
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REG(ANA_MSTI_STATE, 0x008e00),
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REG(ANA_PORT_VLAN_CFG, 0x007000),
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REG(ANA_PORT_DROP_CFG, 0x007004),
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REG(ANA_PORT_QOS_CFG, 0x007008),
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REG(ANA_PORT_VCAP_CFG, 0x00700c),
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REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010),
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REG(ANA_PORT_VCAP_S2_CFG, 0x00701c),
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REG(ANA_PORT_PCP_DEI_MAP, 0x007020),
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REG(ANA_PORT_CPU_FWD_CFG, 0x007060),
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REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064),
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REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068),
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REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c),
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REG(ANA_PORT_PORT_CFG, 0x007070),
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REG(ANA_PORT_POL_CFG, 0x007074),
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REG(ANA_PORT_PTP_CFG, 0x007078),
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REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c),
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REG(ANA_OAM_UPM_LM_CNT, 0x007c00),
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REG(ANA_PORT_PTP_DLY2_CFG, 0x007080),
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REG(ANA_PFC_PFC_CFG, 0x008800),
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REG(ANA_PFC_PFC_TIMER, 0x008804),
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REG(ANA_IPT_OAM_MEP_CFG, 0x008000),
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REG(ANA_IPT_IPT, 0x008004),
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REG(ANA_PPT_PPT, 0x008ac0),
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REG(ANA_FID_MAP_FID_MAP, 0x000000),
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REG(ANA_AGGR_CFG, 0x0090b4),
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REG(ANA_CPUQ_CFG, 0x0090b8),
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REG(ANA_CPUQ_CFG2, 0x0090bc),
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REG(ANA_CPUQ_8021_CFG, 0x0090c0),
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REG(ANA_DSCP_CFG, 0x009100),
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REG(ANA_DSCP_REWR_CFG, 0x009200),
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REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240),
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REG(ANA_VCAP_RNG_VAL_CFG, 0x009260),
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REG(ANA_VRAP_CFG, 0x009280),
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REG(ANA_VRAP_HDR_DATA, 0x009284),
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REG(ANA_VRAP_HDR_MASK, 0x009288),
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REG(ANA_DISCARD_CFG, 0x00928c),
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REG(ANA_FID_CFG, 0x009290),
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REG(ANA_POL_PIR_CFG, 0x004000),
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REG(ANA_POL_CIR_CFG, 0x004004),
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REG(ANA_POL_MODE_CFG, 0x004008),
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REG(ANA_POL_PIR_STATE, 0x00400c),
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REG(ANA_POL_CIR_STATE, 0x004010),
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REG(ANA_POL_STATE, 0x004014),
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REG(ANA_POL_FLOWC, 0x008b80),
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REG(ANA_POL_HYST, 0x008bec),
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REG(ANA_POL_MISC_CFG, 0x008bf0),
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};
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EXPORT_SYMBOL(vsc7514_ana_regmap);
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const u32 vsc7514_qs_regmap[] = {
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REG(QS_XTR_GRP_CFG, 0x000000),
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REG(QS_XTR_RD, 0x000008),
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REG(QS_XTR_FRM_PRUNING, 0x000010),
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REG(QS_XTR_FLUSH, 0x000018),
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REG(QS_XTR_DATA_PRESENT, 0x00001c),
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REG(QS_XTR_CFG, 0x000020),
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REG(QS_INJ_GRP_CFG, 0x000024),
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REG(QS_INJ_WR, 0x00002c),
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REG(QS_INJ_CTRL, 0x000034),
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REG(QS_INJ_STATUS, 0x00003c),
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REG(QS_INJ_ERR, 0x000040),
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REG(QS_INH_DBG, 0x000048),
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};
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EXPORT_SYMBOL(vsc7514_qs_regmap);
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const u32 vsc7514_qsys_regmap[] = {
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REG(QSYS_PORT_MODE, 0x011200),
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REG(QSYS_SWITCH_PORT_MODE, 0x011234),
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REG(QSYS_STAT_CNT_CFG, 0x011264),
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REG(QSYS_EEE_CFG, 0x011268),
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REG(QSYS_EEE_THRES, 0x011294),
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REG(QSYS_IGR_NO_SHARING, 0x011298),
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REG(QSYS_EGR_NO_SHARING, 0x01129c),
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REG(QSYS_SW_STATUS, 0x0112a0),
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REG(QSYS_EXT_CPU_CFG, 0x0112d0),
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REG(QSYS_PAD_CFG, 0x0112d4),
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REG(QSYS_CPU_GROUP_MAP, 0x0112d8),
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REG(QSYS_QMAP, 0x0112dc),
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REG(QSYS_ISDX_SGRP, 0x011400),
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REG(QSYS_TIMED_FRAME_ENTRY, 0x014000),
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REG(QSYS_TFRM_MISC, 0x011310),
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REG(QSYS_TFRM_PORT_DLY, 0x011314),
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REG(QSYS_TFRM_TIMER_CFG_1, 0x011318),
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REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c),
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REG(QSYS_TFRM_TIMER_CFG_3, 0x011320),
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REG(QSYS_TFRM_TIMER_CFG_4, 0x011324),
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REG(QSYS_TFRM_TIMER_CFG_5, 0x011328),
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REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c),
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REG(QSYS_TFRM_TIMER_CFG_7, 0x011330),
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REG(QSYS_TFRM_TIMER_CFG_8, 0x011334),
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REG(QSYS_RED_PROFILE, 0x011338),
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REG(QSYS_RES_QOS_MODE, 0x011378),
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REG(QSYS_RES_CFG, 0x012000),
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REG(QSYS_RES_STAT, 0x012004),
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REG(QSYS_EGR_DROP_MODE, 0x01137c),
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REG(QSYS_EQ_CTRL, 0x011380),
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REG(QSYS_EVENTS_CORE, 0x011384),
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REG(QSYS_CIR_CFG, 0x000000),
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REG(QSYS_EIR_CFG, 0x000004),
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REG(QSYS_SE_CFG, 0x000008),
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REG(QSYS_SE_DWRR_CFG, 0x00000c),
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REG(QSYS_SE_CONNECT, 0x00003c),
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REG(QSYS_SE_DLB_SENSE, 0x000040),
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REG(QSYS_CIR_STATE, 0x000044),
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REG(QSYS_EIR_STATE, 0x000048),
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REG(QSYS_SE_STATE, 0x00004c),
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REG(QSYS_HSCH_MISC_CFG, 0x011388),
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};
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EXPORT_SYMBOL(vsc7514_qsys_regmap);
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const u32 vsc7514_rew_regmap[] = {
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REG(REW_PORT_VLAN_CFG, 0x000000),
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REG(REW_TAG_CFG, 0x000004),
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REG(REW_PORT_CFG, 0x000008),
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REG(REW_DSCP_CFG, 0x00000c),
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REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
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REG(REW_PTP_CFG, 0x000050),
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REG(REW_PTP_DLY1_CFG, 0x000054),
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REG(REW_DSCP_REMAP_DP1_CFG, 0x000690),
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REG(REW_DSCP_REMAP_CFG, 0x000790),
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REG(REW_STAT_CFG, 0x000890),
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REG(REW_PPT, 0x000680),
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};
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EXPORT_SYMBOL(vsc7514_rew_regmap);
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const u32 vsc7514_sys_regmap[] = {
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REG(SYS_COUNT_RX_OCTETS, 0x000000),
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REG(SYS_COUNT_RX_UNICAST, 0x000004),
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REG(SYS_COUNT_RX_MULTICAST, 0x000008),
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REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
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REG(SYS_COUNT_RX_SHORTS, 0x000010),
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REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
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REG(SYS_COUNT_RX_JABBERS, 0x000018),
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REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
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REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
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REG(SYS_COUNT_RX_64, 0x000024),
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REG(SYS_COUNT_RX_65_127, 0x000028),
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REG(SYS_COUNT_RX_128_255, 0x00002c),
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net: mscc: ocelot: fix incorrect ndo_get_stats64 packet counters
Reading stats using the SYS_COUNT_* register definitions is only used by
ocelot_get_stats64() from the ocelot switchdev driver, however,
currently the bucket definitions are incorrect.
Separately, on both RX and TX, we have the following problems:
- a 256-1023 bucket which actually tracks the 256-511 packets
- the 1024-1526 bucket actually tracks the 512-1023 packets
- the 1527-max bucket actually tracks the 1024-1526 packets
=> nobody tracks the packets from the real 1527-max bucket
Additionally, the RX_PAUSE, RX_CONTROL, RX_LONGS and RX_CLASSIFIED_DROPS
all track the wrong thing. However this doesn't seem to have any
consequence, since ocelot_get_stats64() doesn't use these.
Even though this problem only manifests itself for the switchdev driver,
we cannot split the fix for ocelot and for DSA, since it requires fixing
the bucket definitions from enum ocelot_reg, which makes us necessarily
adapt the structures from felix and seville as well.
Fixes: 84705fc16552 ("net: dsa: felix: introduce support for Seville VSC9953 switch")
Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family")
Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-16 16:53:46 +03:00
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REG(SYS_COUNT_RX_256_511, 0x000030),
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REG(SYS_COUNT_RX_512_1023, 0x000034),
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REG(SYS_COUNT_RX_1024_1526, 0x000038),
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REG(SYS_COUNT_RX_1527_MAX, 0x00003c),
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REG(SYS_COUNT_RX_PAUSE, 0x000040),
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REG(SYS_COUNT_RX_CONTROL, 0x000044),
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REG(SYS_COUNT_RX_LONGS, 0x000048),
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REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c),
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2022-08-16 16:53:51 +03:00
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REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050),
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REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054),
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REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058),
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REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c),
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REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060),
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REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064),
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REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068),
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REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c),
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REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070),
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REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074),
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REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078),
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REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c),
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REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080),
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REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084),
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REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088),
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REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c),
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REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090),
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REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094),
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REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098),
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REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c),
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REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0),
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REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4),
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REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8),
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REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac),
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2021-12-07 09:00:30 -08:00
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REG(SYS_COUNT_TX_OCTETS, 0x000100),
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REG(SYS_COUNT_TX_UNICAST, 0x000104),
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REG(SYS_COUNT_TX_MULTICAST, 0x000108),
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REG(SYS_COUNT_TX_BROADCAST, 0x00010c),
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REG(SYS_COUNT_TX_COLLISION, 0x000110),
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REG(SYS_COUNT_TX_DROPS, 0x000114),
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REG(SYS_COUNT_TX_PAUSE, 0x000118),
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REG(SYS_COUNT_TX_64, 0x00011c),
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REG(SYS_COUNT_TX_65_127, 0x000120),
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net: mscc: ocelot: fix incorrect ndo_get_stats64 packet counters
Reading stats using the SYS_COUNT_* register definitions is only used by
ocelot_get_stats64() from the ocelot switchdev driver, however,
currently the bucket definitions are incorrect.
Separately, on both RX and TX, we have the following problems:
- a 256-1023 bucket which actually tracks the 256-511 packets
- the 1024-1526 bucket actually tracks the 512-1023 packets
- the 1527-max bucket actually tracks the 1024-1526 packets
=> nobody tracks the packets from the real 1527-max bucket
Additionally, the RX_PAUSE, RX_CONTROL, RX_LONGS and RX_CLASSIFIED_DROPS
all track the wrong thing. However this doesn't seem to have any
consequence, since ocelot_get_stats64() doesn't use these.
Even though this problem only manifests itself for the switchdev driver,
we cannot split the fix for ocelot and for DSA, since it requires fixing
the bucket definitions from enum ocelot_reg, which makes us necessarily
adapt the structures from felix and seville as well.
Fixes: 84705fc16552 ("net: dsa: felix: introduce support for Seville VSC9953 switch")
Fixes: 56051948773e ("net: dsa: ocelot: add driver for Felix switch family")
Fixes: a556c76adc05 ("net: mscc: Add initial Ocelot switch support")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-08-16 16:53:46 +03:00
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REG(SYS_COUNT_TX_128_255, 0x000124),
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REG(SYS_COUNT_TX_256_511, 0x000128),
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REG(SYS_COUNT_TX_512_1023, 0x00012c),
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REG(SYS_COUNT_TX_1024_1526, 0x000130),
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REG(SYS_COUNT_TX_1527_MAX, 0x000134),
|
2022-08-16 16:53:51 +03:00
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REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138),
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REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c),
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REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140),
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REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144),
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REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148),
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REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c),
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REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150),
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|
REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154),
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|
REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158),
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REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c),
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REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160),
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REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164),
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|
REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168),
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|
REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c),
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REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170),
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|
REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174),
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2022-09-08 19:48:14 +03:00
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|
REG(SYS_COUNT_TX_AGED, 0x000178),
|
2022-08-16 16:53:51 +03:00
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|
REG(SYS_COUNT_DROP_LOCAL, 0x000200),
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|
REG(SYS_COUNT_DROP_TAIL, 0x000204),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c),
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|
REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220),
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|
|
REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000214),
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|
|
REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000218),
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|
|
REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00021c),
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|
REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000220),
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|
|
REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000224),
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|
REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000228),
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|
|
REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00022c),
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|
|
|
REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000230),
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|
|
REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000234),
|
2021-12-07 09:00:30 -08:00
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|
REG(SYS_RESET_CFG, 0x000508),
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|
REG(SYS_CMID, 0x00050c),
|
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|
|
REG(SYS_VLAN_ETYPE_CFG, 0x000510),
|
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|
|
REG(SYS_PORT_MODE, 0x000514),
|
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|
REG(SYS_FRONT_PORT_MODE, 0x000548),
|
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|
|
REG(SYS_FRM_AGING, 0x000574),
|
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|
REG(SYS_STAT_CFG, 0x000578),
|
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|
|
REG(SYS_SW_STATUS, 0x00057c),
|
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|
|
REG(SYS_MISC_CFG, 0x0005ac),
|
|
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|
REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0),
|
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|
|
REG(SYS_REW_MAC_LOW_CFG, 0x0005dc),
|
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|
|
|
REG(SYS_CM_ADDR, 0x000500),
|
|
|
|
|
REG(SYS_CM_DATA, 0x000504),
|
|
|
|
|
REG(SYS_PAUSE_CFG, 0x000608),
|
|
|
|
|
REG(SYS_PAUSE_TOT_CFG, 0x000638),
|
|
|
|
|
REG(SYS_ATOP, 0x00063c),
|
|
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|
|
REG(SYS_ATOP_TOT_CFG, 0x00066c),
|
|
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|
|
REG(SYS_MAC_FC_CFG, 0x000670),
|
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|
|
|
REG(SYS_MMGT, 0x00069c),
|
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|
|
|
REG(SYS_MMGT_FAST, 0x0006a0),
|
|
|
|
|
REG(SYS_EVENTS_DIF, 0x0006a4),
|
|
|
|
|
REG(SYS_EVENTS_CORE, 0x0006b4),
|
|
|
|
|
REG(SYS_PTP_STATUS, 0x0006b8),
|
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|
|
REG(SYS_PTP_TXSTAMP, 0x0006bc),
|
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|
|
REG(SYS_PTP_NXT, 0x0006c0),
|
|
|
|
|
REG(SYS_PTP_CFG, 0x0006c4),
|
|
|
|
|
};
|
|
|
|
|
EXPORT_SYMBOL(vsc7514_sys_regmap);
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|
|
const u32 vsc7514_vcap_regmap[] = {
|
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|
|
/* VCAP_CORE_CFG */
|
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|
|
REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
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|
REG(VCAP_CORE_MV_CFG, 0x000004),
|
|
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|
|
/* VCAP_CORE_CACHE */
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|
REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
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|
REG(VCAP_CACHE_MASK_DAT, 0x000108),
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|
|
REG(VCAP_CACHE_ACTION_DAT, 0x000208),
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|
|
REG(VCAP_CACHE_CNT_DAT, 0x000308),
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|
|
REG(VCAP_CACHE_TG_DAT, 0x000388),
|
|
|
|
|
/* VCAP_CONST */
|
|
|
|
|
REG(VCAP_CONST_VCAP_VER, 0x000398),
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|
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|
|
REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
|
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|
|
|
REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
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|
|
REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
|
|
|
|
|
REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
|
|
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|
|
REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
|
|
|
|
|
REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
|
|
|
|
|
REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
|
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|
|
|
REG(VCAP_CONST_CORE_CNT, 0x0003b8),
|
|
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|
|
REG(VCAP_CONST_IF_CNT, 0x0003bc),
|
|
|
|
|
};
|
|
|
|
|
EXPORT_SYMBOL(vsc7514_vcap_regmap);
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|
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|
|
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|
|
const u32 vsc7514_ptp_regmap[] = {
|
|
|
|
|
REG(PTP_PIN_CFG, 0x000000),
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|
REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
|
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|
|
REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
|
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|
|
REG(PTP_PIN_TOD_NSEC, 0x00000c),
|
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|
|
REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
|
|
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|
|
REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
|
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|
|
REG(PTP_CFG_MISC, 0x0000a0),
|
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|
|
REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
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|
|
|
REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
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|
|
|
|
};
|
|
|
|
|
EXPORT_SYMBOL(vsc7514_ptp_regmap);
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|
|
const u32 vsc7514_dev_gmii_regmap[] = {
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REG(DEV_CLOCK_CFG, 0x0),
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|
REG(DEV_PORT_MISC, 0x4),
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|
REG(DEV_EVENTS, 0x8),
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|
REG(DEV_EEE_CFG, 0xc),
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|
REG(DEV_RX_PATH_DELAY, 0x10),
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|
REG(DEV_TX_PATH_DELAY, 0x14),
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|
|
REG(DEV_PTP_PREDICT_CFG, 0x18),
|
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|
|
REG(DEV_MAC_ENA_CFG, 0x1c),
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|
|
REG(DEV_MAC_MODE_CFG, 0x20),
|
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|
|
REG(DEV_MAC_MAXLEN_CFG, 0x24),
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|
|
REG(DEV_MAC_TAGS_CFG, 0x28),
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|
|
REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
|
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|
|
REG(DEV_MAC_IFG_CFG, 0x30),
|
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|
|
REG(DEV_MAC_HDX_CFG, 0x34),
|
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|
|
REG(DEV_MAC_DBG_CFG, 0x38),
|
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|
REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
|
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|
|
REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
|
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|
|
REG(DEV_MAC_STICKY, 0x44),
|
|
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|
|
REG(PCS1G_CFG, 0x48),
|
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|
|
|
REG(PCS1G_MODE_CFG, 0x4c),
|
|
|
|
|
REG(PCS1G_SD_CFG, 0x50),
|
|
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|
|
REG(PCS1G_ANEG_CFG, 0x54),
|
|
|
|
|
REG(PCS1G_ANEG_NP_CFG, 0x58),
|
|
|
|
|
REG(PCS1G_LB_CFG, 0x5c),
|
|
|
|
|
REG(PCS1G_DBG_CFG, 0x60),
|
|
|
|
|
REG(PCS1G_CDET_CFG, 0x64),
|
|
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|
|
REG(PCS1G_ANEG_STATUS, 0x68),
|
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|
|
REG(PCS1G_ANEG_NP_STATUS, 0x6c),
|
|
|
|
|
REG(PCS1G_LINK_STATUS, 0x70),
|
|
|
|
|
REG(PCS1G_LINK_DOWN_CNT, 0x74),
|
|
|
|
|
REG(PCS1G_STICKY, 0x78),
|
|
|
|
|
REG(PCS1G_DEBUG_STATUS, 0x7c),
|
|
|
|
|
REG(PCS1G_LPI_CFG, 0x80),
|
|
|
|
|
REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84),
|
|
|
|
|
REG(PCS1G_LPI_STATUS, 0x88),
|
|
|
|
|
REG(PCS1G_TSTPAT_MODE_CFG, 0x8c),
|
|
|
|
|
REG(PCS1G_TSTPAT_STATUS, 0x90),
|
|
|
|
|
REG(DEV_PCS_FX100_CFG, 0x94),
|
|
|
|
|
REG(DEV_PCS_FX100_STATUS, 0x98),
|
|
|
|
|
};
|
|
|
|
|
EXPORT_SYMBOL(vsc7514_dev_gmii_regmap);
|
|
|
|
|
|
|
|
|
|
const struct vcap_field vsc7514_vcap_es0_keys[] = {
|
|
|
|
|
[VCAP_ES0_EGR_PORT] = { 0, 4 },
|
|
|
|
|
[VCAP_ES0_IGR_PORT] = { 4, 4 },
|
|
|
|
|
[VCAP_ES0_RSV] = { 8, 2 },
|
|
|
|
|
[VCAP_ES0_L2_MC] = { 10, 1 },
|
|
|
|
|
[VCAP_ES0_L2_BC] = { 11, 1 },
|
|
|
|
|
[VCAP_ES0_VID] = { 12, 12 },
|
|
|
|
|
[VCAP_ES0_DP] = { 24, 1 },
|
|
|
|
|
[VCAP_ES0_PCP] = { 25, 3 },
|
|
|
|
|
};
|
|
|
|
|
EXPORT_SYMBOL(vsc7514_vcap_es0_keys);
|
|
|
|
|
|
|
|
|
|
const struct vcap_field vsc7514_vcap_es0_actions[] = {
|
|
|
|
|
[VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2 },
|
|
|
|
|
[VCAP_ES0_ACT_VID_A_VAL] = { 17, 12 },
|
|
|
|
|
[VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3 },
|
|
|
|
|
[VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1 },
|
|
|
|
|
[VCAP_ES0_ACT_VID_B_VAL] = { 33, 12 },
|
|
|
|
|
[VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3 },
|
|
|
|
|
[VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1 },
|
|
|
|
|
[VCAP_ES0_ACT_RSV] = { 49, 24 },
|
|
|
|
|
[VCAP_ES0_ACT_HIT_STICKY] = { 73, 1 },
|
|
|
|
|
};
|
|
|
|
|
EXPORT_SYMBOL(vsc7514_vcap_es0_actions);
|
|
|
|
|
|
|
|
|
|
const struct vcap_field vsc7514_vcap_is1_keys[] = {
|
|
|
|
|
[VCAP_IS1_HK_TYPE] = { 0, 1 },
|
|
|
|
|
[VCAP_IS1_HK_LOOKUP] = { 1, 2 },
|
|
|
|
|
[VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12 },
|
|
|
|
|
[VCAP_IS1_HK_RSV] = { 15, 9 },
|
|
|
|
|
[VCAP_IS1_HK_OAM_Y1731] = { 24, 1 },
|
|
|
|
|
[VCAP_IS1_HK_L2_MC] = { 25, 1 },
|
|
|
|
|
[VCAP_IS1_HK_L2_BC] = { 26, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP_MC] = { 27, 1 },
|
|
|
|
|
[VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1 },
|
|
|
|
|
[VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1 },
|
|
|
|
|
[VCAP_IS1_HK_TPID] = { 30, 1 },
|
|
|
|
|
[VCAP_IS1_HK_VID] = { 31, 12 },
|
|
|
|
|
[VCAP_IS1_HK_DEI] = { 43, 1 },
|
|
|
|
|
[VCAP_IS1_HK_PCP] = { 44, 3 },
|
|
|
|
|
/* Specific Fields for IS1 Half Key S1_NORMAL */
|
|
|
|
|
[VCAP_IS1_HK_L2_SMAC] = { 47, 48 },
|
|
|
|
|
[VCAP_IS1_HK_ETYPE_LEN] = { 95, 1 },
|
|
|
|
|
[VCAP_IS1_HK_ETYPE] = { 96, 16 },
|
|
|
|
|
[VCAP_IS1_HK_IP_SNAP] = { 112, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4] = { 113, 1 },
|
|
|
|
|
/* Layer-3 Information */
|
|
|
|
|
[VCAP_IS1_HK_L3_FRAGMENT] = { 114, 1 },
|
|
|
|
|
[VCAP_IS1_HK_L3_FRAG_OFS_GT0] = { 115, 1 },
|
|
|
|
|
[VCAP_IS1_HK_L3_OPTIONS] = { 116, 1 },
|
|
|
|
|
[VCAP_IS1_HK_L3_DSCP] = { 117, 6 },
|
|
|
|
|
[VCAP_IS1_HK_L3_IP4_SIP] = { 123, 32 },
|
|
|
|
|
/* Layer-4 Information */
|
|
|
|
|
[VCAP_IS1_HK_TCP_UDP] = { 155, 1 },
|
|
|
|
|
[VCAP_IS1_HK_TCP] = { 156, 1 },
|
|
|
|
|
[VCAP_IS1_HK_L4_SPORT] = { 157, 16 },
|
|
|
|
|
[VCAP_IS1_HK_L4_RNG] = { 173, 8 },
|
|
|
|
|
/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
|
|
|
|
|
[VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_IP4] = { 64, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_IP4_SIP] = { 106, 32 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L3_PROTO] = { 138, 8 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_TCP_UDP] = { 146, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_TCP] = { 147, 1 },
|
|
|
|
|
[VCAP_IS1_HK_IP4_L4_RNG] = { 148, 8 },
|
|
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[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = { 156, 32 },
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};
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EXPORT_SYMBOL(vsc7514_vcap_is1_keys);
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const struct vcap_field vsc7514_vcap_is1_actions[] = {
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[VCAP_IS1_ACT_DSCP_ENA] = { 0, 1 },
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[VCAP_IS1_ACT_DSCP_VAL] = { 1, 6 },
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[VCAP_IS1_ACT_QOS_ENA] = { 7, 1 },
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[VCAP_IS1_ACT_QOS_VAL] = { 8, 3 },
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[VCAP_IS1_ACT_DP_ENA] = { 11, 1 },
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[VCAP_IS1_ACT_DP_VAL] = { 12, 1 },
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[VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8 },
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[VCAP_IS1_ACT_PAG_VAL] = { 21, 8 },
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[VCAP_IS1_ACT_RSV] = { 29, 9 },
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/* The fields below are incorrectly shifted by 2 in the manual */
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[VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1 },
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[VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12 },
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[VCAP_IS1_ACT_FID_SEL] = { 51, 2 },
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[VCAP_IS1_ACT_FID_VAL] = { 53, 13 },
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[VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1 },
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[VCAP_IS1_ACT_PCP_VAL] = { 67, 3 },
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[VCAP_IS1_ACT_DEI_VAL] = { 70, 1 },
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[VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1 },
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[VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2 },
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[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4 },
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[VCAP_IS1_ACT_HIT_STICKY] = { 78, 1 },
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};
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EXPORT_SYMBOL(vsc7514_vcap_is1_actions);
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const struct vcap_field vsc7514_vcap_is2_keys[] = {
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/* Common: 46 bits */
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[VCAP_IS2_TYPE] = { 0, 4 },
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[VCAP_IS2_HK_FIRST] = { 4, 1 },
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[VCAP_IS2_HK_PAG] = { 5, 8 },
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[VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12 },
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[VCAP_IS2_HK_RSV2] = { 25, 1 },
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[VCAP_IS2_HK_HOST_MATCH] = { 26, 1 },
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[VCAP_IS2_HK_L2_MC] = { 27, 1 },
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[VCAP_IS2_HK_L2_BC] = { 28, 1 },
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[VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1 },
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[VCAP_IS2_HK_VID] = { 30, 12 },
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[VCAP_IS2_HK_DEI] = { 42, 1 },
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[VCAP_IS2_HK_PCP] = { 43, 3 },
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/* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
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[VCAP_IS2_HK_L2_DMAC] = { 46, 48 },
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[VCAP_IS2_HK_L2_SMAC] = { 94, 48 },
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/* MAC_ETYPE (TYPE=000) */
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[VCAP_IS2_HK_MAC_ETYPE_ETYPE] = { 142, 16 },
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[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = { 158, 16 },
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[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = { 174, 8 },
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[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = { 182, 3 },
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/* MAC_LLC (TYPE=001) */
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[VCAP_IS2_HK_MAC_LLC_L2_LLC] = { 142, 40 },
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/* MAC_SNAP (TYPE=010) */
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[VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = { 142, 40 },
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/* MAC_ARP (TYPE=011) */
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[VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48 },
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[VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1 },
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[VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1 },
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[VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1 },
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[VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1 },
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[VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1 },
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[VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1 },
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[VCAP_IS2_HK_MAC_ARP_OPCODE] = { 100, 2 },
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[VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 102, 32 },
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[VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = { 134, 32 },
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[VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = { 166, 1 },
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/* IP4_TCP_UDP / IP4_OTHER common */
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[VCAP_IS2_HK_IP4] = { 46, 1 },
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[VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1 },
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[VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1 },
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[VCAP_IS2_HK_L3_OPTIONS] = { 49, 1 },
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[VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1 },
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[VCAP_IS2_HK_L3_TOS] = { 51, 8 },
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[VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32 },
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[VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32 },
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[VCAP_IS2_HK_DIP_EQ_SIP] = { 123, 1 },
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/* IP4_TCP_UDP (TYPE=100) */
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[VCAP_IS2_HK_TCP] = { 124, 1 },
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[VCAP_IS2_HK_L4_DPORT] = { 125, 16 },
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[VCAP_IS2_HK_L4_SPORT] = { 141, 16 },
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[VCAP_IS2_HK_L4_RNG] = { 157, 8 },
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[VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = { 165, 1 },
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[VCAP_IS2_HK_L4_SEQUENCE_EQ0] = { 166, 1 },
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[VCAP_IS2_HK_L4_FIN] = { 167, 1 },
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[VCAP_IS2_HK_L4_SYN] = { 168, 1 },
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[VCAP_IS2_HK_L4_RST] = { 169, 1 },
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[VCAP_IS2_HK_L4_PSH] = { 170, 1 },
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[VCAP_IS2_HK_L4_ACK] = { 171, 1 },
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[VCAP_IS2_HK_L4_URG] = { 172, 1 },
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[VCAP_IS2_HK_L4_1588_DOM] = { 173, 8 },
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[VCAP_IS2_HK_L4_1588_VER] = { 181, 4 },
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/* IP4_OTHER (TYPE=101) */
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[VCAP_IS2_HK_IP4_L3_PROTO] = { 124, 8 },
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[VCAP_IS2_HK_L3_PAYLOAD] = { 132, 56 },
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/* IP6_STD (TYPE=110) */
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[VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1 },
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[VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128 },
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[VCAP_IS2_HK_IP6_L3_PROTO] = { 175, 8 },
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/* OAM (TYPE=111) */
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[VCAP_IS2_HK_OAM_MEL_FLAGS] = { 142, 7 },
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[VCAP_IS2_HK_OAM_VER] = { 149, 5 },
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[VCAP_IS2_HK_OAM_OPCODE] = { 154, 8 },
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[VCAP_IS2_HK_OAM_FLAGS] = { 162, 8 },
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[VCAP_IS2_HK_OAM_MEPID] = { 170, 16 },
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[VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = { 186, 1 },
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[VCAP_IS2_HK_OAM_IS_Y1731] = { 187, 1 },
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|
};
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|
|
EXPORT_SYMBOL(vsc7514_vcap_is2_keys);
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|
const struct vcap_field vsc7514_vcap_is2_actions[] = {
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|
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|
[VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1 },
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|
[VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1 },
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|
[VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3 },
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|
[VCAP_IS2_ACT_MASK_MODE] = { 5, 2 },
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|
[VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1 },
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[VCAP_IS2_ACT_LRN_DIS] = { 8, 1 },
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[VCAP_IS2_ACT_POLICE_ENA] = { 9, 1 },
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|
[VCAP_IS2_ACT_POLICE_IDX] = { 10, 9 },
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|
[VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1 },
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|
[VCAP_IS2_ACT_PORT_MASK] = { 20, 11 },
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|
[VCAP_IS2_ACT_REW_OP] = { 31, 9 },
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|
[VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1 },
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|
[VCAP_IS2_ACT_RSV] = { 41, 2 },
|
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|
|
[VCAP_IS2_ACT_ACL_ID] = { 43, 6 },
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|
|
[VCAP_IS2_ACT_HIT_CNT] = { 49, 32 },
|
|
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|
|
};
|
|
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|
|
EXPORT_SYMBOL(vsc7514_vcap_is2_actions);
|
