2022-05-31 18:04:11 +08:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
|
|
|
|
/*
|
|
|
|
|
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef _LOONGARCH_SETUP_H
|
|
|
|
|
#define _LOONGARCH_SETUP_H
|
|
|
|
|
|
|
|
|
|
#include <linux/types.h>
|
|
|
|
|
#include <uapi/asm/setup.h>
|
|
|
|
|
|
|
|
|
|
#define VECSIZE 0x200
|
|
|
|
|
|
|
|
|
|
extern unsigned long eentry;
|
|
|
|
|
extern unsigned long tlbrentry;
|
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:14 +08:00
|
|
|
extern void tlb_init(int cpu);
|
2022-05-31 18:04:11 +08:00
|
|
|
extern void cpu_cache_init(void);
|
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:14 +08:00
|
|
|
extern void cache_error_setup(void);
|
2022-05-31 18:04:11 +08:00
|
|
|
extern void per_cpu_trap_init(int cpu);
|
|
|
|
|
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
|
|
|
|
|
extern void set_merr_handler(unsigned long offset, void *addr, unsigned long len);
|
|
|
|
|
|
|
|
|
|
#endif /* __SETUP_H */
|
