Copy SmbiosPlatformDxe from Juno
This commit is contained in:
Zhuowei Zhang
parent
8e76e86bf4
commit
ea7f4efd1f
865
Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
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865
Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
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/** @file
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This driver installs SMBIOS information for ARM Juno platforms
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Copyright (c) 2015, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <ArmPlatform.h>
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#include <IndustryStandard/SmBios.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <PiDxe.h>
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#include <Protocol/Smbios.h>
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#define TYPE0_STRINGS \
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"EFI Development Kit II / ARM LTD\0" /* Vendor */ \
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"EDK II\0" /* BiosVersion */ \
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__DATE__"\0" /* BiosReleaseDate */
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#define TYPE1_STRINGS \
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"ARM LTD\0" /* Manufacturer */ \
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"ARM Juno Development Platform\0" /* Product Name */ \
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"None\0" /* Version */ \
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" \0" /* 20 character buffer */
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#define TYPE2_STRINGS \
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"ARM LTD\0" /* Manufacturer */ \
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"ARM Juno Development Platform\0" /* Product Name */ \
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"R0\0" /* Version */ \
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"Serial Not Set\0" /* Serial */ \
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"Base of Chassis\0" /* board location */ \
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"R1\0" /* Version */ \
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"R2\0" /* Version */
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#define TYPE3_STRINGS \
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"ARM LTD\0" /* Manufacturer */ \
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"None\0" /* Version */ \
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"Serial Not Set\0" /* Serial */
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#define TYPE4_STRINGS \
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"BGA-1156\0" /* socket type */ \
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"ARM LTD\0" /* manufactuer */ \
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"Cortex-A57\0" /* processor 1 description */ \
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"Cortex-A53\0" /* processor 2 description */ \
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"Cortex-A72\0" /* processor 2 description */ \
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"0xd03\0" /* A53 part number */ \
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"0xd07\0" /* A57 part number */ \
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"0xd08\0" /* A72 part number */
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#define TYPE7_STRINGS \
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"L1 Instruction\0" /* L1I */ \
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"L1 Data\0" /* L1D */ \
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"L2\0" /* L2 */
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#define TYPE9_STRINGS \
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"PCIE_SLOT0\0" /* Slot0 */ \
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"PCIE_SLOT1\0" /* Slot1 */ \
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"PCIE_SLOT2\0" /* Slot2 */ \
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"PCIE_SLOT3\0" /* Slot3 */
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#define TYPE16_STRINGS \
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"\0" /* nothing */
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#define TYPE17_STRINGS \
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"RIGHT SIDE\0" /* location */ \
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"BANK 0\0" /* bank description */
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#define TYPE19_STRINGS \
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"\0" /* nothing */
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#define TYPE32_STRINGS \
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"\0" /* nothing */
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//
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// Type definition and contents of the default SMBIOS table.
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// This table covers only the minimum structures required by
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// the SMBIOS specification (section 6.2, version 3.0)
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//
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#pragma pack(1)
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typedef struct {
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SMBIOS_TABLE_TYPE0 Base;
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INT8 Strings[sizeof(TYPE0_STRINGS)];
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} ARM_TYPE0;
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typedef struct {
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SMBIOS_TABLE_TYPE1 Base;
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UINT8 Strings[sizeof(TYPE1_STRINGS)];
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} ARM_TYPE1;
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typedef struct {
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SMBIOS_TABLE_TYPE2 Base;
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UINT8 Strings[sizeof(TYPE2_STRINGS)];
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} ARM_TYPE2;
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typedef struct {
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SMBIOS_TABLE_TYPE3 Base;
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UINT8 Strings[sizeof(TYPE3_STRINGS)];
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} ARM_TYPE3;
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typedef struct {
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SMBIOS_TABLE_TYPE4 Base;
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UINT8 Strings[sizeof(TYPE4_STRINGS)];
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} ARM_TYPE4;
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typedef struct {
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SMBIOS_TABLE_TYPE7 Base;
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UINT8 Strings[sizeof(TYPE7_STRINGS)];
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} ARM_TYPE7;
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typedef struct {
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SMBIOS_TABLE_TYPE9 Base;
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UINT8 Strings[sizeof(TYPE9_STRINGS)];
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} ARM_TYPE9;
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typedef struct {
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SMBIOS_TABLE_TYPE16 Base;
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UINT8 Strings[sizeof(TYPE16_STRINGS)];
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} ARM_TYPE16;
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typedef struct {
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SMBIOS_TABLE_TYPE17 Base;
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UINT8 Strings[sizeof(TYPE17_STRINGS)];
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} ARM_TYPE17;
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typedef struct {
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SMBIOS_TABLE_TYPE19 Base;
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UINT8 Strings[sizeof(TYPE19_STRINGS)];
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} ARM_TYPE19;
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typedef struct {
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SMBIOS_TABLE_TYPE32 Base;
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UINT8 Strings[sizeof(TYPE32_STRINGS)];
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} ARM_TYPE32;
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// SMBIOS tables often reference each other using
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// fixed constants, define a list of these constants
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// for our hardcoded tables
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enum SMBIOS_REFRENCE_HANDLES {
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SMBIOS_HANDLE_A57_L1I = 0x1000,
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SMBIOS_HANDLE_A57_L1D,
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SMBIOS_HANDLE_A57_L2,
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SMBIOS_HANDLE_A53_L1I,
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SMBIOS_HANDLE_A53_L1D,
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SMBIOS_HANDLE_A53_L2,
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SMBIOS_HANDLE_MOTHERBOARD,
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SMBIOS_HANDLE_CHASSIS,
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SMBIOS_HANDLE_A72_CLUSTER,
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SMBIOS_HANDLE_A57_CLUSTER,
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SMBIOS_HANDLE_A53_CLUSTER,
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SMBIOS_HANDLE_MEMORY,
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SMBIOS_HANDLE_DIMM
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};
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#define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure
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#pragma pack()
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// BIOS information (section 7.1)
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STATIC ARM_TYPE0 mArmDefaultType0 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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1, // SMBIOS_TABLE_STRING Vendor
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2, // SMBIOS_TABLE_STRING BiosVersion
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0xE800,// UINT16 BiosSegment
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3, // SMBIOS_TABLE_STRING BiosReleaseDate
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0, // UINT8 BiosSize
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{
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0,0,0,0,0,0,
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1, //PCI supported
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0,
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1, //PNP supported
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0,
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1, //BIOS upgradable
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0, 0, 0,
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1, //Boot from CD
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1, //selectable boot
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}, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics
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{ // BIOSCharacteristicsExtensionBytes[2]
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0x3,
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0xC,
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},
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0, // UINT8 SystemBiosMajorRelease
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0, // UINT8 SystemBiosMinorRelease
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0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease
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0xFF // UINT8 EmbeddedControllerFirmwareMinorRelease
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},
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// Text strings (unformatted area)
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TYPE0_STRINGS
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};
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// System information (section 7.2)
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STATIC CONST ARM_TYPE1 mArmDefaultType1 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,
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sizeof(SMBIOS_TABLE_TYPE1),
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SMBIOS_HANDLE_PI_RESERVED,
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},
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1, //Manufacturer
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2, //Product Name
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3, //Version
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4, //Serial
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{ 0x8a95d198, 0x7f46, 0x11e5, { 0xbf,0x8b,0x08,0x00,0x27,0x04,0xd4,0x8e }}, //UUID
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6, //Wakeup type
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0, //SKU
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0, //Family
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},
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// Text strings (unformatted)
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TYPE1_STRINGS
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};
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// Baseboard (section 7.3)
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STATIC ARM_TYPE2 mArmDefaultType2 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length
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SMBIOS_HANDLE_MOTHERBOARD,
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},
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1, //Manufacturer
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2, //Product Name
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3, //Version
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4, //Serial
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0, //Asset tag
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{1}, //motherboard, not replaceable
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5, //location of board
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SMBIOS_HANDLE_CHASSIS,
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BaseBoardTypeMotherBoard,
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1,
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{SMBIOS_HANDLE_A53_CLUSTER}, //,SMBIOS_HANDLE_A53_CLUSTER,SMBIOS_HANDLE_MEMORY},
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},
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TYPE2_STRINGS
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};
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// Enclosure
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STATIC CONST ARM_TYPE3 mArmDefaultType3 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length
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SMBIOS_HANDLE_CHASSIS,
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},
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1, //Manufacturer
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4, //enclosure type (low profile desktop)
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2, //version
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3, //serial
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0, //asset tag
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ChassisStateUnknown, //boot chassis state
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ChassisStateSafe, //power supply state
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ChassisStateSafe, //thermal state
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ChassisSecurityStatusNone, //security state
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{0,0,0,0,}, //OEM defined
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1, //1U height
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1, //number of power cords
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0, //no contained elements
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},
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TYPE3_STRINGS
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};
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// Processor
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STATIC CONST ARM_TYPE4 mArmDefaultType4_a72 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
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SMBIOS_HANDLE_A72_CLUSTER,
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},
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1, //socket type
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3, //processor type CPU
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ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
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2, //manufactuer
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{{0,},{0.}}, //processor id
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5, //version
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{0,0,0,0,0,1}, //voltage
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0, //external clock
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1200, //max speed
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1200, //current speed
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0x41, //status
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ProcessorUpgradeOther,
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SMBIOS_HANDLE_A57_L1I, //l1 cache handle
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SMBIOS_HANDLE_A57_L2, //l2 cache handle
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0xFFFF, //l3 cache handle
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0, //serial not set
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0, //asset not set
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8, //part number
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2, //core count in socket
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2, //enabled core count in socket
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0, //threads per socket
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0xEC, // processor characteristics
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ProcessorFamilyARM, //ARM core
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},
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TYPE4_STRINGS
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};
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STATIC CONST ARM_TYPE4 mArmDefaultType4_a57 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
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SMBIOS_HANDLE_A57_CLUSTER,
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},
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1, //socket type
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3, //processor type CPU
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ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
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2, //manufactuer
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{{0,},{0.}}, //processor id
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3, //version
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{0,0,0,0,0,1}, //voltage
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0, //external clock
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1200, //max speed
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1200, //current speed
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0x41, //status
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ProcessorUpgradeOther,
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SMBIOS_HANDLE_A57_L1I, //l1 cache handle
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SMBIOS_HANDLE_A57_L2, //l2 cache handle
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0xFFFF, //l3 cache handle
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0, //serial not set
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0, //asset not set
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7, //part number
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2, //core count in socket
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2, //enabled core count in socket
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0, //threads per socket
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0xEC, // processor characteristics
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ProcessorFamilyARM, //ARM core
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},
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TYPE4_STRINGS
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};
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STATIC CONST ARM_TYPE4 mArmDefaultType4_a53 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
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SMBIOS_HANDLE_A53_CLUSTER,
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},
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1, //socket type
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3, //processor type CPU
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ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
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2, //manufactuer
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{{0,},{0.}}, //processor id
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4, //version
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{0,0,0,0,0,1}, //voltage
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0, //external clock
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650, //max speed
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650, //current speed
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0x41, //status
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ProcessorUpgradeOther,
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SMBIOS_HANDLE_A53_L1I, //l1 cache handle
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SMBIOS_HANDLE_A53_L2, //l2 cache handle
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0xFFFF, //l3 cache handle
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0, //serial not set
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0, //asset not set
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6, //part number
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4, //core count in socket
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4, //enabled core count in socket
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0, //threads per socket
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0xEC, // processor characteristics
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ProcessorFamilyARM, //ARM core
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},
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TYPE4_STRINGS
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};
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// Cache
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STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1i = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A57_L1I,
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},
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1,
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0x380, //L1 enabled, unknown WB
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48, //48k i cache max
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48, //48k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //unkown speed
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CacheErrorParity, //parity checking
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CacheTypeInstruction, //instruction cache
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CacheAssociativityOther, //three way
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},
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TYPE7_STRINGS
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};
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STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1i = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A53_L1I,
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},
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1,
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0x380, //L1 enabled, unknown WB
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32, //32k i cache max
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32, //32k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //unkown speed
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CacheErrorParity, //parity checking
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CacheTypeInstruction, //instruction cache
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CacheAssociativity2Way, //two way
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},
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TYPE7_STRINGS
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};
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STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1d = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A57_L1D,
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},
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2,
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0x180, //L1 enabled, WB
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32, //32k d cache max
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32, //32k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //unkown speed
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CacheErrorSingleBit, //ECC checking
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CacheTypeData, //instruction cache
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CacheAssociativity2Way, //two way associative
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},
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TYPE7_STRINGS
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};
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STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1d = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A53_L1D,
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},
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2,
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0x180, //L1 enabled, WB
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32, //32k d cache max
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32, //32k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //unkown speed
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CacheErrorSingleBit, //ECC checking
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CacheTypeData, //instruction cache
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CacheAssociativity4Way, //four way associative
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},
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TYPE7_STRINGS
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};
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STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l2 = {
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{
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A57_L2,
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},
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3,
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0x181, //L2 enabled, WB
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2048, //2M d cache max
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2048, //2M installed
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{0,1}, //SRAM type
|
||||
{0,1}, //SRAM type
|
||||
0, //unkown speed
|
||||
CacheErrorSingleBit, //ECC checking
|
||||
CacheTypeUnified, //instruction cache
|
||||
CacheAssociativity16Way, //16 way associative
|
||||
},
|
||||
TYPE7_STRINGS
|
||||
};
|
||||
|
||||
STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l2 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
|
||||
SMBIOS_HANDLE_A53_L2,
|
||||
},
|
||||
3,
|
||||
0x181, //L2 enabled, WB
|
||||
1024, //1M D cache max
|
||||
1024, //1M installed
|
||||
{0,1}, //SRAM type
|
||||
{0,1}, //SRAM type
|
||||
0, //unkown speed
|
||||
CacheErrorSingleBit, //ECC checking
|
||||
CacheTypeUnified, //instruction cache
|
||||
CacheAssociativity16Way, //16 way associative
|
||||
},
|
||||
TYPE7_STRINGS
|
||||
};
|
||||
|
||||
// Slots
|
||||
STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
|
||||
SMBIOS_HANDLE_PI_RESERVED,
|
||||
},
|
||||
1, //slot 0
|
||||
SlotTypePciExpressGen2X4,
|
||||
SlotDataBusWidth1X,
|
||||
SlotUsageUnknown,
|
||||
SlotLengthShort,
|
||||
0,
|
||||
{1}, //unknown
|
||||
{1,0,1}, //PME and SMBUS
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
},
|
||||
TYPE9_STRINGS
|
||||
};
|
||||
|
||||
STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
|
||||
SMBIOS_HANDLE_PI_RESERVED,
|
||||
},
|
||||
1, //slot 0
|
||||
SlotTypePciExpressGen2X4,
|
||||
SlotDataBusWidth1X,
|
||||
SlotUsageUnknown,
|
||||
SlotLengthShort,
|
||||
0,
|
||||
{1},
|
||||
{1,0,1}, //PME and SMBUS
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
},
|
||||
TYPE9_STRINGS
|
||||
};
|
||||
|
||||
STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
|
||||
SMBIOS_HANDLE_PI_RESERVED,
|
||||
},
|
||||
1, //slot 0
|
||||
SlotTypePciExpressGen2X8,
|
||||
SlotDataBusWidth4X,
|
||||
SlotUsageUnknown,
|
||||
SlotLengthShort,
|
||||
0,
|
||||
{1},
|
||||
{1,0,1}, //PME and SMBUS
|
||||
0,
|
||||
2,
|
||||
3,
|
||||
},
|
||||
TYPE9_STRINGS
|
||||
};
|
||||
|
||||
STATIC CONST ARM_TYPE9 mArmDefaultType9_3 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
|
||||
SMBIOS_HANDLE_PI_RESERVED,
|
||||
},
|
||||
1, //slot 0
|
||||
SlotTypePciExpressGen2X16,
|
||||
SlotDataBusWidth4X,
|
||||
SlotUsageUnknown,
|
||||
SlotLengthShort,
|
||||
0,
|
||||
{1},
|
||||
{1,0,1}, //PME and SMBUS
|
||||
0,
|
||||
2,
|
||||
0xc,
|
||||
},
|
||||
TYPE9_STRINGS
|
||||
};
|
||||
|
||||
// Memory array
|
||||
STATIC CONST ARM_TYPE16 mArmDefaultType16 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length
|
||||
SMBIOS_HANDLE_MEMORY,
|
||||
},
|
||||
MemoryArrayLocationSystemBoard, //on motherboard
|
||||
MemoryArrayUseSystemMemory, //system RAM
|
||||
MemoryErrorCorrectionNone, //Juno doesn't have ECC RAM
|
||||
0x800000, //8GB
|
||||
0xFFFE, //No error information structure
|
||||
0x1, //soldered memory
|
||||
},
|
||||
TYPE16_STRINGS
|
||||
};
|
||||
|
||||
// Memory device
|
||||
STATIC CONST ARM_TYPE17 mArmDefaultType17 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
|
||||
SMBIOS_HANDLE_DIMM,
|
||||
},
|
||||
SMBIOS_HANDLE_MEMORY, //array to which this module belongs
|
||||
0xFFFE, //no errors
|
||||
64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
|
||||
64, //data width of this device (64-bits)
|
||||
0x2000, //8GB
|
||||
0x0B, //row of chips
|
||||
0, //not part of a set
|
||||
1, //right side of board
|
||||
2, //bank 0
|
||||
// MemoryTypeLpddr3, //LP DDR3, isn't defined yet
|
||||
MemoryTypeDdr3, //LP DDR3
|
||||
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered
|
||||
1600, //1600Mhz DDR
|
||||
0, //varies between diffrent production runs
|
||||
0, //serial
|
||||
0, //asset tag
|
||||
0, //part number
|
||||
0, //rank
|
||||
},
|
||||
TYPE17_STRINGS
|
||||
};
|
||||
|
||||
// Memory array mapped address, this structure
|
||||
// is overridden by InstallMemoryStructure
|
||||
STATIC CONST ARM_TYPE19 mArmDefaultType19 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length
|
||||
SMBIOS_HANDLE_PI_RESERVED,
|
||||
},
|
||||
0xFFFFFFFF, //invalid, look at extended addr field
|
||||
0xFFFFFFFF,
|
||||
SMBIOS_HANDLE_DIMM, //handle
|
||||
1,
|
||||
0x080000000, //starting addr of first 2GB
|
||||
0x100000000, //ending addr of first 2GB
|
||||
},
|
||||
TYPE19_STRINGS
|
||||
};
|
||||
|
||||
// System boot info
|
||||
STATIC CONST ARM_TYPE32 mArmDefaultType32 = {
|
||||
{
|
||||
{ // SMBIOS_STRUCTURE Hdr
|
||||
EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type
|
||||
sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length
|
||||
SMBIOS_HANDLE_PI_RESERVED,
|
||||
},
|
||||
{0,0,0,0,0,0}, //reserved
|
||||
BootInformationStatusNoError,
|
||||
},
|
||||
TYPE32_STRINGS
|
||||
};
|
||||
|
||||
STATIC CONST VOID *DefaultCommonTables[]=
|
||||
{
|
||||
&mArmDefaultType0,
|
||||
&mArmDefaultType1,
|
||||
&mArmDefaultType2,
|
||||
&mArmDefaultType3,
|
||||
&mArmDefaultType7_a53_l1i,
|
||||
&mArmDefaultType7_a53_l1d,
|
||||
&mArmDefaultType7_a53_l2,
|
||||
&mArmDefaultType4_a53,
|
||||
&mArmDefaultType9_0,
|
||||
&mArmDefaultType9_1,
|
||||
&mArmDefaultType9_2,
|
||||
&mArmDefaultType9_3,
|
||||
&mArmDefaultType16,
|
||||
&mArmDefaultType17,
|
||||
// &mArmDefaultType19, //memory range type 19 dynamically generated
|
||||
&mArmDefaultType32,
|
||||
NULL
|
||||
};
|
||||
|
||||
STATIC CONST VOID *DefaultTablesR0R1[]=
|
||||
{
|
||||
&mArmDefaultType7_a57_l1i,
|
||||
&mArmDefaultType7_a57_l1d,
|
||||
&mArmDefaultType7_a57_l2,
|
||||
&mArmDefaultType4_a57,
|
||||
NULL
|
||||
};
|
||||
|
||||
STATIC CONST VOID *DefaultTablesR2[]=
|
||||
{
|
||||
&mArmDefaultType7_a57_l1i, // Cache layout is the same on the A72 vs A57
|
||||
&mArmDefaultType7_a57_l1d,
|
||||
&mArmDefaultType7_a57_l2,
|
||||
&mArmDefaultType4_a72,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
Installs a memory descriptor (type19) for the given address range
|
||||
|
||||
@param Smbios SMBIOS protocol
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
InstallMemoryStructure (
|
||||
IN EFI_SMBIOS_PROTOCOL *Smbios,
|
||||
IN UINT64 StartingAddress,
|
||||
IN UINT64 RegionLength
|
||||
)
|
||||
{
|
||||
EFI_SMBIOS_HANDLE SmbiosHandle;
|
||||
ARM_TYPE19 MemoryDescriptor;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
CopyMem( &MemoryDescriptor, &mArmDefaultType19, sizeof(ARM_TYPE19));
|
||||
|
||||
MemoryDescriptor.Base.ExtendedStartingAddress = StartingAddress;
|
||||
MemoryDescriptor.Base.ExtendedEndingAddress = StartingAddress+RegionLength;
|
||||
SmbiosHandle = MemoryDescriptor.Base.Hdr.Handle;
|
||||
|
||||
Status = Smbios->Add (
|
||||
Smbios,
|
||||
NULL,
|
||||
&SmbiosHandle,
|
||||
(EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor
|
||||
);
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
Install a whole table worth of structructures
|
||||
|
||||
@parm
|
||||
**/
|
||||
EFI_STATUS
|
||||
InstallStructures (
|
||||
IN EFI_SMBIOS_PROTOCOL *Smbios,
|
||||
IN CONST VOID *DefaultTables[]
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
EFI_SMBIOS_HANDLE SmbiosHandle;
|
||||
|
||||
int TableEntry;
|
||||
for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++)
|
||||
{
|
||||
SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle;
|
||||
Status = Smbios->Add (
|
||||
Smbios,
|
||||
NULL,
|
||||
&SmbiosHandle,
|
||||
(EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry]
|
||||
);
|
||||
if (EFI_ERROR(Status))
|
||||
break;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Install all structures from the DefaultTables structure
|
||||
|
||||
@param Smbios SMBIOS protocol
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
InstallAllStructures (
|
||||
IN EFI_SMBIOS_PROTOCOL *Smbios
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
UINT32 JunoRevision;
|
||||
VOID *ExtraTables = DefaultTablesR0R1;
|
||||
|
||||
GetJunoRevision(JunoRevision);
|
||||
|
||||
// Fixup some table values
|
||||
mArmDefaultType0.Base.SystemBiosMajorRelease = (PcdGet32 ( PcdFirmwareRevision ) >> 16) & 0xFF;
|
||||
mArmDefaultType0.Base.SystemBiosMinorRelease = PcdGet32 ( PcdFirmwareRevision ) & 0xFF;
|
||||
if ( JunoRevision == JUNO_REVISION_R1 )
|
||||
{
|
||||
mArmDefaultType2.Base.Version = 6;
|
||||
}
|
||||
else if ( JunoRevision == JUNO_REVISION_R2 )
|
||||
{
|
||||
mArmDefaultType2.Base.Version = 7;
|
||||
ExtraTables=DefaultTablesR2;
|
||||
}
|
||||
|
||||
//
|
||||
// Add all Juno table entries
|
||||
//
|
||||
Status=InstallStructures (Smbios,DefaultCommonTables);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status=InstallStructures (Smbios,ExtraTables);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
// Generate memory descriptors for the two memory ranges we know about
|
||||
Status = InstallMemoryStructure ( Smbios, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemorySize));
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
Status = InstallMemoryStructure ( Smbios, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
Installs SMBIOS information for ARM platforms
|
||||
|
||||
@param ImageHandle Module's image handle
|
||||
@param SystemTable Pointer of EFI_SYSTEM_TABLE
|
||||
|
||||
@retval EFI_SUCCESS Smbios data successfully installed
|
||||
@retval Other Smbios data was not installed
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SmbiosTablePublishEntry (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_SMBIOS_PROTOCOL *Smbios;
|
||||
|
||||
//
|
||||
// Find the SMBIOS protocol
|
||||
//
|
||||
Status = gBS->LocateProtocol (
|
||||
&gEfiSmbiosProtocolGuid,
|
||||
NULL,
|
||||
(VOID**)&Smbios
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = InstallAllStructures (Smbios);
|
||||
|
||||
return Status;
|
||||
}
|
||||
68
Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
Normal file
68
Pixel3XL/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
Normal file
@ -0,0 +1,68 @@
|
||||
## @file
|
||||
# This driver installs SMBIOS information for ArmJuno
|
||||
#
|
||||
# Copyright (c) 2011, Bei Guan <gbtju85@gmail.com>
|
||||
# Copyright (c) 2011, Intel Corporation. All rights reserved.
|
||||
# Copyright (c) 2015, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = SmbiosPlatformDxe
|
||||
FILE_GUID = 4110465d-5ff3-4f4b-b580-24ed0d06747a
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = SmbiosTablePublishEntry
|
||||
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = AARCH64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
SmbiosPlatformDxe.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
Platform/ARM/JunoPkg/ArmJuno.dec
|
||||
|
||||
[LibraryClasses]
|
||||
ArmLib
|
||||
BaseMemoryLib
|
||||
BaseLib
|
||||
DebugLib
|
||||
HobLib
|
||||
IoLib
|
||||
MemoryAllocationLib
|
||||
PcdLib
|
||||
UefiBootServicesTableLib
|
||||
UefiDriverEntryPoint
|
||||
|
||||
[Guids]
|
||||
gEfiGlobalVariableGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision
|
||||
|
||||
[Protocols]
|
||||
gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
|
||||
|
||||
[Guids]
|
||||
|
||||
[Depex]
|
||||
gEfiSmbiosProtocolGuid
|
||||
Loading…
Reference in New Issue
Block a user