initial bringup
Signed-off-by: Ivaylo Ivanov <ivo.ivanov@null.net>
This commit is contained in:
Ivaylo Ivanov
parent
1cf3e94ab3
commit
c75269db6e
@ -34,19 +34,17 @@ SerialPortInitialize (
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VOID
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)
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{
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#if 0
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UINT8* base = (UINT8*)0xa1a10000ull;
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UINT8* base = (UINT8*)0x8d100000ull;
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for (UINTN i = 0; i < 0x200000; i++) {
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base[i] = 0;
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}
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#endif
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return RETURN_SUCCESS;
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}
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static void mem_putchar(UINT8 c) {
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static const UINTN size = 0x200000;
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static UINTN offset = 0;
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UINT8* base = (UINT8*)0xa1a10000ull;
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UINT8* base = (UINT8*)0x8d100000ull;
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base[offset++] = c;
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if (offset >= size) {
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offset = 0;
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@ -18,31 +18,7 @@
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.align 3
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ASM_FUNC(ArmPlatformPeiBootAction)
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startlabel:
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// check if we're located at expected location
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adr x4, .
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ldr x5, =ArmPlatformPeiBootAction
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cmp x4, x5
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bne docopy
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ret
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docopy:
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// find our start address by getting our expected offset, then subtracting it from our actual address
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ldr x6, =FixedPcdGet64 (PcdFdBaseAddress)
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sub x5, x5, x6 // x5 now holds offset of ArmPlatformPeiBootAction from start of FD base
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sub x4, x4, x5 // x4 now holds address of actual FD base
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// tweak the return address
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// note: x30 is lr; gcc5 doesn't have the alias
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sub x30, x30, x4
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add x30, x30, x6
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ldr x5, =FixedPcdGet64 (PcdFdSize)
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// crap memcpy
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loop:
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ldp x2, x3, [x4], #16
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stp x2, x3, [x6], #16
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subs x5, x5, #16
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b.ne loop
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ret
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.ltorg
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//UINTN
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//ArmPlatformIsPrimaryCore (
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@ -27,7 +27,7 @@
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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#define SDM845_PERIPH_BASE 0x00000000
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#define SDM845_PERIPH_SZ 0x80000000
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#define SDM845_PERIPH_SZ 0x60000000
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#define HIKEY960_MEMORY_SIZE 0x0000000100000000
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@ -35,10 +35,17 @@ STATIC struct Pixel3XLReservedMemory {
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EFI_PHYSICAL_ADDRESS Offset;
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EFI_PHYSICAL_ADDRESS Size;
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} Pixel3XLReservedMemoryBuffer [] = {
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{ 0x85700000, 0x00600000 }, // hyp_region
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{ 0x85e00000, 0x00100000 }, // xbl_region
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{ 0x85fc0000, 0x02f40000 }, // removed_region
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{ 0x8ab00000, 0x01400000 }, // qseecom_region
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/** { 0x86000000, 0x00300000 }, // tz_apps_region
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{ 0x86300000, 0x00100000 }, // smem_region
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{ 0x86400000, 0x00280000 }, // tz/hyp_region
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{ 0x86700000, 0x06C00000 }, // MPSS/EFS/DHMS/PIL_region
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**/
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/*
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{ 0x85A00000, 0x00E00000 }, // tz-apps_region
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{ 0x86800000, 0x05400000 }, // mpss_region
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{ 0x8bc00000, 0x00200000 }, // gps_region
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{ 0x8be00000, 0x00600000 }, // wcnss_region
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{ 0x8c400000, 0x00600000 }, // venus_region*/
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};
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/**
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@ -33,7 +33,7 @@
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[PcdsFixedAtBuild.common]
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# Simple FrameBuffer
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress|0x00400000|UINT32|0x0000a400
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress|0x00400000|UINT32|0x0000a400 # 0x7C400000
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferWidth|1080|UINT32|0x0000a401
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferHeight|1920|UINT32|0x0000a402
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferPixelBpp|32|UINT32|0x0000a403
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@ -93,9 +93,9 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
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# System Memory (4GB)
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# System Memory (1.5GB)
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
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gArmTokenSpaceGuid.PcdSystemMemorySize|0xe0000000
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gArmTokenSpaceGuid.PcdSystemMemorySize|0x60000000
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# We only boot one processor here!
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gArmPlatformTokenSpaceGuid.PcdCoreCount|1
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@ -108,8 +108,8 @@
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#
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# ARM General Interrupt Controller
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0x17a00000
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gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x17a60000
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gArmTokenSpaceGuid.PcdGicDistributorBase|0x0b000000
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0b002000
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x12
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gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x13
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@ -133,9 +133,9 @@
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9d400000
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferWidth|1440
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferHeight|2960
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferAddress|0x8e000000
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferWidth|720
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gPixel3XLTokenSpaceGuid.PcdMipiFrameBufferHeight|1280
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
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@ -25,7 +25,7 @@
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################################################################################
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[FD.PIXEL3XL_UEFI]
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BaseAddress = 0xd0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
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BaseAddress = 0x80080000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
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Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
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ErasePolarity = 1
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@ -43,6 +43,7 @@ InitPeripherals (
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IN VOID
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)
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{
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// MmioWrite32(0x004ab000, 0);
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/* This also crashes. Do you really hate memory attributes or something?
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EFI_STATUS Status;
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// https://lists.01.org/pipermail/edk2-devel/2017-August/013417.html
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24
basic.dts
Normal file
24
basic.dts
Normal file
@ -0,0 +1,24 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/dts-v1/;
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/ {
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// This is used by the bootloader to find the correct DTB
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qcom,msm-id = <206 0>; // qcom,msm-id = <247 0>; for APQ8016
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qcom,board-id = <0xCE08FF01 5>; /* FIXME: Check your downstream device tree */
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model = "Samsung Galaxy J5 2015"; // FIXME
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compatible = "samsung,j500f", "qcom,msm8916"; // FIXME
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#address-cells = <2>;
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#size-cells = <2>;
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// The bootloader gets really sad if it cannot find those nodes
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chosen { };
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memory@0 {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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};
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2
build.sh
2
build.sh
@ -5,4 +5,4 @@ set -e
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# not actually GCC5; it's GCC7 on Ubuntu 18.04.
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GCC5_AARCH64_PREFIX=aarch64-linux-gnu- build -s -n 0 -a AARCH64 -t GCC5 -p Pixel3XL/Pixel3XL.dsc
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gzip -c < workspace/Build/Pixel3XL/DEBUG_GCC5/FV/PIXEL3XL_UEFI.fd >uefi.img
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cat crosshatch.dtb >>uefi.img
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cat j5.dtb >>uefi.img
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