[ADD] Temporary binary opcodes
[FIX] Reading and writing to non-existing port does not cause interrupt now
[FIX] Port bus failure is interrupt #8 now (instead of #10)
[FIX] Reading from non-existing port is now #10 instead of #8
[FIX] Increased max CPU frequency
[FIX] Fixed bug when setting frequency over limit does not set it to maximum allowed value
[FIX] Removed debug message in constant gate
[FIX] CPU now sends packets with more bandwidth and speed in SP (bandwidth only in MP). Uploading 70KB now takes 3-5 seconds
[TEMP FIX] Multiply "CPU Upload complete" messages
[ADD] Presets in address bus
[ADD] wire_cpu_dumpcode convar, set it to "enable" to enable dumping some debug information (pointers to functions and variables, code listing with corresponding byte addresses, and raw bytes dump)
[ADD] Supports filenames without extension now
[ADD] More information for user about CPU upload status
[ADD] CVAR: wire_cpu_packet_bandwidth (size of each packet, def. 50). It seems that it's reliable to use bandwidth of 100, but not tested in MP (twice the less time needed for uploading program)
[ADD] CVAR: wire_cpu_packet_rate_sp (data rate in SP, def. 0.1)
[ADD] CVAR: wire_cpu_packet_rate_mp (data rate in MP, def. 0.4)
[FIX] Parameters handled as strings
[FIX] Precision fixed (at least floating point digits precision, 14-15 digits actual precision)
[FIX] TPG now sets CMPR to address of error instead of next page address (you cant read cmpr anyway)
[FIX] CPU upload status not displaying in MP
added desc field to outputs (for value chip use)
fixed sorting outputs on wire tool (first output is now first, not last)
changed indicator overlay text to format value as % instead of a factor (it was confusing)
