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std.Target: Remove the r600 arch tag.

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These are quite old GPUs, and it is unlikely that Zig will ever be able to
target them.

See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series
This commit is contained in:
Alex Rønne Petersen 2024-07-21 14:04:52 +02:00
parent 9848623e62
commit c825b567b2
No known key found for this signature in database
8 changed files with 0 additions and 19 deletions
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3
lib/compiler/aro/aro/target.zig vendored
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@ -470,7 +470,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparc,
.sparcel,
@ -527,7 +526,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.lanai,
.m68k,
.msp430,
.r600,
.shave,
.sparcel,
.spu_2,
@ -616,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.powerpcle => "powerpcle",
.powerpc64 => "powerpc64",
.powerpc64le => "powerpc64le",
.r600 => "r600",
.amdgcn => "amdgcn",
.riscv32 => "riscv32",
.riscv64 => "riscv64",

8
lib/std/Target.zig
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@ -994,7 +994,6 @@ pub const Cpu = struct {
powerpcle,
powerpc64,
powerpc64le,
r600,
amdgcn,
riscv32,
riscv64,
@ -1146,7 +1145,6 @@ pub const Cpu = struct {
.mips => .MIPS,
.mipsel => .MIPS_RS3_LE,
.powerpc, .powerpcle => .PPC,
.r600 => .NONE,
.riscv32 => .RISCV,
.sparc => .SPARC,
.sparcel => .SPARC,
@ -1208,7 +1206,6 @@ pub const Cpu = struct {
.mips => .Unknown,
.mipsel => .Unknown,
.powerpc, .powerpcle => .POWERPC,
.r600 => .Unknown,
.riscv32 => .RISCV32,
.sparc => .Unknown,
.sparcel => .Unknown,
@ -1282,7 +1279,6 @@ pub const Cpu = struct {
.tcele,
.powerpcle,
.powerpc64le,
.r600,
.riscv32,
.riscv64,
.x86,
@ -1772,7 +1768,6 @@ pub const DynamicLinker = struct {
.hexagon,
.m68k,
.msp430,
.r600,
.amdgcn,
.tce,
.tcele,
@ -1874,7 +1869,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparcel,
.tce,
@ -2436,7 +2430,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.lanai,
.nvptx,
.nvptx64,
.r600,
.s390x,
.spir64,
.spirv64,
@ -2560,7 +2553,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.lanai,
.nvptx,
.nvptx64,
.r600,
.s390x,
.spir64,
.spirv64,

1
src/Type.zig
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@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.amdgcn,
.riscv32,
.sparc,

1
src/Zcu.zig
View File

@ -3246,7 +3246,6 @@ pub fn atomicPtrAlignment(
.nvptx,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparc,
.sparcel,

3
src/codegen/llvm.zig
View File

@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.powerpcle => "powerpcle",
.powerpc64 => "powerpc64",
.powerpc64le => "powerpc64le",
.r600 => "r600",
.amdgcn => "amdgcn",
.riscv32 => "riscv32",
.riscv64 => "riscv64",
@ -287,7 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.powerpcle => .ppcle,
.powerpc64 => .ppc64,
.powerpc64le => .ppc64le,
.r600 => .r600,
.amdgcn => .amdgcn,
.riscv32 => .riscv32,
.riscv64 => .riscv64,
@ -12090,7 +12088,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
// LLVM backends that have no initialization functions.
.tce,
.tcele,
.r600,
.amdil,
.amdil64,
.hsail,

1
src/target.zig
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@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.powerpcle,
.powerpc64,
.powerpc64le,
.r600,
.amdgcn,
.riscv32,
.riscv64,

1
test/behavior/align.zig
View File

@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.amdgcn,
.riscv32,
.sparc,

1
test/llvm_targets.zig
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@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{
.{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl },
.{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none },
//.{ .cpu_arch = .r600, .os_tag = .mesa3d, .abi = .none },
.{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none },
.{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
.{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },