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ctz + clz
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@ -1907,9 +1907,11 @@ struct ZigLLVMFnKey {
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union {
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struct {
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uint32_t bit_count;
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uint32_t vector_len; // 0 means not a vector
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} ctz;
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struct {
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uint32_t bit_count;
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uint32_t vector_len; // 0 means not a vector
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} clz;
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struct {
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uint32_t bit_count;
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@ -7883,9 +7883,11 @@ bool type_id_eql(TypeId const *a, TypeId const *b) {
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uint32_t zig_llvm_fn_key_hash(ZigLLVMFnKey const *x) {
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switch (x->id) {
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case ZigLLVMFnIdCtz:
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return (uint32_t)(x->data.ctz.bit_count) * (uint32_t)810453934;
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return (uint32_t)(x->data.ctz.bit_count) * (uint32_t)810453934 +
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(uint32_t)(x->data.ctz.vector_len) * (((uint32_t)x->id << 5) + 1025);
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case ZigLLVMFnIdClz:
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return (uint32_t)(x->data.clz.bit_count) * (uint32_t)2428952817;
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return (uint32_t)(x->data.clz.bit_count) * (uint32_t)2428952817 +
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(uint32_t)(x->data.clz.vector_len) * (((uint32_t)x->id << 5) + 1025);
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case ZigLLVMFnIdPopCount:
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return (uint32_t)(x->data.pop_count.bit_count) * (uint32_t)101195049 +
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(uint32_t)(x->data.pop_count.vector_len) * (((uint32_t)x->id << 5) + 1025);
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@ -15945,54 +15945,154 @@ static Stage1AirInst *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira,
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}
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static Stage1AirInst *ir_analyze_instruction_ctz(IrAnalyze *ira, Stage1ZirInstCtz *instruction) {
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Error err;
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ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
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if (type_is_invalid(int_type))
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return ira->codegen->invalid_inst_gen;
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Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
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Stage1AirInst *uncasted_op = instruction->op->child;
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if (type_is_invalid(uncasted_op->value->type))
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return ira->codegen->invalid_inst_gen;
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uint32_t vector_len = UINT32_MAX; // means not a vector
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if (uncasted_op->value->type->id == ZigTypeIdArray) {
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bool can_be_vec_elem;
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if ((err = is_valid_vector_elem_type(ira->codegen, uncasted_op->value->type->data.array.child_type,
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&can_be_vec_elem)))
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{
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return ira->codegen->invalid_inst_gen;
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}
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if (can_be_vec_elem) {
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vector_len = uncasted_op->value->type->data.array.len;
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}
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} else if (uncasted_op->value->type->id == ZigTypeIdVector) {
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vector_len = uncasted_op->value->type->data.vector.len;
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}
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bool is_vector = (vector_len != UINT32_MAX);
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ZigType *op_type = is_vector ? get_vector_type(ira->codegen, vector_len, int_type) : int_type;
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Stage1AirInst *op = ir_implicit_cast(ira, uncasted_op, op_type);
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if (type_is_invalid(op->value->type))
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return ira->codegen->invalid_inst_gen;
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if (int_type->data.integral.bit_count == 0)
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return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, 0);
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ZigType *smallest_type = get_smallest_unsigned_int_type(ira->codegen, int_type->data.integral.bit_count);
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if (instr_is_comptime(op)) {
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ZigValue *val = ir_resolve_const(ira, op, UndefOk);
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if (val == nullptr)
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return ira->codegen->invalid_inst_gen;
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if (val->special == ConstValSpecialUndef)
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return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
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size_t result_usize = bigint_ctz(&op->value->data.x_bigint, int_type->data.integral.bit_count);
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return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, result_usize);
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if (is_vector) {
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ZigType *smallest_vec_type = get_vector_type(ira->codegen, vector_len, smallest_type);
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Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, smallest_vec_type);
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expand_undef_array(ira->codegen, val);
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result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(smallest_vec_type->data.vector.len);
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for (unsigned i = 0; i < smallest_vec_type->data.vector.len; i += 1) {
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ZigValue *op_elem_val = &val->data.x_array.data.s_none.elements[i];
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if ((err = ir_resolve_const_val(ira->codegen, ira->new_irb.exec, instruction->base.source_node,
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op_elem_val, UndefOk)))
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{
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return ira->codegen->invalid_inst_gen;
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}
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ZigValue *result_elem_val = &result->value->data.x_array.data.s_none.elements[i];
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result_elem_val->type = smallest_type;
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result_elem_val->special = op_elem_val->special;
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if (op_elem_val->special == ConstValSpecialUndef)
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continue;
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size_t value = bigint_ctz(&op_elem_val->data.x_bigint, int_type->data.integral.bit_count);
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bigint_init_unsigned(&result->value->data.x_array.data.s_none.elements[i].data.x_bigint, value);
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}
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return result;
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} else {
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size_t result_usize = bigint_ctz(&op->value->data.x_bigint, int_type->data.integral.bit_count);
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return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, result_usize);
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}
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}
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ZigType *return_type = get_smallest_unsigned_int_type(ira->codegen, int_type->data.integral.bit_count);
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ZigType *return_type = is_vector ? get_vector_type(ira->codegen, vector_len, smallest_type) : smallest_type;
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return ir_build_ctz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
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}
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static Stage1AirInst *ir_analyze_instruction_clz(IrAnalyze *ira, Stage1ZirInstClz *instruction) {
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Error err;
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ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child);
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if (type_is_invalid(int_type))
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return ira->codegen->invalid_inst_gen;
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Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type);
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Stage1AirInst *uncasted_op = instruction->op->child;
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if (type_is_invalid(uncasted_op->value->type))
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return ira->codegen->invalid_inst_gen;
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uint32_t vector_len = UINT32_MAX; // means not a vector
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if (uncasted_op->value->type->id == ZigTypeIdArray) {
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bool can_be_vec_elem;
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if ((err = is_valid_vector_elem_type(ira->codegen, uncasted_op->value->type->data.array.child_type,
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&can_be_vec_elem)))
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{
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return ira->codegen->invalid_inst_gen;
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}
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if (can_be_vec_elem) {
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vector_len = uncasted_op->value->type->data.array.len;
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}
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} else if (uncasted_op->value->type->id == ZigTypeIdVector) {
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vector_len = uncasted_op->value->type->data.vector.len;
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}
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bool is_vector = (vector_len != UINT32_MAX);
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ZigType *op_type = is_vector ? get_vector_type(ira->codegen, vector_len, int_type) : int_type;
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Stage1AirInst *op = ir_implicit_cast(ira, uncasted_op, op_type);
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if (type_is_invalid(op->value->type))
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return ira->codegen->invalid_inst_gen;
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if (int_type->data.integral.bit_count == 0)
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return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, 0);
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ZigType *smallest_type = get_smallest_unsigned_int_type(ira->codegen, int_type->data.integral.bit_count);
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if (instr_is_comptime(op)) {
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ZigValue *val = ir_resolve_const(ira, op, UndefOk);
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if (val == nullptr)
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return ira->codegen->invalid_inst_gen;
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if (val->special == ConstValSpecialUndef)
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return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int);
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size_t result_usize = bigint_clz(&op->value->data.x_bigint, int_type->data.integral.bit_count);
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return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, result_usize);
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if (is_vector) {
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ZigType *smallest_vec_type = get_vector_type(ira->codegen, vector_len, smallest_type);
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Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, smallest_vec_type);
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expand_undef_array(ira->codegen, val);
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result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate<ZigValue>(smallest_vec_type->data.vector.len);
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for (unsigned i = 0; i < smallest_vec_type->data.vector.len; i += 1) {
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ZigValue *op_elem_val = &val->data.x_array.data.s_none.elements[i];
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if ((err = ir_resolve_const_val(ira->codegen, ira->new_irb.exec, instruction->base.source_node,
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op_elem_val, UndefOk)))
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{
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return ira->codegen->invalid_inst_gen;
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}
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ZigValue *result_elem_val = &result->value->data.x_array.data.s_none.elements[i];
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result_elem_val->type = smallest_type;
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result_elem_val->special = op_elem_val->special;
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if (op_elem_val->special == ConstValSpecialUndef)
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continue;
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size_t value = bigint_clz(&op_elem_val->data.x_bigint, int_type->data.integral.bit_count);
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bigint_init_unsigned(&result->value->data.x_array.data.s_none.elements[i].data.x_bigint, value);
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}
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return result;
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} else {
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size_t result_usize = bigint_clz(&op->value->data.x_bigint, int_type->data.integral.bit_count);
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return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, result_usize);
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}
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}
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ZigType *return_type = get_smallest_unsigned_int_type(ira->codegen, int_type->data.integral.bit_count);
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ZigType *return_type = is_vector ? get_vector_type(ira->codegen, vector_len, smallest_type) : smallest_type;
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return ir_build_clz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op);
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}
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@ -123,16 +123,27 @@ test "@clz" {
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}
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fn testClz() !void {
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try expect(clz(u8, 0b10001010) == 0);
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try expect(clz(u8, 0b00001010) == 4);
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try expect(clz(u8, 0b00011010) == 3);
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try expect(clz(u8, 0b00000000) == 8);
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try expect(clz(u128, 0xffffffffffffffff) == 64);
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try expect(clz(u128, 0x10000000000000000) == 63);
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try expect(@clz(u8, 0b10001010) == 0);
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try expect(@clz(u8, 0b00001010) == 4);
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try expect(@clz(u8, 0b00011010) == 3);
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try expect(@clz(u8, 0b00000000) == 8);
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try expect(@clz(u128, 0xffffffffffffffff) == 64);
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try expect(@clz(u128, 0x10000000000000000) == 63);
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}
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fn clz(comptime T: type, x: T) usize {
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return @clz(T, x);
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test "@clz vectors" {
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try testClzVectors();
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comptime try testClzVectors();
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}
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fn testClzVectors() !void {
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@setEvalBranchQuota(10_000);
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try expectEqual(@clz(u8, @splat(64, @as(u8, 0b10001010))), @splat(64, @as(u4, 0)));
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try expectEqual(@clz(u8, @splat(64, @as(u8, 0b00001010))), @splat(64, @as(u4, 4)));
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try expectEqual(@clz(u8, @splat(64, @as(u8, 0b00011010))), @splat(64, @as(u4, 3)));
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try expectEqual(@clz(u8, @splat(64, @as(u8, 0b00000000))), @splat(64, @as(u4, 8)));
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try expectEqual(@clz(u128, @splat(64, @as(u128, 0xffffffffffffffff))), @splat(64, @as(u8, 64)));
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try expectEqual(@clz(u128, @splat(64, @as(u128, 0x10000000000000000))), @splat(64, @as(u8, 63)));
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}
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test "@ctz" {
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@ -141,14 +152,23 @@ test "@ctz" {
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}
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fn testCtz() !void {
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try expect(ctz(u8, 0b10100000) == 5);
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try expect(ctz(u8, 0b10001010) == 1);
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try expect(ctz(u8, 0b00000000) == 8);
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try expect(ctz(u16, 0b00000000) == 16);
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try expect(@ctz(u8, 0b10100000) == 5);
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try expect(@ctz(u8, 0b10001010) == 1);
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try expect(@ctz(u8, 0b00000000) == 8);
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try expect(@ctz(u16, 0b00000000) == 16);
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}
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fn ctz(comptime T: type, x: T) usize {
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return @ctz(T, x);
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test "@ctz vectors" {
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try testClzVectors();
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comptime try testClzVectors();
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}
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fn testCtzVectors() !void {
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@setEvalBranchQuota(10_000);
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try expectEqual(@ctz(u8, @splat(64, @as(u8, 0b10100000))), @splat(64, @as(u4, 5)));
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try expectEqual(@ctz(u8, @splat(64, @as(u8, 0b10001010))), @splat(64, @as(u4, 1)));
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try expectEqual(@ctz(u8, @splat(64, @as(u8, 0b00000000))), @splat(64, @as(u4, 8)));
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try expectEqual(@ctz(u16, @splat(64, @as(u16, 0b00000000))), @splat(64, @as(u5, 16)));
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}
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test "assignment operators" {
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