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stage1: update zig1.wasm

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As well as being necessary for the `CallingConvention` changes, this
update includes the following notable changes:

* Fix unlabeled `break` targeting the wrong scope in the presence of
  labeled continue, unblocking #21422
* Implement `@FieldType`
* Implement `@splat` on arrays

Signed-off-by: mlugg <mlugg@mlugg.co.uk>
This commit is contained in:
mlugg 2024-10-14 03:05:20 +01:00
parent 51706af908
commit 36405b9b43
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GPG Key ID: 3F5B7DCCBF4AF02E
2 changed files with 35 additions and 25 deletions
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60
stage1/zig.h
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@ -248,37 +248,55 @@ typedef char bool;
#if zig_has_builtin(trap)
#define zig_trap() __builtin_trap()
#elif _MSC_VER && (_M_IX86 || _M_X64)
#elif defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_X64))
#define zig_trap() __ud2()
#elif _MSC_VER
#define zig_trap() __fastfail(0)
#elif defined(__i386__) || defined(__x86_64__)
#define zig_trap() __asm__ volatile("ud2");
#elif defined(_MSC_VER)
#define zig_trap() __fastfail(7)
#elif defined(__thumb__)
#define zig_trap() __asm__ volatile("udf #0xfe")
#elif defined(__arm__) || defined(__aarch64__)
#define zig_trap() __asm__ volatile("udf #0");
#define zig_trap() __asm__ volatile("udf #0xfdee")
#elif defined(__loongarch__) || defined(__powerpc__)
#define zig_trap() __asm__ volatile(".word 0x0")
#elif defined(__mips__)
#define zig_trap() __asm__ volatile(".word 0x3d")
#elif defined(__riscv)
#define zig_trap() __asm__ volatile("unimp")
#elif defined(__s390__)
#define zig_trap() __asm__ volatile("j 0x2")
#elif defined(__sparc__)
#define zig_trap() __asm__ volatile("illtrap")
#elif defined(__i386__) || defined(__x86_64__)
#define zig_trap() __asm__ volatile("ud2")
#else
#include <stdlib.h>
#define zig_trap() abort()
#define zig_trap() zig_trap_unavailable
#endif
#if zig_has_builtin(debugtrap)
#define zig_breakpoint() __builtin_debugtrap()
#elif defined(_MSC_VER) || defined(__MINGW32__) || defined(__MINGW64__)
#define zig_breakpoint() __debugbreak()
#elif defined(__i386__) || defined(__x86_64__)
#define zig_breakpoint() __asm__ volatile("int $0x03");
#elif defined(__arm__)
#define zig_breakpoint() __asm__ volatile("bkpt #0");
#define zig_breakpoint() __asm__ volatile("bkpt #0x0")
#elif defined(__aarch64__)
#define zig_breakpoint() __asm__ volatile("brk #0");
#else
#include <signal.h>
#if defined(SIGTRAP)
#define zig_breakpoint() raise(SIGTRAP)
#define zig_breakpoint() __asm__ volatile("brk #0xf000")
#elif defined(__loongarch__)
#define zig_breakpoint() __asm__ volatile("break 0x0")
#elif defined(__mips__)
#define zig_breakpoint() __asm__ volatile("break")
#elif defined(__powerpc__)
#define zig_breakpoint() __asm__ volatile("trap")
#elif defined(__riscv)
#define zig_breakpoint() __asm__ volatile("ebreak")
#elif defined(__s390__)
#define zig_breakpoint() __asm__ volatile("j 0x6")
#elif defined(__sparc__)
#define zig_breakpoint() __asm__ volatile("ta 0x1")
#elif defined(__i386__) || defined(__x86_64__)
#define zig_breakpoint() __asm__ volatile("int $0x3")
#else
#define zig_breakpoint() zig_breakpoint_unavailable
#endif
#endif
#if zig_has_builtin(return_address) || defined(zig_gnuc)
#define zig_return_address() __builtin_extract_return_addr(__builtin_return_address(0))
@ -3592,7 +3610,6 @@ typedef enum memory_order zig_memory_order;
#define zig_atomicrmw_add_float zig_atomicrmw_add
#undef zig_atomicrmw_sub_float
#define zig_atomicrmw_sub_float zig_atomicrmw_sub
#define zig_fence(order) atomic_thread_fence(order)
#elif defined(__GNUC__)
typedef int zig_memory_order;
#define zig_memory_order_relaxed __ATOMIC_RELAXED
@ -3616,7 +3633,6 @@ typedef int zig_memory_order;
#define zig_atomic_load(res, obj, order, Type, ReprType) __atomic_load (obj, &(res), order)
#undef zig_atomicrmw_xchg_float
#define zig_atomicrmw_xchg_float zig_atomicrmw_xchg
#define zig_fence(order) __atomic_thread_fence(order)
#elif _MSC_VER && (_M_IX86 || _M_X64)
#define zig_memory_order_relaxed 0
#define zig_memory_order_acquire 2
@ -3637,11 +3653,6 @@ typedef int zig_memory_order;
#define zig_atomicrmw_max(res, obj, arg, order, Type, ReprType) res = zig_msvc_atomicrmw_max_ ##Type(obj, arg)
#define zig_atomic_store( obj, arg, order, Type, ReprType) zig_msvc_atomic_store_ ##Type(obj, arg)
#define zig_atomic_load(res, obj, order, Type, ReprType) res = zig_msvc_atomic_load_ ##order##_##Type(obj)
#if _M_X64
#define zig_fence(order) __faststorefence()
#else
#define zig_fence(order) zig_msvc_atomic_barrier()
#endif
/* TODO: _MSC_VER && (_M_ARM || _M_ARM64) */
#else
#define zig_memory_order_relaxed 0
@ -3663,7 +3674,6 @@ typedef int zig_memory_order;
#define zig_atomicrmw_max(res, obj, arg, order, Type, ReprType) zig_atomics_unavailable
#define zig_atomic_store( obj, arg, order, Type, ReprType) zig_atomics_unavailable
#define zig_atomic_load(res, obj, order, Type, ReprType) zig_atomics_unavailable
#define zig_fence(order) zig_fence_unavailable
#endif
#if _MSC_VER && (_M_IX86 || _M_X64)

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