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stage2: change max int align from 8 to 16 for more ISAs
These targets now have a similar disagreement with LLVM about the alignment of 128-bit integers as x86_64: * riscv64 * powerpc64 * powerpc64le * mips64 * mips64el * sparcv9 See #2987
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@ -1787,18 +1787,12 @@ pub const Target = struct {
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.hexagon,
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.powerpc,
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.powerpcle,
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.powerpc64,
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.powerpc64le,
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.r600,
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.amdgcn,
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.riscv32,
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.riscv64,
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.sparc,
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.sparcv9,
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.sparcel,
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.s390x,
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.lanai,
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@ -1812,10 +1806,20 @@ pub const Target = struct {
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},
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// For x86_64, LLVMABIAlignmentOfType(i128) reports 8. However I think 16
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// is a better number because of two reasons:
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// is a better number for two reasons:
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// 1. Better machine code when loading into SIMD register.
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// 2. The C ABI wants 16 for extern structs.
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// 3. 16-byte cmpxchg needs 16-byte alignment.
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// Same logic for riscv64, powerpc64, mips64, sparcv9.
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.x86_64,
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.riscv64,
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.powerpc64,
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.powerpc64le,
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.mips64,
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.mips64el,
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.sparcv9,
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// Even LLVMABIAlignmentOfType(i128) agrees on these targets.
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.aarch64,
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.aarch64_be,
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.aarch64_32,
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@ -1825,11 +1829,9 @@ pub const Target = struct {
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.nvptx64,
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=> 16,
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// Below this comment are unverified and I have chosen a number
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// based on ptrBitWidth.
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.spu_2 => 2,
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// Below this comment are unverified but based on the fact that C requires
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// int128_t to be 16 bytes aligned, it's a safe default.
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.spu_2,
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.csky,
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.arc,
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.m68k,
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@ -1843,8 +1845,6 @@ pub const Target = struct {
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.renderscript32,
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.spirv32,
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.shave,
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=> 4,
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.le64,
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.amdil64,
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.hsail64,
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@ -1852,7 +1852,7 @@ pub const Target = struct {
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.renderscript64,
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.ve,
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.spirv64,
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=> 8,
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=> 16,
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};
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}
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};
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@ -77,18 +77,12 @@ test "alignment and size of structs with 128-bit fields" {
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.hexagon,
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.powerpc,
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.powerpcle,
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.powerpc64,
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.powerpc64le,
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.r600,
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.amdgcn,
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.riscv32,
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.riscv64,
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.sparc,
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.sparcv9,
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.sparcel,
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.s390x,
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.lanai,
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@ -134,6 +128,12 @@ test "alignment and size of structs with 128-bit fields" {
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},
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},
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.mips64,
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.mips64el,
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.powerpc64,
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.powerpc64le,
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.riscv64,
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.sparcv9,
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.x86_64,
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.aarch64,
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.aarch64_be,
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