Nixyri/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2024-11-10 14:11:59 +00:00
Code Issues Packages Projects Releases Wiki Activity

tricore CFSR wrong space

Browse Source
This commit is contained in:
mumbel 2020-03-14 23:23:39 -05:00
parent f1782a7629
commit ff2f6d3835
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Ghidra/Processors/tricore/data/languages/tricore.sinc
View File

@ -5042,13 +5042,13 @@ macro multiply_u_u(mres0, rega, regb, n) {
# MFCR D[c], const16 (RLC)
:mfcr Rd2831,const1227Z is PCPMode=0 & ( op0007=0x4d & op0811=0x0 ; Rd2831 ) & const1227Z
{
Rd2831 = *[register]:4 const1227Z;
Rd2831 = *[ram]:4 const1227Z;
}
@if defined(TRICORE_V2)
:mffr Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x1d1
{
Rd2831 = *[register]:4 Rd0811;
Rd2831 = *[ram]:4 Rd0811;
}
@endif
@ -6364,13 +6364,13 @@ macro multiply_u_u(mres0, rega, regb, n) {
# MTCR const16, D[a] (RLC)
:mtcr const1227Z,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xcd ; op2831=0x0 ) & const1227Z
{
*[register]:4 const1227Z = Rd0811;
*[ram]:4 const1227Z = Rd0811;
}
@if defined(TRICORE_V2)
:mtfr Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; op1631=0x1c1
{
*[register]:4 Rd1215 = Rd0811;
*[ram]:4 Rd1215 = Rd0811;
}
@endif